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amd/vpelib: Fix cost profiling support

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Add additional changes/logs to profile total register writes.

Signed-off-by: Iswara Nagulendran <Iswara.Nagulendran@amd.com>
Reviewed-by: Roy Chan <Roy.Chan@amd.com>
Reviewed-by: Jesse Agate <Jesse.Agate@amd.com>
Acked-by: Chuanyu Tseng <Chuanyu.Tseng@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36433>
This commit is contained in:
Nagulendran, Iswara 2025-06-30 09:25:20 -04:00 • committed by Marge Bot
parent 02beb30d6b
commit 6088dbe05c
4 changed files with 51 additions and 25 deletions
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52
src/amd/vpelib/src/chip/vpe10/vpe10_cm_common.c
View file

@ -527,18 +527,22 @@ bool vpe10_cm_helper_translate_curve_to_degamma_hw_format(
#define REG_SET_CM(reg_offset, init_val, field, val) \
do { \
config_writer_fill( \
config_writer, VPEC_FIELD_VALUE(VPE_DIR_CFG_PKT_DATA_SIZE, 0) | \
VPEC_FIELD_VALUE(VPE_DIR_CFG_PKT_REGISTER_OFFSET, reg_offset)); \
struct vpep_direct_config_packet packet; \
packet.bits.INC = 0; \
packet.bits.VPEP_CONFIG_DATA_SIZE = 0; \
packet.bits.VPEP_CONFIG_REGISTER_OFFSET = reg_offset; \
config_writer_fill_direct_config_packet_header(config_writer, &packet); \
config_writer_fill(config_writer, \
((init_val & ~(REG_FIELD_MASK_CM(field))) | REG_FIELD_VALUE_CM(field, val))); \
} while (0)
#define REG_SET_2_CM(reg_offset, init_val, f1, v1, f2, v2) \
do { \
config_writer_fill( \
config_writer, VPEC_FIELD_VALUE(VPE_DIR_CFG_PKT_DATA_SIZE, 0) | \
VPEC_FIELD_VALUE(VPE_DIR_CFG_PKT_REGISTER_OFFSET, reg_offset)); \
struct vpep_direct_config_packet packet; \
packet.bits.INC = 0; \
packet.bits.VPEP_CONFIG_DATA_SIZE = 0; \
packet.bits.VPEP_CONFIG_REGISTER_OFFSET = reg_offset; \
config_writer_fill_direct_config_packet_header(config_writer, &packet); \
config_writer_fill( \
config_writer, ((init_val & ~(REG_FIELD_MASK_CM(f1)) & ~(REG_FIELD_MASK_CM(f2))) | \
REG_FIELD_VALUE_CM(f1, v1) | REG_FIELD_VALUE_CM(f2, v2))); \
@ -546,9 +550,11 @@ bool vpe10_cm_helper_translate_curve_to_degamma_hw_format(
#define REG_SET_4_CM(reg_offset, init_val, f1, v1, f2, v2, f3, v3, f4, v4) \
do { \
config_writer_fill( \
config_writer, VPEC_FIELD_VALUE(VPE_DIR_CFG_PKT_DATA_SIZE, 0) | \
VPEC_FIELD_VALUE(VPE_DIR_CFG_PKT_REGISTER_OFFSET, reg_offset)); \
struct vpep_direct_config_packet packet; \
packet.bits.INC = 0; \
packet.bits.VPEP_CONFIG_DATA_SIZE = 0; \
packet.bits.VPEP_CONFIG_REGISTER_OFFSET = reg_offset; \
config_writer_fill_direct_config_packet_header(config_writer, &packet); \
config_writer_fill( \
config_writer, ((init_val & ~(REG_FIELD_MASK_CM(f1)) & ~(REG_FIELD_MASK_CM(f2)) & \
~(REG_FIELD_MASK_CM(f3)) & ~(REG_FIELD_MASK_CM(f4))) | \
@ -611,10 +617,12 @@ void vpe10_cm_helper_program_gamcor_xfer_func(struct config_writer *config_write
// program all the *GAM_RAM?_REGION_start ~ region_end regs in one VPEP_DIRECT_CONFIG packet
// with auto inc
config_writer_fill(
config_writer, VPEC_FIELD_VALUE(VPE_DIR_CFG_PKT_DATA_SIZE, packet_data_size - 1) |
VPEC_FIELD_VALUE(VPE_DIR_CFG_PKT_REGISTER_OFFSET, reg->region_start) |
0x01); // auto increase on
struct vpep_direct_config_packet packet;
packet.bits.INC = 1;
packet.bits.VPEP_CONFIG_DATA_SIZE = packet_data_size - 1;
packet.bits.VPEP_CONFIG_REGISTER_OFFSET = reg->region_start;
config_writer_fill_direct_config_packet_header(config_writer, &packet);
for (reg_region_cur = reg->region_start; reg_region_cur <= reg->region_end; reg_region_cur++) {
@ -644,9 +652,12 @@ void vpe10_cm_helper_program_pwl(struct config_writer *config_writer,
uint32_t lut_data = 0;
// For LUT, we keep write the same address with entire LUT data, so do not set INC bit
config_writer_fill(
config_writer, VPEC_FIELD_VALUE(VPE_DIR_CFG_PKT_DATA_SIZE, num) |
VPEC_FIELD_VALUE(VPE_DIR_CFG_PKT_REGISTER_OFFSET, lut_data_reg_offset));
struct vpep_direct_config_packet packet;
packet.bits.INC = 0;
packet.bits.VPEP_CONFIG_DATA_SIZE = num;
packet.bits.VPEP_CONFIG_REGISTER_OFFSET = lut_data_reg_offset;
config_writer_fill_direct_config_packet_header(config_writer, &packet);
for (i = 0; i < num; i++) {
switch (channel) {
@ -673,11 +684,12 @@ void vpe10_cm_helper_program_color_matrices(struct config_writer *config_writer,
uint32_t cur_csc_reg;
unsigned int i = 0;
uint16_t packet_data_size = (uint16_t)((reg->csc_c33_c34 - reg->csc_c11_c12 + 1));
struct vpep_direct_config_packet packet;
config_writer_fill(
config_writer, VPEC_FIELD_VALUE(VPE_DIR_CFG_PKT_DATA_SIZE, packet_data_size - 1) |
VPEC_FIELD_VALUE(VPE_DIR_CFG_PKT_REGISTER_OFFSET, reg->csc_c11_c12) |
0x01); // auto increase on
packet.bits.INC = 1;
packet.bits.VPEP_CONFIG_DATA_SIZE = packet_data_size - 1;
packet.bits.VPEP_CONFIG_REGISTER_OFFSET = reg->csc_c11_c12;
config_writer_fill_direct_config_packet_header(config_writer, &packet);
for (cur_csc_reg = reg->csc_c11_c12; cur_csc_reg <= reg->csc_c33_c34; cur_csc_reg++) {

10
src/amd/vpelib/src/core/config_writer.c
View file

@ -208,7 +208,12 @@ void config_writer_fill_direct_config_packet_header(
}
#ifdef VPE_REGISTER_PROFILE
writer->register_count += packet->bits.VPEP_CONFIG_DATA_SIZE + 1;
writer->total_register_count += packet->bits.VPEP_CONFIG_DATA_SIZE + 1;
if (packet->bits.VPEP_CONFIG_DATA_SIZE == 0) {
writer->nonBurstMode_register_count++;
} else {
writer->burstMode_register_count += packet->bits.VPEP_CONFIG_DATA_SIZE + 1;
}
#endif
cmd_space = (uint32_t *)(uintptr_t)writer->buf->cpu_va;
*cmd_space++ = packet->u32all;
@ -245,7 +250,8 @@ void config_writer_fill_direct_config_packet(
}
#ifdef VPE_REGISTER_PROFILE
writer->register_count++;
writer->total_register_count++;
writer->nonBurstMode_register_count++;
#endif
cmd_space = (uint32_t *)(uintptr_t)writer->buf->cpu_va;
*cmd_space++ = packet->u32all; // Write header

4
src/amd/vpelib/src/core/inc/config_writer.h
View file

@ -93,7 +93,9 @@ struct config_writer {
enum vpe_status status;
#ifdef VPE_REGISTER_PROFILE
uint64_t register_count;
uint64_t total_register_count;
uint64_t burstMode_register_count;
uint64_t nonBurstMode_register_count;
uint64_t total_config_count;
uint64_t reused_config_count;
#endif

10
src/amd/vpelib/src/core/vpelib.c
View file

@ -713,7 +713,9 @@ enum vpe_status vpe_build_commands(
vpe_priv = container_of(vpe, struct vpe_priv, pub);
#ifdef VPE_REGISTER_PROFILE
vpe_priv->config_writer.register_count = 0;
vpe_priv->config_writer.total_register_count = 0;
vpe_priv->config_writer.burstMode_register_count = 0;
vpe_priv->config_writer.nonBurstMode_register_count = 0;
vpe_priv->config_writer.total_config_count = 0;
vpe_priv->config_writer.reused_config_count = 0;
#endif
@ -867,7 +869,11 @@ enum vpe_status vpe_build_commands(
#endif
}
#ifdef VPE_REGISTER_PROFILE
vpe_log("Total Registers Accessed: % d\n", vpe_priv->config_writer.register_count);
vpe_log("Total Registers Accessed: % d\n", vpe_priv->config_writer.total_register_count);
vpe_log("Burst Mode Registers Accessed: % d\n",
vpe_priv->config_writer.burstMode_register_count);
vpe_log("Non-Burst Mode Registers Accessed: % d\n",
vpe_priv->config_writer.nonBurstMode_register_count);
vpe_log("Total Config Descriptors: % d\n", vpe_priv->config_writer.total_config_count);
vpe_log("Total Re-used Config Descriptors: % d\n", vpe_priv->config_writer.reused_config_count);
#endif