mesa/src/amd
Samuel Pitoiset 874bc09537 radv: reserve more CS space when executing DGC calls
This can trigger an assert otherwise. The space reserved before
executing DGC IBs is an arbitrary number which should be large enough
in all cases.

Found this while implementing descriptor heap.

Cc: mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37681>
2025-10-06 06:28:18 +00:00
..
addrlib addrlib: __debugbreak only present on Windows and from intrin.h 2025-08-07 07:47:42 +00:00
ci Revert "radv/ci: document recent unexpected failures on TAHITI" 2025-10-03 13:37:16 +02:00
common ac/parse_ib: Update vcn ib parser to include missing commands 2025-10-03 14:44:07 +00:00
compiler aco: fix debug info offset 2025-10-02 13:38:56 +00:00
drm-shim amd/drm-shim: add navi33 2025-08-19 12:15:01 +00:00
gmlib meson: Relax -Wmaybe-uninitialized errors 2025-09-16 06:16:20 +00:00
lanczoslib meson: Relax -Wmaybe-uninitialized errors 2025-09-16 06:16:20 +00:00
llvm ac/llvm: remove unused ballot size 2025-09-14 13:21:20 +00:00
registers amd: Rename GFX1103_R1/R2 to PHOENIX/2 2024-11-20 02:14:40 +00:00
vpelib amd/vpelib: add FL capabilitie and lut container size 2025-09-22 10:37:22 +00:00
vulkan radv: reserve more CS space when executing DGC calls 2025-10-06 06:28:18 +00:00
meson.build radeonsi/vpe: enhance scaling quality 2025-06-12 07:44:26 +00:00