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amd/drm-shim: add navi33

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Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36813>
This commit is contained in:
Samuel Pitoiset 2025-08-18 13:37:21 +02:00 • committed by Marge Bot
parent 9eed511337
commit 790d59e01d
1 changed files with 131 additions and 0 deletions
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131
src/amd/drm-shim/amdgpu_devices.c
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@ -1449,6 +1449,137 @@ const struct amdgpu_device amdgpu_devices[] = {
},
},
},
{
.name = "navi33",
.radeon_family = CHIP_NAVI33,
.hw_ip_gfx = {
.hw_ip_version_major = 11,
.hw_ip_version_minor = 0,
.capabilities_flags = UINT64_C(0),
.ib_start_alignment = 32,
.ib_size_alignment = 32,
.available_rings = 0x1,
.ip_discovery_version = 0xb0002,
.userq_num_slots = 0x0,
},
.hw_ip_compute = {
.hw_ip_version_major = 11,
.hw_ip_version_minor = 0,
.capabilities_flags = UINT64_C(0),
.ib_start_alignment = 32,
.ib_size_alignment = 32,
.available_rings = 0xf,
.ip_discovery_version = 0xb0002,
.userq_num_slots = 0x0,
},
.fw_gfx_me = {
.ver = 2390,
.feature = 29,
},
.fw_gfx_pfp = {
.ver = 2530,
.feature = 29,
},
.fw_gfx_mec = {
.ver = 2600,
.feature = 29,
},
.mmr_regs = {
0x263e, 0xffffffff, 0x00000343,
},
.mmr_reg_count = 1,
.dev = {
.device_id = 0x7480,
.chip_rev = 0x00,
.external_rev = 0x10,
.pci_rev = 0xcf,
.family = AMDGPU_FAMILY_GC_11_0_0,
.num_shader_engines = 2,
.num_shader_arrays_per_engine = 2,
.gpu_counter_freq = 100000,
.max_engine_clock = UINT64_C(2356000),
.max_memory_clock = UINT64_C(1124000),
.cu_active_number = 32,
.cu_ao_mask = 0x0,
.cu_bitmap = {
{ 0xff, 0xff, 0x0, 0x0, },
{ 0xff, 0xff, 0x0, 0x0, },
{ 0x0, 0x0, 0x0, 0x0, },
{ 0x0, 0x0, 0x0, 0x0, },
},
.enabled_rb_pipes_mask = 0xff,
.num_rb_pipes = 8,
.num_hw_gfx_contexts = 8,
.pcie_gen = 3,
.ids_flags = UINT64_C(0x8),
.virtual_address_offset = UINT64_C(0x10000),
.virtual_address_max = UINT64_C(0x800000000000),
.virtual_address_alignment = 4096,
.pte_fragment_size = 2097152,
.gart_page_size = 4096,
.ce_ram_size = 0,
.vram_type = 9,
.vram_bit_width = 128,
.vce_harvest_config = 0,
.gc_double_offchip_lds_buf = 0,
.prim_buf_gpu_addr = UINT64_C(0),
.pos_buf_gpu_addr = UINT64_C(0),
.cntl_sb_buf_gpu_addr = UINT64_C(0),
.param_buf_gpu_addr = UINT64_C(0),
.prim_buf_size = 0,
.pos_buf_size = 0,
.cntl_sb_buf_size = 0,
.param_buf_size = 0,
.wave_front_size = 32,
.num_shader_visible_vgprs = 1024,
.num_cu_per_sh = 8,
.num_tcc_blocks = 8,
.gs_vgt_table_depth = 32,
.gs_prim_buffer_depth = 1792,
.max_gs_waves_per_vgt = 32,
.pcie_num_lanes = 8,
.cu_ao_bitmap = {
{ 0x0, 0x0, 0x0, 0x0, },
{ 0x0, 0x0, 0x0, 0x0, },
{ 0x0, 0x0, 0x0, 0x0, },
{ 0x0, 0x0, 0x0, 0x0, },
},
.high_va_offset = UINT64_C(0xffff800000000000),
.high_va_max = UINT64_C(0xffffffffffbfe000),
.pa_sc_tile_steering_override = 0,
.tcc_disabled_mask = UINT64_C(0),
.min_engine_clock = UINT64_C(255000),
.min_memory_clock = UINT64_C(96000),
.tcp_cache_size = 32,
.num_sqc_per_wgp = 1,
.sqc_data_cache_size = 16,
.sqc_inst_cache_size = 32,
.gl1c_cache_size = 256,
.gl2c_cache_size = 2048,
.mall_size = UINT64_C(0),
.enabled_rb_pipes_mask_hi = 0,
},
.mem = {
.vram = {
.total_heap_size = UINT64_C(8573157376),
.usable_heap_size = UINT64_C(8527036416),
.heap_usage = UINT64_C(72122368),
.max_allocation = UINT64_C(6395277312),
},
.cpu_accessible_vram = {
.total_heap_size = UINT64_C(8573157376),
.usable_heap_size = UINT64_C(8527036416),
.heap_usage = UINT64_C(72122368),
.max_allocation = UINT64_C(6395277312),
},
.gtt = {
.total_heap_size = UINT64_C(16757649408),
.usable_heap_size = UINT64_C(16742203392),
.heap_usage = UINT64_C(32239616),
.max_allocation = UINT64_C(12556652544),
},
},
},
{
.name = "navi21",
.radeon_family = CHIP_NAVI21,