Georg Lehmann 67d03033e4 radv: remove separate discard peephole select ... This allows removing control flow with a mix of alu and discard. Foz-DB Navi21 (ignore throughput/latency because of single iteration loops): Totals from 1251 (1.58% of 79377) affected shaders: Instrs: 1459317 -> 1457751 (-0.11%); split: -0.14%, +0.04% CodeSize: 8350856 -> 8352408 (+0.02%); split: -0.03%, +0.05% VGPRs: 53056 -> 53328 (+0.51%) SpillSGPRs: 66 -> 62 (-6.06%) Latency: 19784315 -> 15649290 (-20.90%); split: -21.26%, +0.36% InvThroughput: 4080229 -> 3122717 (-23.47%); split: -23.56%, +0.09% VClause: 29293 -> 29294 (+0.00%); split: -0.01%, +0.01% SClause: 56060 -> 55941 (-0.21%); split: -0.23%, +0.02% Copies: 129794 -> 127880 (-1.47%); split: -1.51%, +0.04% Branches: 52039 -> 51275 (-1.47%); split: -1.47%, +0.01% PreSGPRs: 50221 -> 50024 (-0.39%); split: -0.64%, +0.25% PreVGPRs: 44058 -> 44053 (-0.01%); split: -0.02%, +0.00% VALU: 984915 -> 984993 (+0.01%); split: -0.01%, +0.02% SALU: 177126 -> 177184 (+0.03%); split: -0.62%, +0.65% SMEM: 79565 -> 79525 (-0.05%) Reviewed-by: Daniel Schürmann <daniel@schuermann.dev> Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33590>		2025-02-20 21:59:18 +00:00
..
addrlib	amd: update addrlib	2024-12-26 21:02:21 +00:00
ci	radv/ci: Don't start X11 for ANGLE	2025-02-17 11:31:01 +00:00
common	ac/nir: set higher alignment for some swizzled store_buffer_amd	2025-02-18 12:31:19 +00:00
compiler	amd: switch to nir_metadata_divergence	2025-02-13 10:08:43 +00:00
drm-shim	amd/drm-shim: add GFX1150 support	2024-08-13 13:17:17 +00:00
llvm	ac: Don't include full nir.h anymore.	2025-02-12 22:33:07 +01:00
registers	amd: Rename GFX1103_R1/R2 to PHOENIX/2	2024-11-20 02:14:40 +00:00
vpelib	amd/vpelib: Shaper Refactor	2024-12-26 01:23:59 +00:00
vulkan	radv: remove separate discard peephole select	2025-02-20 21:59:18 +00:00
meson.build	build: pass licensing information in SPDX form	2024-06-29 12:42:49 -07:00