Rohan Garg 9baa57158d intel/genxml: update PIPE_CONTROL so that we can decode it on the CCS ... Signed-off-by: Rohan Garg <rohan.garg@intel.com> Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28013>		2024-03-06 14:37:11 +00:00
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blorp	anv, blorp: Set COMPUTE_WALKER Message SIMD field	2024-03-06 10:58:27 +00:00
ci	ci/intel: split asus-cx9400-volteer into acer-cp514-2h-11{30,60}g7-volteer	2024-03-06 01:52:49 +00:00
common	intel: Use _brw suffix for genX headers that rely on brw	2024-02-24 00:24:32 +00:00
compiler	intel/brw: Unindent code after previous change	2024-03-05 12:03:31 +00:00
decoder	intel/decoder: Add ELK support	2024-02-24 00:24:31 +00:00
dev	intel/dev: declare workarounds required by ATSM platforms	2024-03-05 22:49:14 -08:00
ds	intel: Add missing dependencies on blorp	2024-02-16 00:08:42 +00:00
genxml	intel/genxml: update PIPE_CONTROL so that we can decode it on the CCS	2024-03-06 14:37:11 +00:00
isl	isl: Pick a better initial state for zeroed MCS	2024-03-01 19:40:03 +00:00
nullhw-layer	intel/nullhw: Fix 32bits compilation warnings	2024-02-28 23:37:43 +00:00
perf	intel: Remove unused ALIGN macro	2023-12-07 02:30:53 +00:00
shaders	intel-clc: Use correct set of nir_options when building for Gfx8	2024-02-24 00:24:32 +00:00
tools	intel/meson: Add dependencies for brw and elk	2024-02-29 23:08:16 +00:00
vulkan	anv, blorp: Set COMPUTE_WALKER Message SIMD field	2024-03-06 10:58:27 +00:00
vulkan_hasvk	treewide: Remove vulkan/runtime vulkan/util prefix in include path	2024-03-05 19:05:00 +00:00
meson.build	intel: Only build shaders with anv and iris	2024-02-21 20:53:36 +00:00