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intel/genxml: update PIPE_CONTROL so that we can decode it on the CCS

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Signed-off-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28013>
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Rohan Garg 2024-03-06 14:27:56 +01:00 • committed by Marge Bot
parent 3b28ba8239
commit 9baa57158d
1 changed files with 1 additions and 1 deletions
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2
src/intel/genxml/gen20.xml
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@ -813,7 +813,7 @@
<field name="Command SubType" start="27" end="28" type="uint" default="1" />
<field name="Command Type" start="29" end="31" type="uint" default="3" />
</instruction>
<instruction name="PIPE_CONTROL" bias="2" length="6" engine="render">
<instruction name="PIPE_CONTROL" bias="2" length="6" engine="render|compute">
<field name="DWord Length" start="0" end="7" type="uint" default="4" />
<field name="HDC Pipeline Flush Enable" start="9" end="9" type="bool" />
<field name="L3 Read Only Cache Invalidation Enable" start="10" end="10" type="bool" />