Sagar Ghuge c0849a0697 intel/genxml: Add Un-Typed Data-Port Cache Flush field to pipe control ... Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14676>		2022-01-23 23:46:54 -08:00
..
blorp	anv,blorp,crocus,i965,iris: Use devinfo->max_threads_per_psd for gfx8+	2022-01-19 00:29:35 +00:00
ci	anv/ci: Test with deqp-vk on Tiger Lake	2022-01-07 13:33:32 +00:00
common	intel/gem: Return length from intel_i915_query_alloc	2022-01-19 00:29:35 +00:00
compiler	intel/fs: Fix gl_FrontFacing optimization on Gfx12+	2022-01-20 22:37:18 +00:00
dev	intel/dev: fix ppipe_mask computation	2022-01-19 10:22:36 +00:00
ds	iris: utrace/perfetto support	2022-01-14 20:17:44 +00:00
genxml	intel/genxml: Add Un-Typed Data-Port Cache Flush field to pipe control	2022-01-23 23:46:54 -08:00
isl	intel/isl: Allow creating MCS in Tile4 memory	2022-01-21 20:38:05 +00:00
nullhw-layer	intel/nullhw: fix build	2021-03-26 20:12:40 +00:00
perf	intel/perf: use a function to do common allocations	2022-01-20 06:41:17 +00:00
tools	intel: remove chipset_id	2022-01-13 03:09:36 +00:00
vulkan	anv: add helper methods related to enabling CCS for external images	2022-01-20 11:37:29 -08:00
Makefile.perf.am	intel: Rename GEN_PERF prefix to INTEL_PERF in build files	2021-04-20 20:06:34 +00:00
meson.build	anv: add perfetto source	2022-01-14 20:17:44 +00:00