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intel/genxml: Add Un-Typed Data-Port Cache Flush field to pipe control

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Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14676>
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Sagar Ghuge 2021-08-23 18:05:50 -07:00 • committed by Caio Oliveira
parent 08429da731
commit c0849a0697
1 changed files with 1 additions and 0 deletions
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src/intel/genxml/gen125.xml
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@ -6740,6 +6740,7 @@
<instruction name="PIPE_CONTROL" bias="2" length="6" engine="render">
<field name="DWord Length" start="0" end="7" type="uint" default="4"/>
<field name="HDC Pipeline Flush Enable" start="9" end="9" type="bool"/>
<field name="Untyped Data Port Cache Flush Enable" start="11" end="11" type="bool"/>
<field name="3D Command Sub Opcode" start="16" end="23" type="uint" default="0"/>
<field name="3D Command Opcode" start="24" end="26" type="uint" default="2"/>
<field name="Command SubType" start="27" end="28" type="uint" default="3"/>