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intel/fs: Fix gl_FrontFacing optimization on Gfx12+

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It's not obvious why the (gl_FrontFacing ? -1.0 : 1.0) case was handled
different for Gfx12+ than for previous generations, and it's not
correct.  It tries to negate the result as an integer, and it does this
before the mask operation that clears the other bits in the value.

When we eventually support dual-SIMD8 dispatch, the other front-facing
bit is in g1.6 at bit 15, so similar code should be possible there.

Reviewed-by: Matt Turner <mattst88@gmail.com>
Fixes: c92fb60007 ("intel/fs/gen12: Implement gl_FrontFacing on gen12+.")
Closes: #5876
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14625>
This commit is contained in:
Ian Romanick 2022-01-18 16:30:37 -08:00 • committed by Marge Bot
parent 4aaedc20c1
commit 945fb51fb5
1 changed files with 5 additions and 6 deletions
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11
src/intel/compiler/brw_fs_nir.cpp
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@ -562,17 +562,16 @@ fs_visitor::optimize_frontfacing_ternary(nir_alu_instr *instr,
/* For (gl_FrontFacing ? 1.0 : -1.0), emit:
*
* or(8) tmp.1<2>W g0.0<0,1,0>W 0x00003f80W
* or(8) tmp.1<2>W g1.1<0,1,0>W 0x00003f80W
* and(8) dst<1>D tmp<8,8,1>D 0xbf800000D
*
* and negate the result for (gl_FrontFacing ? -1.0 : 1.0).
* and negate g1.1<0,1,0>W for (gl_FrontFacing ? -1.0 : 1.0).
*/
if (value1 == -1.0f)
g1.negate = true;
bld.OR(subscript(tmp, BRW_REGISTER_TYPE_W, 1),
g1, brw_imm_uw(0x3f80));
if (value1 == -1.0f)
bld.MOV(tmp, negate(tmp));
} else if (devinfo->ver >= 6) {
/* Bit 15 of g0.0 is 0 if the polygon is front facing. */
fs_reg g0 = fs_reg(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_W));