Alyssa Rosenzweig 079e9ae606 treewide: use BITSET_*_COUNT ... Mix of Coccinelle patch, manual fix ups, sed, etc. Probably best to review the diff as-if hand written: Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com> Reviewed-by: Mel Henning <mhenning@darkrefraction.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38955>		2025-12-16 17:42:10 +00:00
..
addrlib	amd: rename most GFX115x definitions for released chips	2025-12-03 13:29:07 +00:00
ci	ci: Uprev GL & GLES CTS	2025-12-10 11:31:33 +00:00
common	radv: Use zero-filled BO for GFX6 and GFX10 null index buffer bug	2025-12-15 21:03:19 +00:00
compiler	treewide: use BITSET_*_COUNT	2025-12-16 17:42:10 +00:00
drm-shim	amd: rename most GFX115x definitions for released chips	2025-12-03 13:29:07 +00:00
gmlib	meson: Relax -Wmaybe-uninitialized errors	2025-09-16 06:16:20 +00:00
lanczoslib	meson: Relax -Wmaybe-uninitialized errors	2025-09-16 06:16:20 +00:00
llvm	ac/llvm/gfx6: move mrtz writemask workaround to ac_build_export	2025-12-12 17:00:51 +00:00
registers	amd: Rename GFX1103_R1/R2 to PHOENIX/2	2024-11-20 02:14:40 +00:00
vpelib	amd/vpelib: add FL capabilitie and lut container size	2025-09-22 10:37:22 +00:00
vulkan	radv: rename RADEON_FLAG_VA_UNCACHED to RADEON_FLAG_GL2_BYPASS	2025-12-16 07:17:08 +00:00
meson.build	radv/tests: require drm-shim and use it instead of RADV_FORCE_FAMILY	2025-11-19 07:11:05 +00:00