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treewide: use BITSET_*_COUNT

Browse source 
Mix of Coccinelle patch, manual fix ups, sed, etc. Probably best to review the diff
as-if hand written:

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Reviewed-by: Mel Henning <mhenning@darkrefraction.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38955>
This commit is contained in:
Alyssa Rosenzweig 2025-12-15 14:15:37 -05:00 • committed by Marge Bot
parent 593517a53a
commit 079e9ae606
26 changed files with 92 additions and 113 deletions
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3
src/amd/compiler/aco_insert_NOPs.cpp
View file

@ -464,10 +464,9 @@ set_bitset_range(BITSET_WORD* words, unsigned start, unsigned size)
bool
test_bitset_range(BITSET_WORD* words, unsigned start, unsigned size)
{
unsigned end = start + size - 1;
unsigned start_mod = start % BITSET_WORDBITS;
if (start_mod + size <= BITSET_WORDBITS) {
return BITSET_TEST_RANGE(words, start, end);
return BITSET_TEST_COUNT(words, start, size);
} else {
unsigned first_size = BITSET_WORDBITS - start_mod;
return test_bitset_range(words, start, BITSET_WORDBITS - start_mod) ||

2
src/amd/compiler/instruction_selection/aco_isel_helpers.cpp
View file

@ -939,7 +939,7 @@ find_param_regs(Program* program, const ABI& abi, callee_info& info,
if (next_reg) {
param_demand += Temp(0, params.back().rc);
params.back().dst_info->def.setPrecolored(*next_reg);
BITSET_CLEAR_RANGE(regs, next_reg->reg(), next_reg->reg() + params.back().rc.size() - 1);
BITSET_CLEAR_COUNT(regs, next_reg->reg(), params.back().rc.size());
if (!params.back().is_system_param) {
++info.reg_param_count;
if (discardable)

12
src/asahi/compiler/agx_compile.c
View file

@ -184,7 +184,7 @@ gather_cf(nir_builder *b, nir_intrinsic_instr *intr, void *data)
unsigned location = sem.location + nir_src_as_uint(*offset);
unsigned start_comp = (location * 4) + nir_intrinsic_component(intr);
BITSET_SET_RANGE(set, start_comp, start_comp + nr - 1);
BITSET_SET_COUNT(set, start_comp, nr);
} else {
unsigned start_comp = (sem.location * 4) + nir_intrinsic_component(intr);
bool compact = sem.location == VARYING_SLOT_CLIP_DIST0 ||
@ -197,8 +197,7 @@ gather_cf(nir_builder *b, nir_intrinsic_instr *intr, void *data)
nr = stride;
for (unsigned i = 0; i < sem.num_slots; ++i) {
BITSET_SET_RANGE(set, start_comp + (i * stride),
start_comp + (i * stride) + nr - 1);
BITSET_SET_COUNT(set, start_comp + (i * stride), nr);
}
}
@ -242,10 +241,9 @@ assign_coefficient_regs(nir_shader *nir, struct agx_varyings_fs *var)
static_assert(VARYING_SLOT_POS == 0, "special and handled first");
for (unsigned i = VARYING_SLOT_POS + 1; i < VARYING_SLOT_MAX; ++i) {
bool smooth = BITSET_TEST_RANGE(info.smooth, i * 4, (i * 4) + 3);
bool flat = BITSET_TEST_RANGE(info.flat, i * 4, (i * 4) + 3);
bool noperspective =
BITSET_TEST_RANGE(info.noperspective, i * 4, (i * 4) + 3);
bool smooth = BITSET_TEST_COUNT(info.smooth, i * 4, 4);
bool flat = BITSET_TEST_COUNT(info.flat, i * 4, 4);
bool noperspective = BITSET_TEST_COUNT(info.noperspective, i * 4, 4);
if (!(smooth || flat || noperspective))
continue;

12
src/asahi/compiler/agx_insert_waits.c
View file

@ -65,8 +65,7 @@ agx_insert_waits_local(agx_context *ctx, agx_block *block)
unsigned nr_read = agx_index_size_16(I->src[s]);
for (unsigned slot = 0; slot < ARRAY_SIZE(slots); ++slot) {
if (BITSET_TEST_RANGE(slots[slot].writes, I->src[s].value,
I->src[s].value + nr_read - 1))
if (BITSET_TEST_COUNT(slots[slot].writes, I->src[s].value, nr_read))
wait_mask |= BITSET_BIT(slot);
}
}
@ -78,8 +77,8 @@ agx_insert_waits_local(agx_context *ctx, agx_block *block)
unsigned nr_writes = agx_index_size_16(I->dest[d]);
for (unsigned slot = 0; slot < ARRAY_SIZE(slots); ++slot) {
if (BITSET_TEST_RANGE(slots[slot].writes, I->dest[d].value,
I->dest[d].value + nr_writes - 1))
if (BITSET_TEST_COUNT(slots[slot].writes, I->dest[d].value,
nr_writes))
wait_mask |= BITSET_BIT(slot);
}
}
@ -125,9 +124,8 @@ agx_insert_waits_local(agx_context *ctx, agx_block *block)
continue;
assert(I->dest[d].type == AGX_INDEX_REGISTER);
BITSET_SET_RANGE(
slots[I->scoreboard].writes, I->dest[d].value,
I->dest[d].value + agx_index_size_16(I->dest[d]) - 1);
BITSET_SET_COUNT(slots[I->scoreboard].writes, I->dest[d].value,
agx_index_size_16(I->dest[d]));
}
slots[I->scoreboard].nr_pending++;

11
src/asahi/compiler/agx_opt_register_cache.c
View file

@ -13,12 +13,12 @@ postra_liveness_ins(BITSET_WORD *live, agx_instr *I)
{
agx_foreach_reg_dest(I, d) {
unsigned reg = I->dest[d].value;
BITSET_CLEAR_RANGE(live, reg, reg + agx_index_size_16(I->dest[d]) - 1);
BITSET_CLEAR_COUNT(live, reg, agx_index_size_16(I->dest[d]));
}
agx_foreach_reg_src(I, s) {
unsigned reg = I->src[s].value;
BITSET_SET_RANGE(live, reg, reg + agx_index_size_16(I->src[s]) - 1);
BITSET_SET_COUNT(live, reg, agx_index_size_16(I->src[s]));
}
}
@ -113,7 +113,7 @@ agx_opt_register_cache(agx_context *ctx)
unsigned nr = agx_index_size_16(I->dest[d]);
I->dest[d].cache = BITSET_TEST(alu_reads, I->dest[d].value);
BITSET_CLEAR_RANGE(alu_reads, reg, reg + nr - 1);
BITSET_CLEAR_COUNT(alu_reads, reg, nr);
}
agx_foreach_reg_src(I, s) {
@ -128,8 +128,7 @@ agx_opt_register_cache(agx_context *ctx)
* That includes if the register is overwritten this cycle, but that
* won't show up in the liveness analysis.
*/
bool lu = !BITSET_TEST_RANGE(live, reg, reg + nr - 1) ||
writes_reg(I, reg);
bool lu = !BITSET_TEST_COUNT(live, reg, nr) || writes_reg(I, reg);
/* Handling divergent blocks would require physical CFG awareness.
* Just bail for now, skipping this pass won't affect correctness.
@ -144,7 +143,7 @@ agx_opt_register_cache(agx_context *ctx)
* better given our limited understanding of the hardware.
*/
if (agx_is_alu(I))
BITSET_SET_RANGE(alu_reads, reg, reg + nr - 1);
BITSET_SET_COUNT(alu_reads, reg, nr);
assert(!(I->src[s].discard && I->src[s].cache));
}

57
src/asahi/compiler/agx_register_allocate.c
View file

@ -331,7 +331,7 @@ find_regs_simple(struct ra_ctx *rctx, enum ra_class cls, unsigned count,
unsigned align, unsigned *out)
{
for (unsigned reg = 0; reg + count <= rctx->bound[cls]; reg += align) {
if (!BITSET_TEST_RANGE(rctx->used_regs[cls], reg, reg + count - 1)) {
if (!BITSET_TEST_COUNT(rctx->used_regs[cls], reg, count)) {
*out = reg;
return true;
}
@ -388,7 +388,7 @@ find_best_region_to_evict(struct ra_ctx *rctx, unsigned size,
/* Do not evict the same register multiple times. It's not necessary since
* we're just shuffling, there are enough free registers elsewhere.
*/
if (BITSET_TEST_RANGE(already_evicted, base, base + size - 1))
if (BITSET_TEST_COUNT(already_evicted, base, size))
continue;
/* Estimate the number of moves required if we pick this region */
@ -521,7 +521,7 @@ assign_regs_by_copying(struct ra_ctx *rctx, agx_index dest, const agx_instr *I,
/* We are going to allocate to this range, so it is now fully used. Mark
* it as such so we don't reassign here later.
*/
BITSET_SET_RANGE(rctx->used_regs[RA_GPR], new_reg, new_reg + nr - 1);
BITSET_SET_COUNT(rctx->used_regs[RA_GPR], new_reg, nr);
/* The first iteration is special: it is the original allocation of a
* variable. All subsequent iterations pick a new register for a blocked
@ -534,7 +534,7 @@ assign_regs_by_copying(struct ra_ctx *rctx, agx_index dest, const agx_instr *I,
/* Mark down the set of clobbered registers, so that killed sources may be
* handled correctly later.
*/
BITSET_SET_RANGE(clobbered, new_reg, new_reg + nr - 1);
BITSET_SET_COUNT(clobbered, new_reg, nr);
/* Update bookkeeping for this variable */
set_ssa_to_reg(rctx, ssa, new_reg);
@ -634,7 +634,7 @@ find_regs(struct ra_ctx *rctx, agx_instr *I, unsigned dest_idx, unsigned count,
util_dynarray_fini(&copies);
/* assign_regs asserts this is cleared, so clear to be reassigned */
BITSET_CLEAR_RANGE(rctx->used_regs[cls], reg, reg + count - 1);
BITSET_CLEAR_COUNT(rctx->used_regs[cls], reg, count);
return reg;
}
}
@ -751,12 +751,12 @@ assign_regs(struct ra_ctx *rctx, agx_index v, unsigned reg)
assert(!BITSET_TEST(rctx->visited, v.value) && "SSA violated");
BITSET_SET(rctx->visited, v.value);
assert(rctx->ncomps[v.value] >= 1);
unsigned end = reg + rctx->ncomps[v.value] - 1;
assert(!BITSET_TEST_RANGE(rctx->used_regs[cls], reg, end) &&
unsigned nr = rctx->ncomps[v.value];
assert(nr >= 1);
assert(!BITSET_TEST_COUNT(rctx->used_regs[cls], reg, nr) &&
"no interference");
BITSET_SET_RANGE(rctx->used_regs[cls], reg, end);
BITSET_SET_COUNT(rctx->used_regs[cls], reg, nr);
/* Phi webs need to remember which register they're assigned to */
struct phi_web_node *node =
@ -815,7 +815,7 @@ try_coalesce_with(struct ra_ctx *rctx, agx_index ssa, unsigned count,
unsigned base = rctx->ssa_to_reg[ssa.value];
enum ra_class cls = ra_class_for_index(ssa);
if (BITSET_TEST_RANGE(rctx->used_regs[cls], base, base + count - 1))
if (BITSET_TEST_COUNT(rctx->used_regs[cls], base, count))
return false;
assert(base + count <= rctx->bound[cls] && "invariant");
@ -840,7 +840,7 @@ pick_regs(struct ra_ctx *rctx, agx_instr *I, unsigned d)
if (rctx->phi_web[phi_idx].assigned) {
unsigned reg = rctx->phi_web[phi_idx].reg;
if ((reg % align) == 0 && reg + align < rctx->bound[cls] &&
!BITSET_TEST_RANGE(rctx->used_regs[cls], reg, reg + align - 1))
!BITSET_TEST_COUNT(rctx->used_regs[cls], reg, align))
return reg;
}
@ -881,7 +881,7 @@ pick_regs(struct ra_ctx *rctx, agx_instr *I, unsigned d)
if (base % align)
continue;
if (!BITSET_TEST_RANGE(rctx->used_regs[cls], base, base + count - 1))
if (!BITSET_TEST_COUNT(rctx->used_regs[cls], base, count))
return base;
}
}
@ -891,7 +891,7 @@ pick_regs(struct ra_ctx *rctx, agx_instr *I, unsigned d)
if (collect_phi && collect_phi->op == AGX_OPCODE_EXPORT) {
unsigned reg = collect_phi->imm;
if (!BITSET_TEST_RANGE(rctx->used_regs[cls], reg, reg + align - 1) &&
if (!BITSET_TEST_COUNT(rctx->used_regs[cls], reg, align) &&
(reg % align) == 0)
return reg;
}
@ -903,8 +903,7 @@ pick_regs(struct ra_ctx *rctx, agx_instr *I, unsigned d)
if (exp && exp->op == AGX_OPCODE_EXPORT) {
unsigned reg = exp->imm;
if (!BITSET_TEST_RANGE(rctx->used_regs[cls], reg,
reg + align - 1) &&
if (!BITSET_TEST_COUNT(rctx->used_regs[cls], reg, align) &&
(reg % align) == 0)
return reg;
}
@ -947,8 +946,7 @@ pick_regs(struct ra_ctx *rctx, agx_instr *I, unsigned d)
continue;
/* If those registers are free, then choose them */
if (!BITSET_TEST_RANGE(rctx->used_regs[cls], our_reg,
our_reg + align - 1))
if (!BITSET_TEST_COUNT(rctx->used_regs[cls], our_reg, align))
return our_reg;
}
@ -961,8 +959,8 @@ pick_regs(struct ra_ctx *rctx, agx_instr *I, unsigned d)
for (unsigned base = 0;
base + (collect->nr_srcs * align) <= rctx->bound[cls];
base += collect_align) {
if (!BITSET_TEST_RANGE(rctx->used_regs[cls], base,
base + (collect->nr_srcs * align) - 1))
if (!BITSET_TEST_COUNT(rctx->used_regs[cls], base,
collect->nr_srcs * align))
return base + offset;
}
@ -973,7 +971,7 @@ pick_regs(struct ra_ctx *rctx, agx_instr *I, unsigned d)
if (collect_align > align) {
for (unsigned reg = offset; reg + collect_align <= rctx->bound[cls];
reg += collect_align) {
if (!BITSET_TEST_RANGE(rctx->used_regs[cls], reg, reg + count - 1))
if (!BITSET_TEST_COUNT(rctx->used_regs[cls], reg, count))
return reg;
}
}
@ -994,7 +992,7 @@ pick_regs(struct ra_ctx *rctx, agx_instr *I, unsigned d)
unsigned base = phi->dest[0].reg;
if (base + count <= rctx->bound[cls] &&
!BITSET_TEST_RANGE(rctx->used_regs[cls], base, base + count - 1))
!BITSET_TEST_COUNT(rctx->used_regs[cls], base, count))
return base;
}
}
@ -1013,7 +1011,7 @@ kill_source(struct ra_ctx *rctx, const agx_instr *I, unsigned s)
assert(I->op != AGX_OPCODE_PHI && "phis don't use .kill");
assert(count >= 1);
BITSET_CLEAR_RANGE(rctx->used_regs[cls], reg, reg + count - 1);
BITSET_CLEAR_COUNT(rctx->used_regs[cls], reg, count);
}
static void
@ -1074,7 +1072,7 @@ agx_ra_assign_local(struct ra_ctx *rctx)
/* Reserve bottom registers as temporaries for parallel copy lowering */
if (rctx->shader->has_spill_pcopy_reserved) {
BITSET_SET_RANGE(used_regs_gpr, 0, 7);
BITSET_SET_COUNT(used_regs_gpr, 0, 8);
}
agx_foreach_instr_in_block(block, I) {
@ -1093,20 +1091,15 @@ agx_ra_assign_local(struct ra_ctx *rctx)
/* Free up the source */
unsigned offset_reg = reg + (d * width);
BITSET_CLEAR_RANGE(used_regs_gpr, offset_reg,
offset_reg + width - 1);
BITSET_CLEAR_COUNT(used_regs_gpr, offset_reg, width);
/* Assign the destination where the source was */
if (!agx_is_null(I->dest[d]))
assign_regs(rctx, I->dest[d], offset_reg);
}
unsigned excess =
rctx->ncomps[I->src[0].value] - (I->nr_dests * width);
if (excess) {
BITSET_CLEAR_RANGE(used_regs_gpr, reg + (I->nr_dests * width),
reg + rctx->ncomps[I->src[0].value] - 1);
}
unsigned trail = rctx->ncomps[I->src[0].value] - (I->nr_dests * width);
BITSET_CLEAR_COUNT(used_regs_gpr, reg + (I->nr_dests * width), trail);
agx_set_sources(rctx, I);
agx_set_dests(rctx, I);

2
src/compiler/glsl/gl_nir_link_uniforms.c
View file

@ -142,7 +142,7 @@ mark_array_elements_referenced(const struct array_deref_range *dr,
BITSET_SET(bits, dr[0].index);
} else {
/* Accessed by non-constant index so set everything as referenced */
BITSET_SET_RANGE(bits, 0, dr[0].size - 1);
BITSET_SET_COUNT(bits, 0, dr[0].size);
}
return;

19
src/compiler/glsl/gl_nir_lower_samplers_as_deref.c
View file

@ -127,18 +127,15 @@ record_images_used(struct shader_info *info,
const unsigned size =
glsl_type_is_array(var->type) ? glsl_get_aoa_size(var->type) : 1;
BITSET_SET_RANGE(info->images_used, var->data.binding,
var->data.binding + (MAX2(size, 1) - 1));
BITSET_SET_COUNT(info->images_used, var->data.binding, MAX2(size, 1));
enum glsl_sampler_dim sampler_dim =
glsl_get_sampler_dim(glsl_without_array(var->type));
if (sampler_dim == GLSL_SAMPLER_DIM_BUF) {
BITSET_SET_RANGE(info->image_buffers, var->data.binding,
var->data.binding + (MAX2(size, 1) - 1));
BITSET_SET_COUNT(info->image_buffers, var->data.binding, MAX2(size, 1));
}
if (sampler_dim == GLSL_SAMPLER_DIM_MS) {
BITSET_SET_RANGE(info->msaa_images, var->data.binding,
var->data.binding + (MAX2(size, 1) - 1));
BITSET_SET_COUNT(info->msaa_images, var->data.binding, MAX2(size, 1));
}
}
@ -242,14 +239,13 @@ record_textures_used(struct shader_info *info,
const unsigned size =
glsl_type_is_array(var->type) ? glsl_get_aoa_size(var->type) : 1;
BITSET_SET_RANGE(info->textures_used, var->data.binding,
var->data.binding + (MAX2(size, 1) - 1));
BITSET_SET_COUNT(info->textures_used, var->data.binding, MAX2(size, 1));
if (op == nir_texop_txf ||
op == nir_texop_txf_ms ||
op == nir_texop_txf_ms_mcs_intel) {
BITSET_SET_RANGE(info->textures_used_by_txf, var->data.binding,
var->data.binding + (MAX2(size, 1) - 1));
BITSET_SET_COUNT(info->textures_used_by_txf, var->data.binding,
MAX2(size, 1));
}
}
@ -264,8 +260,7 @@ record_samplers_used(struct shader_info *info,
const unsigned size =
glsl_type_is_array(var->type) ? glsl_get_aoa_size(var->type) : 1;
BITSET_SET_RANGE(info->samplers_used, var->data.binding,
var->data.binding + (MAX2(size, 1) - 1));
BITSET_SET_COUNT(info->samplers_used, var->data.binding, MAX2(size, 1));
}
static bool

9
src/compiler/nir/nir_lower_cl_images.c
View file

@ -144,12 +144,10 @@ nir_lower_cl_images(nir_shader *shader, bool lower_image_derefs, bool lower_samp
}
shader->info.num_textures = num_rd_images;
BITSET_ZERO(shader->info.textures_used);
if (num_rd_images)
BITSET_SET_RANGE(shader->info.textures_used, 0, num_rd_images - 1);
BITSET_SET_COUNT(shader->info.textures_used, 0, num_rd_images);
BITSET_ZERO(shader->info.images_used);
if (num_wr_images)
BITSET_SET_RANGE(shader->info.images_used, 0, num_wr_images - 1);
BITSET_SET_COUNT(shader->info.images_used, 0, num_wr_images);
shader->info.num_images = num_wr_images;
last_loc = -1;
@ -167,8 +165,7 @@ nir_lower_cl_images(nir_shader *shader, bool lower_image_derefs, bool lower_samp
}
}
BITSET_ZERO(shader->info.samplers_used);
if (num_samplers)
BITSET_SET_RANGE(shader->info.samplers_used, 0, num_samplers - 1);
BITSET_SET_COUNT(shader->info.samplers_used, 0, num_samplers);
nir_builder b = nir_builder_create(impl);

2
src/compiler/nir/nir_lower_mem_access_bit_sizes.c
View file

@ -475,7 +475,7 @@ lower_mem_store(nir_builder *b, nir_intrinsic_instr *intrin,
align_mul, chunk_align_offset, packed,
requested.num_components, requested.bit_size);
}
BITSET_CLEAR_RANGE(mask, chunk_start, (chunk_start + chunk_bytes - 1));
BITSET_CLEAR_COUNT(mask, chunk_start, chunk_bytes);
}
nir_instr_remove(&intrin->instr);

6
src/freedreno/ir3/ir3.h
View file

@ -3202,21 +3202,21 @@ static inline bool
__regmask_get(regmask_t *regmask, enum ir3_reg_file file, unsigned n, unsigned size)
{
BITSET_WORD *regs = __regmask_file(regmask, file);
return BITSET_TEST_RANGE(regs, n, n + size - 1);
return BITSET_TEST_COUNT(regs, n, size);
}
static inline void
__regmask_set(regmask_t *regmask, enum ir3_reg_file file, unsigned n, unsigned size)
{
BITSET_WORD *regs = __regmask_file(regmask, file);
BITSET_SET_RANGE(regs, n, n + size - 1);
BITSET_SET_COUNT(regs, n, size);
}
static inline void
__regmask_clear(regmask_t *regmask, enum ir3_reg_file file, unsigned n, unsigned size)
{
BITSET_WORD *regs = __regmask_file(regmask, file);
BITSET_CLEAR_RANGE(regs, n, n + size - 1);
BITSET_CLEAR_COUNT(regs, n, size);
}
static inline void

12
src/freedreno/ir3/ir3_alias.c
View file

@ -279,7 +279,7 @@ find_free_alias_regs_in_range(const reg_bitset *alloc_regs,
assert(end >= num_aliases);
for (unsigned reg = start; reg < end - num_aliases; reg++) {
if (!BITSET_TEST_RANGE(*alloc_regs, reg, reg + num_aliases - 1)) {
if (!BITSET_TEST_COUNT(*alloc_regs, reg, num_aliases)) {
return reg;
}
}
@ -384,8 +384,7 @@ alloc_alias(struct alias_table_state *state, struct ir3_instruction *instr,
*/
unsigned first_reg = alias->num - alias_n;
if (BITSET_TEST_RANGE(*alloc_regs, first_reg,
first_reg + num_aliases - 1)) {
if (BITSET_TEST_COUNT(*alloc_regs, first_reg, num_aliases)) {
continue;
}
@ -426,10 +425,9 @@ alloc_alias(struct alias_table_state *state, struct ir3_instruction *instr,
}
/* Mark used registers as allocated. */
unsigned end_reg = best_reg + num_aliases - 1;
assert(end_reg < GPR_REG_SIZE);
assert(!BITSET_TEST_RANGE(*alloc_regs, best_reg, end_reg));
BITSET_SET_RANGE(*alloc_regs, best_reg, end_reg);
assert(best_reg + num_aliases <= GPR_REG_SIZE);
assert(!BITSET_TEST_COUNT(*alloc_regs, best_reg, num_aliases));
BITSET_SET_COUNT(*alloc_regs, best_reg, num_aliases);
/* Add the allocated registers that differ from the ones already used to the
* alias table.

2
src/gallium/drivers/asahi/agx_nir_lower_sysvals.c
View file

@ -293,7 +293,7 @@ record_loads(nir_builder *b, nir_intrinsic_instr *intr, void *data)
unsigned offset = nir_intrinsic_binding(intr);
assert((offset % 2) == 0 && "all entries are aligned by ABI");
BITSET_SET_RANGE(table->pushed, (offset / 2), (offset / 2) + length - 1);
BITSET_SET_COUNT(table->pushed, (offset / 2), length);
for (unsigned i = 0; i < length; ++i) {
if (table->element_size[(offset / 2) + i])

4
src/gallium/drivers/iris/iris_state.c
View file

@ -3531,8 +3531,8 @@ iris_set_sampler_views(struct pipe_context *ctx,
if (count == 0 && unbind_num_trailing_slots == 0)
return;
BITSET_CLEAR_RANGE(shs->bound_sampler_views, start,
start + count + unbind_num_trailing_slots - 1);
BITSET_CLEAR_COUNT(shs->bound_sampler_views, start,
count + unbind_num_trailing_slots);
for (i = 0; i < count; i++) {
struct pipe_sampler_view *pview = views ? views[i] : NULL;

3
src/gallium/drivers/radeonsi/si_gfx_cs.c
View file

@ -372,7 +372,8 @@ void si_set_tracked_regs_to_clear_state(struct si_context *ctx)
ctx->tracked_regs.reg_value[SI_TRACKED_CB_DCC_CONTROL] = 0;
/* Set all cleared context registers to saved. */
BITSET_SET_RANGE(ctx->tracked_regs.reg_saved_mask, 0, SI_NUM_TRACKED_CONTEXT_REGS - 1);
BITSET_SET_COUNT(ctx->tracked_regs.reg_saved_mask, 0,
SI_NUM_TRACKED_CONTEXT_REGS);
}
void si_install_draw_wrapper(struct si_context *sctx, pipe_draw_func wrapper,

7
src/gallium/drivers/zink/zink_compiler.c
View file

@ -4294,7 +4294,8 @@ analyze_io(struct zink_shader *zs, nir_shader *shader)
if (deref_idx >= 0) {
nir_variable *img = nir_deref_instr_get_variable(nir_def_as_deref(tex->src[deref_idx].src.ssa));
unsigned size = glsl_type_is_array(img->type) ? glsl_get_aoa_size(img->type) : 1;
BITSET_SET_RANGE(shader->info.textures_used, img->data.driver_location, img->data.driver_location + (size - 1));
BITSET_SET_COUNT(shader->info.textures_used,
img->data.driver_location, size);
}
continue;
}
@ -4680,8 +4681,8 @@ scan_nir(struct zink_screen *screen, nir_shader *shader, struct zink_shader *zs)
/* Structs have been lowered already, so get_aoa_size is sufficient. */
const unsigned size =
glsl_type_is_array(var->type) ? glsl_get_aoa_size(var->type) : 1;
BITSET_SET_RANGE(shader->info.images_used, var->data.binding,
var->data.binding + (MAX2(size, 1) - 1));
BITSET_SET_COUNT(shader->info.images_used, var->data.binding,
MAX2(size, 1));
}
if (intr->intrinsic == nir_intrinsic_is_sparse_texels_resident ||
intr->intrinsic == nir_intrinsic_image_deref_sparse_load)

8
src/imagination/vulkan/pvr_hw_pass.c
View file

@ -390,7 +390,7 @@ pvr_is_space_in_buffer(const struct pvr_device_info *dev_info,
assert(pixel_size <= max_out_regs);
for (uint32_t i = 0U; i <= (max_out_regs - pixel_size); i += alignment) {
if (!BITSET_TEST_RANGE(buffer->allocs, i, i + pixel_size - 1U))
if (!BITSET_TEST_COUNT(buffer->allocs, i, pixel_size))
return i;
}
@ -590,8 +590,8 @@ pvr_mark_storage_allocated_in_buffer(struct pvr_renderpass_alloc_buffer *buffer,
uint32_t start,
uint32_t pixel_size)
{
assert(!BITSET_TEST_RANGE(buffer->allocs, start, start + pixel_size - 1U));
BITSET_SET_RANGE(buffer->allocs, start, start + pixel_size - 1U);
assert(!BITSET_TEST_COUNT(buffer->allocs, start, pixel_size));
BITSET_SET_COUNT(buffer->allocs, start, pixel_size);
}
static VkResult
@ -706,7 +706,7 @@ pvr_free_buffer_storage(struct pvr_renderpass_alloc_buffer *buffer,
pvr_get_accum_format_bitsize(int_attach->attachment->vk_format),
32U);
BITSET_CLEAR_RANGE(buffer->allocs, start, start + pixel_size - 1U);
BITSET_CLEAR_COUNT(buffer->allocs, start, pixel_size);
}
/** Free the storage allocated to an attachment. */

4
src/imagination/vulkan/pvr_mrt.c
View file

@ -70,8 +70,8 @@ static int32_t pvr_mrt_alloc_from_buffer(const struct pvr_device_info *dev_info,
assert(pixel_size <= max_out_regs);
for (uint32_t i = 0U; i <= (max_out_regs - pixel_size); i += alignment) {
if (!BITSET_TEST_RANGE(buffer->allocs, i, i + pixel_size - 1U)) {
BITSET_SET_RANGE(buffer->allocs, i, i + pixel_size - 1U);
if (!BITSET_TEST_COUNT(buffer->allocs, i, pixel_size)) {
BITSET_SET_COUNT(buffer->allocs, i, pixel_size);
return i;
}
}

2
src/intel/vulkan/anv_allocator.c
View file

@ -1161,7 +1161,7 @@ anv_state_reserved_array_pool_init(struct anv_state_reserved_array_pool *pool,
if (pool->states == NULL)
return vk_error(&device->vk, VK_ERROR_OUT_OF_HOST_MEMORY);
BITSET_SET_RANGE(pool->states, 0, pool->count - 1);
BITSET_SET_COUNT(pool->states, 0, pool->count);
simple_mtx_init(&pool->mutex, mtx_plain);
pool->state = anv_state_pool_alloc(pool->pool, pool->stride * count, alignment);

4
src/kosmickrisp/vulkan/kk_descriptor_set_layout.c
View file

@ -206,8 +206,8 @@ kk_CreateDescriptorSetLayout(VkDevice device,
switch (binding->descriptorType) {
case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC:
layout->binding[b].dynamic_buffer_index = dynamic_buffer_count;
BITSET_SET_RANGE(layout->dynamic_ubos, dynamic_buffer_count,
dynamic_buffer_count + binding->descriptorCount - 1);
BITSET_SET_COUNT(layout->dynamic_ubos, dynamic_buffer_count,
binding->descriptorCount);
dynamic_buffer_count += binding->descriptorCount;
break;

2
src/mesa/state_tracker/st_atom.h
View file

@ -126,7 +126,7 @@ typedef BITSET_DECLARE(st_state_bitset, ST_NUM_ATOMS);
} while (0)
#define ST_SET_ALL_STATES(bitset) \
BITSET_SET_RANGE(bitset, 0, ST_NUM_ATOMS - 1)
BITSET_SET_COUNT(bitset, 0, ST_NUM_ATOMS)
#define ST_SHADER_STATE_MASK(bitset, shader) \
ST_SET_STATE4(bitset, ST_NEW_##shader##_STATE, ST_NEW_##shader##_SAMPLER_VIEWS, \

10
src/microsoft/vulkan/dzn_cmd_buffer.c
View file

@ -798,7 +798,7 @@ dzn_cmd_buffer_dynbitset_set_range(struct dzn_cmd_buffer *cmdbuf,
if (result != VK_SUCCESS)
return result;
BITSET_SET_RANGE(util_dynarray_element(array, BITSET_WORD, 0), bit, bit + count - 1);
BITSET_SET_COUNT(util_dynarray_element(array, BITSET_WORD, 0), bit, count);
return VK_SUCCESS;
}
@ -816,7 +816,8 @@ dzn_cmd_buffer_dynbitset_clear_range(struct dzn_cmd_buffer *cmdbuf,
while (bit <= end) {
uint32_t subcount = MIN2(end + 1 - bit, 32 - (bit % 32));
BITSET_CLEAR_RANGE(util_dynarray_element(array, BITSET_WORD, 0), bit, bit + subcount - 1);
BITSET_CLEAR_COUNT(util_dynarray_element(array, BITSET_WORD, 0), bit,
subcount);
bit += subcount;
}
}
@ -5142,7 +5143,7 @@ dzn_CmdBindPipeline(VkCommandBuffer commandBuffer,
cmdbuf->state.vb.views[vb].StrideInBytes = gfx->vb.strides[vb];
if (gfx->vb.count > 0)
BITSET_SET_RANGE(cmdbuf->state.vb.dirty, 0, gfx->vb.count - 1);
BITSET_SET_COUNT(cmdbuf->state.vb.dirty, 0, gfx->vb.count);
}
}
@ -5482,8 +5483,7 @@ dzn_CmdBindVertexBuffers(VkCommandBuffer commandBuffer,
vbviews[firstBinding + i].SizeInBytes = buf->size - pOffsets[i];
}
BITSET_SET_RANGE(cmdbuf->state.vb.dirty, firstBinding,
firstBinding + bindingCount - 1);
BITSET_SET_COUNT(cmdbuf->state.vb.dirty, firstBinding, bindingCount);
}
VKAPI_ATTR void VKAPI_CALL

4
src/nouveau/vulkan/nvk_descriptor_set_layout.c
View file

@ -252,8 +252,8 @@ nvk_CreateDescriptorSetLayout(VkDevice device,
switch (binding->descriptorType) {
case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC:
layout->binding[b].dynamic_buffer_index = dynamic_buffer_count;
BITSET_SET_RANGE(layout->dynamic_ubos, dynamic_buffer_count,
dynamic_buffer_count + binding->descriptorCount - 1);
BITSET_SET_COUNT(layout->dynamic_ubos, dynamic_buffer_count,
binding->descriptorCount);
dynamic_buffer_count += binding->descriptorCount;
break;

2
src/panfrost/vulkan/panvk_vX_cmd_draw.c
View file

@ -972,7 +972,7 @@ panvk_per_arch(cmd_prepare_draw_sysvals)(struct panvk_cmd_buffer *cmdbuf,
* they are not read at all, so clear the dirty bits to avoid re-emitting
* FAUs when we can. */
if (!cmdbuf->state.gfx.cb.info.shader_loads_blend_const)
BITSET_CLEAR_RANGE(dirty_shader_sysvals, 0, 3);
BITSET_CLEAR_COUNT(dirty_shader_sysvals, 0, 4);
if (!BITSET_IS_EMPTY(dirty_shader_sysvals))
gfx_state_set_dirty(cmdbuf, FS_PUSH_UNIFORMS);

4
src/panfrost/vulkan/panvk_vX_descriptor_set.c
View file

@ -382,7 +382,7 @@ panvk_per_arch(CreateDescriptorPool)(
}
/* initialize to all ones to indicate all sets are free */
BITSET_SET_RANGE(free_sets, 0, pCreateInfo->maxSets - 1);
BITSET_SET_COUNT(free_sets, 0, pCreateInfo->maxSets);
pool->free_sets = free_sets;
pool->sets = sets;
pool->max_sets = pCreateInfo->maxSets;
@ -642,7 +642,7 @@ panvk_per_arch(ResetDescriptorPool)(VkDevice _device, VkDescriptorPool _pool,
for (uint32_t i = 0; i < pool->max_sets; i++)
panvk_desc_pool_free_set(pool, &pool->sets[i]);
BITSET_SET_RANGE(pool->free_sets, 0, pool->max_sets - 1);
BITSET_SET_COUNT(pool->free_sets, 0, pool->max_sets);
return VK_SUCCESS;
}

2
src/vulkan/runtime/vk_graphics_state.h
View file

@ -1210,7 +1210,7 @@ vk_dynamic_graphics_state_fill(struct vk_dynamic_graphics_state *dyn,
static inline void
vk_dynamic_graphics_state_dirty_all(struct vk_dynamic_graphics_state *d)
{
BITSET_SET_RANGE(d->dirty, 0, MESA_VK_DYNAMIC_GRAPHICS_STATE_ENUM_MAX - 1);
BITSET_SET_COUNT(d->dirty, 0, MESA_VK_DYNAMIC_GRAPHICS_STATE_ENUM_MAX);
}
/** Mark all states in the given vk_dynamic_graphics_state not dirty