Georg Lehmann 5827de9cd6 aco/gfx12: use 64bit add/sub to swap sgprs ... Not writing SCC requires less instructions and gives the scheduler more freedom. Foz-DB GFX1201: Totals from 114 (0.14% of 82179) affected shaders: Instrs: 276265 -> 275791 (-0.17%) CodeSize: 1460504 -> 1458504 (-0.14%) Latency: 902933 -> 902548 (-0.04%); split: -0.04%, +0.00% InvThroughput: 166517 -> 166512 (-0.00%) SClause: 6703 -> 6698 (-0.07%) Reviewed-by: Rhys Perry <pendingchaos02@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39329>		2026-01-23 10:13:19 +00:00
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addrlib	amd: rename most GFX115x definitions for released chips	2025-12-03 13:29:07 +00:00
ci	ac/nir: fix computing cube derivatives when the major axis is negative	2026-01-21 07:12:34 +00:00
common	ac,radeonsi: set optimal COMPUTE_DISPATCH_INTERLEAVE for buffer clears/copies	2026-01-22 22:28:39 +00:00
compiler	aco/gfx12: use 64bit add/sub to swap sgprs	2026-01-23 10:13:19 +00:00
drm-shim	amd/drm-shim: add vega20	2026-01-08 09:30:54 +00:00
gmlib	meson: Relax -Wmaybe-uninitialized errors	2025-09-16 06:16:20 +00:00
lanczoslib	meson: Relax -Wmaybe-uninitialized errors	2025-09-16 06:16:20 +00:00
llvm	amd: add and use ac_cu_info::has_vtx_format_alpha_adjust_bug	2025-12-22 07:34:48 +00:00
registers	amd: Rename GFX1103_R1/R2 to PHOENIX/2	2024-11-20 02:14:40 +00:00
vpelib	amd/vpelib: add FL capabilitie and lut container size	2025-09-22 10:37:22 +00:00
vulkan	radv/gfx11: add a RADV_PERFTEST flag to expose bfloat16 cmat	2026-01-23 09:41:20 +00:00
meson.build	radv/tests: require drm-shim and use it instead of RADV_FORCE_FAMILY	2025-11-19 07:11:05 +00:00