Francisco Jerez 054eb9f346 intel/dev: Implement DG2 restrictions requiring additional DSSes to be disabled. ... Note that this causes a geometry slice to be disabled if any DSS is fused off within that slice, which may seem stricter than the BSpec quotation implies, but testing shows that pixel pipes with any faulted DSS don't work at all, and that using a slice with any faulted pixel pipe leads to serious graphics corruption. It would be better to query this geometry topology information from the hardware instead of trying to reconstruct it here, but the kernel interface for that is not available yet. Reviewed-by: Caio Oliveira <caio.oliveira@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14436>		2022-01-07 07:58:27 +00:00
..
intel_debug.c	intel/fs,vec4: Drop support for shader time	2021-12-10 21:20:47 +00:00
intel_debug.h	intel/fs,vec4: Drop support for shader time	2021-12-10 21:20:47 +00:00
intel_dev_info.c	intel/dev: fix subslice/eu total computations with some fused configurations	2021-11-05 10:22:18 +00:00
intel_device_info.c	intel/dev: Implement DG2 restrictions requiring additional DSSes to be disabled.	2022-01-07 07:58:27 +00:00
intel_device_info.h	intel/dev: Add support for pixel pipe subslice accounting on multi-slice GPUs.	2022-01-07 07:58:27 +00:00
intel_device_info_test.c	classic/i965: Remove driver	2021-12-03 23:53:06 +00:00
meson.build	intel: Rename gen_device prefix to intel_device	2021-04-20 20:06:33 +00:00