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intel: Rename gen_device prefix to intel_device

Browse source 
export SEARCH_PATH="src/intel src/gallium/drivers/iris src/mesa/drivers/dri/i965"
grep -E "gen_device" -rIl $SEARCH_PATH | xargs sed -ie "s/gen_device/intel_device/g"

Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10241>
This commit is contained in:
Anuj Phogat 2021-04-05 13:19:39 -07:00 • committed by Marge Bot
parent cd39d3b1ad
commit 61e8636557
205 changed files with 1119 additions and 1119 deletions
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2
src/gallium/drivers/iris/iris_batch.c
View file

@ -541,7 +541,7 @@ finish_seqno(struct iris_batch *batch)
static void
iris_finish_batch(struct iris_batch *batch)
{
const struct gen_device_info *devinfo = &batch->screen->devinfo;
const struct intel_device_info *devinfo = &batch->screen->devinfo;
if (devinfo->ver == 12 && batch->name == IRIS_BATCH_RENDER) {
/* We re-emit constants at the beginning of every batch as a hardware

6
src/gallium/drivers/iris/iris_blit.c
View file

@ -284,7 +284,7 @@ tex_cache_flush_hack(struct iris_batch *batch,
enum isl_format view_format,
enum isl_format surf_format)
{
const struct gen_device_info *devinfo = &batch->screen->devinfo;
const struct intel_device_info *devinfo = &batch->screen->devinfo;
/* The WaSamplerCacheFlushBetweenRedescribedSurfaceReads workaround says:
*
@ -351,7 +351,7 @@ iris_blit(struct pipe_context *ctx, const struct pipe_blit_info *info)
{
struct iris_context *ice = (void *) ctx;
struct iris_screen *screen = (struct iris_screen *)ctx->screen;
const struct gen_device_info *devinfo = &screen->devinfo;
const struct intel_device_info *devinfo = &screen->devinfo;
struct iris_batch *batch = &ice->batches[IRIS_BATCH_RENDER];
enum blorp_batch_flags blorp_flags = 0;
@ -552,7 +552,7 @@ get_copy_region_aux_settings(struct iris_context *ice,
bool is_render_target)
{
struct iris_screen *screen = (void *) ice->ctx.screen;
struct gen_device_info *devinfo = &screen->devinfo;
struct intel_device_info *devinfo = &screen->devinfo;
switch (res->aux.usage) {
case ISL_AUX_USAGE_HIZ:

4
src/gallium/drivers/iris/iris_bufmgr.c
View file

@ -1882,7 +1882,7 @@ gem_param(int fd, int name)
* \param fd File descriptor of the opened DRM device.
*/
static struct iris_bufmgr *
iris_bufmgr_create(struct gen_device_info *devinfo, int fd, bool bo_reuse)
iris_bufmgr_create(struct intel_device_info *devinfo, int fd, bool bo_reuse)
{
uint64_t gtt_size = iris_gtt_size(fd);
if (gtt_size <= IRIS_MEMZONE_OTHER_START)
@ -1988,7 +1988,7 @@ iris_bufmgr_unref(struct iris_bufmgr *bufmgr)
* \param fd File descriptor of the opened DRM device.
*/
struct iris_bufmgr *
iris_bufmgr_get_for_fd(struct gen_device_info *devinfo, int fd, bool bo_reuse)
iris_bufmgr_get_for_fd(struct intel_device_info *devinfo, int fd, bool bo_reuse)
{
struct stat st;

4
src/gallium/drivers/iris/iris_bufmgr.h
View file

@ -35,7 +35,7 @@
#include "pipe/p_defines.h"
struct iris_batch;
struct gen_device_info;
struct intel_device_info;
struct pipe_debug_callback;
/**
@ -370,7 +370,7 @@ int iris_bo_busy(struct iris_bo *bo);
int iris_bo_madvise(struct iris_bo *bo, int madv);
/* drm_bacon_bufmgr_gem.c */
struct iris_bufmgr *iris_bufmgr_get_for_fd(struct gen_device_info *devinfo, int fd,
struct iris_bufmgr *iris_bufmgr_get_for_fd(struct intel_device_info *devinfo, int fd,
bool bo_reuse);
int iris_bufmgr_get_fd(struct iris_bufmgr *bufmgr);

8
src/gallium/drivers/iris/iris_clear.c
View file

@ -41,7 +41,7 @@ iris_is_color_fast_clear_compatible(struct iris_context *ice,
const union isl_color_value color)
{
struct iris_batch *batch = &ice->batches[IRIS_BATCH_RENDER];
const struct gen_device_info *devinfo = &batch->screen->devinfo;
const struct intel_device_info *devinfo = &batch->screen->devinfo;
if (isl_format_has_int_channel(format)) {
perf_debug(&ice->dbg, "Integer fast clear not enabled for %s\n",
@ -343,7 +343,7 @@ clear_color(struct iris_context *ice,
struct iris_resource *res = (void *) p_res;
struct iris_batch *batch = &ice->batches[IRIS_BATCH_RENDER];
const struct gen_device_info *devinfo = &batch->screen->devinfo;
const struct intel_device_info *devinfo = &batch->screen->devinfo;
enum blorp_batch_flags blorp_flags = 0;
if (render_condition_enabled) {
@ -415,7 +415,7 @@ can_fast_clear_depth(struct iris_context *ice,
struct pipe_resource *p_res = (void *) res;
struct pipe_context *ctx = (void *) ice;
struct iris_screen *screen = (void *) ctx->screen;
const struct gen_device_info *devinfo = &screen->devinfo;
const struct intel_device_info *devinfo = &screen->devinfo;
if (INTEL_DEBUG & DEBUG_NO_FAST_CLEAR)
return false;
@ -697,7 +697,7 @@ iris_clear_texture(struct pipe_context *ctx,
struct iris_context *ice = (void *) ctx;
struct iris_screen *screen = (void *) ctx->screen;
struct iris_resource *res = (void *) p_res;
const struct gen_device_info *devinfo = &screen->devinfo;
const struct intel_device_info *devinfo = &screen->devinfo;
if (iris_resource_unfinished_aux_import(res))
iris_resource_finish_aux_import(ctx->screen, res);

2
src/gallium/drivers/iris/iris_context.c
View file

@ -270,7 +270,7 @@ struct pipe_context *
iris_create_context(struct pipe_screen *pscreen, void *priv, unsigned flags)
{
struct iris_screen *screen = (struct iris_screen*)pscreen;
const struct gen_device_info *devinfo = &screen->devinfo;
const struct intel_device_info *devinfo = &screen->devinfo;
struct iris_context *ice = rzalloc(NULL, struct iris_context);
if (!ice)

2
src/gallium/drivers/iris/iris_draw.c
View file

@ -254,7 +254,7 @@ iris_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *info,
struct iris_context *ice = (struct iris_context *) ctx;
struct iris_screen *screen = (struct iris_screen*)ice->ctx.screen;
const struct gen_device_info *devinfo = &screen->devinfo;
const struct intel_device_info *devinfo = &screen->devinfo;
struct iris_batch *batch = &ice->batches[IRIS_BATCH_RENDER];
if (ice->state.predicate == IRIS_PREDICATE_STATE_DONT_RENDER)

4
src/gallium/drivers/iris/iris_formats.c
View file

@ -35,7 +35,7 @@
#include "iris_screen.h"
struct iris_format_info
iris_format_for_usage(const struct gen_device_info *devinfo,
iris_format_for_usage(const struct intel_device_info *devinfo,
enum pipe_format pformat,
isl_surf_usage_flags_t usage)
{
@ -111,7 +111,7 @@ iris_is_format_supported(struct pipe_screen *pscreen,
unsigned usage)
{
struct iris_screen *screen = (struct iris_screen *) pscreen;
const struct gen_device_info *devinfo = &screen->devinfo;
const struct intel_device_info *devinfo = &screen->devinfo;
uint32_t max_samples = devinfo->ver == 8 ? 8 : 16;
if (sample_count > max_samples ||

40
src/gallium/drivers/iris/iris_program.c
View file

@ -61,7 +61,7 @@ get_new_program_id(struct iris_screen *screen)
}
static struct brw_vs_prog_key
iris_to_brw_vs_key(const struct gen_device_info *devinfo,
iris_to_brw_vs_key(const struct intel_device_info *devinfo,
const struct iris_vs_prog_key *key)
{
return (struct brw_vs_prog_key) {
@ -75,7 +75,7 @@ iris_to_brw_vs_key(const struct gen_device_info *devinfo,
}
static struct brw_tcs_prog_key
iris_to_brw_tcs_key(const struct gen_device_info *devinfo,
iris_to_brw_tcs_key(const struct intel_device_info *devinfo,
const struct iris_tcs_prog_key *key)
{
return (struct brw_tcs_prog_key) {
@ -89,7 +89,7 @@ iris_to_brw_tcs_key(const struct gen_device_info *devinfo,
}
static struct brw_tes_prog_key
iris_to_brw_tes_key(const struct gen_device_info *devinfo,
iris_to_brw_tes_key(const struct intel_device_info *devinfo,
const struct iris_tes_prog_key *key)
{
return (struct brw_tes_prog_key) {
@ -100,7 +100,7 @@ iris_to_brw_tes_key(const struct gen_device_info *devinfo,
}
static struct brw_gs_prog_key
iris_to_brw_gs_key(const struct gen_device_info *devinfo,
iris_to_brw_gs_key(const struct intel_device_info *devinfo,
const struct iris_gs_prog_key *key)
{
return (struct brw_gs_prog_key) {
@ -109,7 +109,7 @@ iris_to_brw_gs_key(const struct gen_device_info *devinfo,
}
static struct brw_wm_prog_key
iris_to_brw_fs_key(const struct gen_device_info *devinfo,
iris_to_brw_fs_key(const struct intel_device_info *devinfo,
const struct iris_fs_prog_key *key)
{
return (struct brw_wm_prog_key) {
@ -130,7 +130,7 @@ iris_to_brw_fs_key(const struct gen_device_info *devinfo,
}
static struct brw_cs_prog_key
iris_to_brw_cs_key(const struct gen_device_info *devinfo,
iris_to_brw_cs_key(const struct intel_device_info *devinfo,
const struct iris_cs_prog_key *key)
{
return (struct brw_cs_prog_key) {
@ -385,7 +385,7 @@ iris_setup_uniforms(const struct brw_compiler *compiler,
unsigned *out_num_system_values,
unsigned *out_num_cbufs)
{
UNUSED const struct gen_device_info *devinfo = compiler->devinfo;
UNUSED const struct intel_device_info *devinfo = compiler->devinfo;
unsigned system_values_start = ALIGN(kernel_input_size, sizeof(uint32_t));
@ -790,7 +790,7 @@ skip_compacting_binding_tables(void)
* Set up the binding table indices and apply to the shader.
*/
static void
iris_setup_binding_table(const struct gen_device_info *devinfo,
iris_setup_binding_table(const struct intel_device_info *devinfo,
struct nir_shader *nir,
struct iris_binding_table *bt,
unsigned num_render_targets,
@ -1030,7 +1030,7 @@ iris_debug_recompile(struct iris_screen *screen,
|| list_is_singular(&ish->variants))
return;
const struct gen_device_info *devinfo = &screen->devinfo;
const struct intel_device_info *devinfo = &screen->devinfo;
const struct brw_compiler *c = screen->compiler;
const struct shader_info *info = &ish->nir->info;
@ -1161,7 +1161,7 @@ iris_compile_vs(struct iris_screen *screen,
const struct iris_vs_prog_key *key)
{
const struct brw_compiler *compiler = screen->compiler;
const struct gen_device_info *devinfo = &screen->devinfo;
const struct intel_device_info *devinfo = &screen->devinfo;
void *mem_ctx = ralloc_context(NULL);
struct brw_vs_prog_data *vs_prog_data =
rzalloc(mem_ctx, struct brw_vs_prog_data);
@ -1341,7 +1341,7 @@ iris_compile_tcs(struct iris_screen *screen,
rzalloc(mem_ctx, struct brw_tcs_prog_data);
struct brw_vue_prog_data *vue_prog_data = &tcs_prog_data->base;
struct brw_stage_prog_data *prog_data = &vue_prog_data->base;
const struct gen_device_info *devinfo = &screen->devinfo;
const struct intel_device_info *devinfo = &screen->devinfo;
enum brw_param_builtin *system_values = NULL;
unsigned num_system_values = 0;
unsigned num_cbufs = 0;
@ -1437,7 +1437,7 @@ iris_update_compiled_tcs(struct iris_context *ice)
struct iris_screen *screen = (struct iris_screen *)ice->ctx.screen;
struct u_upload_mgr *uploader = ice->shaders.uploader_driver;
const struct brw_compiler *compiler = screen->compiler;
const struct gen_device_info *devinfo = &screen->devinfo;
const struct intel_device_info *devinfo = &screen->devinfo;
const struct shader_info *tes_info =
iris_get_shader_info(ice, MESA_SHADER_TESS_EVAL);
@ -1499,7 +1499,7 @@ iris_compile_tes(struct iris_screen *screen,
struct brw_vue_prog_data *vue_prog_data = &tes_prog_data->base;
struct brw_stage_prog_data *prog_data = &vue_prog_data->base;
enum brw_param_builtin *system_values;
const struct gen_device_info *devinfo = &screen->devinfo;
const struct intel_device_info *devinfo = &screen->devinfo;
unsigned num_system_values;
unsigned num_cbufs;
@ -1620,7 +1620,7 @@ iris_compile_gs(struct iris_screen *screen,
const struct iris_gs_prog_key *key)
{
const struct brw_compiler *compiler = screen->compiler;
const struct gen_device_info *devinfo = &screen->devinfo;
const struct intel_device_info *devinfo = &screen->devinfo;
void *mem_ctx = ralloc_context(NULL);
struct brw_gs_prog_data *gs_prog_data =
rzalloc(mem_ctx, struct brw_gs_prog_data);
@ -1747,7 +1747,7 @@ iris_compile_fs(struct iris_screen *screen,
rzalloc(mem_ctx, struct brw_wm_prog_data);
struct brw_stage_prog_data *prog_data = &fs_prog_data->base;
enum brw_param_builtin *system_values;
const struct gen_device_info *devinfo = &screen->devinfo;
const struct intel_device_info *devinfo = &screen->devinfo;
unsigned num_system_values;
unsigned num_cbufs;
@ -2033,7 +2033,7 @@ iris_compile_cs(struct iris_screen *screen,
rzalloc(mem_ctx, struct brw_cs_prog_data);
struct brw_stage_prog_data *prog_data = &cs_prog_data->base;
enum brw_param_builtin *system_values;
const struct gen_device_info *devinfo = &screen->devinfo;
const struct intel_device_info *devinfo = &screen->devinfo;
unsigned num_system_values;
unsigned num_cbufs;
@ -2146,7 +2146,7 @@ iris_get_scratch_space(struct iris_context *ice,
{
struct iris_screen *screen = (struct iris_screen *)ice->ctx.screen;
struct iris_bufmgr *bufmgr = screen->bufmgr;
const struct gen_device_info *devinfo = &screen->devinfo;
const struct intel_device_info *devinfo = &screen->devinfo;
unsigned encoded_size = ffs(per_thread_scratch) - 11;
assert(encoded_size < (1 << 16));
@ -2228,7 +2228,7 @@ iris_create_uncompiled_shader(struct iris_screen *screen,
nir_shader *nir,
const struct pipe_stream_output_info *so_info)
{
const struct gen_device_info *devinfo = &screen->devinfo;
const struct intel_device_info *devinfo = &screen->devinfo;
struct iris_uncompiled_shader *ish =
calloc(1, sizeof(struct iris_uncompiled_shader));
@ -2433,7 +2433,7 @@ iris_create_fs_state(struct pipe_context *ctx,
bool can_rearrange_varyings =
util_bitcount64(info->inputs_read & BRW_FS_VARYING_INPUT_MASK) <= 16;
const struct gen_device_info *devinfo = &screen->devinfo;
const struct intel_device_info *devinfo = &screen->devinfo;
struct iris_fs_prog_key key = {
KEY_ID(base),
.nr_color_regions = util_bitcount(color_outputs),
@ -2682,7 +2682,7 @@ iris_bind_fs_state(struct pipe_context *ctx, void *state)
{
struct iris_context *ice = (struct iris_context *) ctx;
struct iris_screen *screen = (struct iris_screen *) ctx->screen;
const struct gen_device_info *devinfo = &screen->devinfo;
const struct intel_device_info *devinfo = &screen->devinfo;
struct iris_uncompiled_shader *old_ish =
ice->shaders.uncompiled[MESA_SHADER_FRAGMENT];
struct iris_uncompiled_shader *new_ish = state;

2
src/gallium/drivers/iris/iris_program_cache.c
View file

@ -123,7 +123,7 @@ iris_upload_shader(struct iris_screen *screen,
unsigned num_cbufs,
const struct iris_binding_table *bt)
{
const struct gen_device_info *devinfo = &screen->devinfo;
const struct intel_device_info *devinfo = &screen->devinfo;
void *mem_ctx = ish ? NULL : (void *) driver_shaders;
struct iris_compiled_shader *shader =

16
src/gallium/drivers/iris/iris_query.c
View file

@ -156,7 +156,7 @@ iris_pipelined_write(struct iris_batch *batch,
enum pipe_control_flags flags,
unsigned offset)
{
const struct gen_device_info *devinfo = &batch->screen->devinfo;
const struct intel_device_info *devinfo = &batch->screen->devinfo;
const unsigned optional_cs_stall =
GFX_VER == 9 && devinfo->gt == 4 ? PIPE_CONTROL_CS_STALL : 0;
struct iris_bo *bo = iris_resource_bo(q->query_state_ref.res);
@ -286,7 +286,7 @@ stream_overflowed(struct iris_query_so_overflow *so, int s)
}
static void
calculate_result_on_cpu(const struct gen_device_info *devinfo,
calculate_result_on_cpu(const struct intel_device_info *devinfo,
struct iris_query *q)
{
switch (q->type) {
@ -297,12 +297,12 @@ calculate_result_on_cpu(const struct gen_device_info *devinfo,
case PIPE_QUERY_TIMESTAMP:
case PIPE_QUERY_TIMESTAMP_DISJOINT:
/* The timestamp is the single starting snapshot. */
q->result = gen_device_info_timebase_scale(devinfo, q->map->start);
q->result = intel_device_info_timebase_scale(devinfo, q->map->start);
q->result &= (1ull << TIMESTAMP_BITS) - 1;
break;
case PIPE_QUERY_TIME_ELAPSED:
q->result = iris_raw_timestamp_delta(q->map->start, q->map->end);
q->result = gen_device_info_timebase_scale(devinfo, q->result);
q->result = intel_device_info_timebase_scale(devinfo, q->result);
q->result &= (1ull << TIMESTAMP_BITS) - 1;
break;
case PIPE_QUERY_SO_OVERFLOW_PREDICATE:
@ -385,7 +385,7 @@ query_is_boolean(enum pipe_query_type type)
* Calculate the result using MI_MATH.
*/
static struct mi_value
calculate_result_on_gpu(const struct gen_device_info *devinfo,
calculate_result_on_gpu(const struct intel_device_info *devinfo,
struct mi_builder *b,
struct iris_query *q)
{
@ -590,7 +590,7 @@ static void
iris_check_query_no_flush(struct iris_context *ice, struct iris_query *q)
{
struct iris_screen *screen = (void *) ice->ctx.screen;
const struct gen_device_info *devinfo = &screen->devinfo;
const struct intel_device_info *devinfo = &screen->devinfo;
if (!q->ready && READ_ONCE(q->map->snapshots_landed)) {
calculate_result_on_cpu(devinfo, q);
@ -610,7 +610,7 @@ iris_get_query_result(struct pipe_context *ctx,
return iris_get_monitor_result(ctx, q->monitor, wait, result->batch);
struct iris_screen *screen = (void *) ctx->screen;
const struct gen_device_info *devinfo = &screen->devinfo;
const struct intel_device_info *devinfo = &screen->devinfo;
if (unlikely(screen->no_hw)) {
result->u64 = 0;
@ -660,7 +660,7 @@ iris_get_query_result_resource(struct pipe_context *ctx,
struct iris_context *ice = (void *) ctx;
struct iris_query *q = (void *) query;
struct iris_batch *batch = &ice->batches[q->batch_idx];
const struct gen_device_info *devinfo = &batch->screen->devinfo;
const struct intel_device_info *devinfo = &batch->screen->devinfo;
struct iris_resource *res = (void *) p_res;
struct iris_bo *query_bo = iris_resource_bo(q->query_state_ref.res);
struct iris_bo *dst_bo = iris_resource_bo(p_res);

8
src/gallium/drivers/iris/iris_resolve.c
View file

@ -186,7 +186,7 @@ iris_predraw_resolve_framebuffer(struct iris_context *ice,
{
struct pipe_framebuffer_state *cso_fb = &ice->state.framebuffer;
struct iris_screen *screen = (void *) ice->ctx.screen;
struct gen_device_info *devinfo = &screen->devinfo;
struct intel_device_info *devinfo = &screen->devinfo;
struct iris_uncompiled_shader *ish =
ice->shaders.uncompiled[MESA_SHADER_FRAGMENT];
const nir_shader *nir = ish->nir;
@ -444,7 +444,7 @@ iris_mcs_partial_resolve(struct iris_context *ice,
}
bool
iris_sample_with_depth_aux(const struct gen_device_info *devinfo,
iris_sample_with_depth_aux(const struct intel_device_info *devinfo,
const struct iris_resource *res)
{
switch (res->aux.usage) {
@ -814,7 +814,7 @@ iris_resource_texture_aux_usage(struct iris_context *ice,
enum isl_format view_format)
{
struct iris_screen *screen = (void *) ice->ctx.screen;
struct gen_device_info *devinfo = &screen->devinfo;
struct intel_device_info *devinfo = &screen->devinfo;
switch (res->aux.usage) {
case ISL_AUX_USAGE_HIZ:
@ -952,7 +952,7 @@ iris_resource_render_aux_usage(struct iris_context *ice,
bool draw_aux_disabled)
{
struct iris_screen *screen = (void *) ice->ctx.screen;
struct gen_device_info *devinfo = &screen->devinfo;
struct intel_device_info *devinfo = &screen->devinfo;
if (draw_aux_disabled)
return ISL_AUX_USAGE_NONE;

22
src/gallium/drivers/iris/iris_resource.c
View file

@ -75,7 +75,7 @@ static const uint64_t priority_to_modifier[] = {
};
static bool
modifier_is_supported(const struct gen_device_info *devinfo,
modifier_is_supported(const struct intel_device_info *devinfo,
enum pipe_format pfmt, uint64_t modifier)
{
/* Check for basic device support. */
@ -138,7 +138,7 @@ modifier_is_supported(const struct gen_device_info *devinfo,
}
static uint64_t
select_best_modifier(struct gen_device_info *devinfo, enum pipe_format pfmt,
select_best_modifier(struct intel_device_info *devinfo, enum pipe_format pfmt,
const uint64_t *modifiers,
int count)
{
@ -198,7 +198,7 @@ iris_query_dmabuf_modifiers(struct pipe_screen *pscreen,
int *count)
{
struct iris_screen *screen = (void *) pscreen;
const struct gen_device_info *devinfo = &screen->devinfo;
const struct intel_device_info *devinfo = &screen->devinfo;
uint64_t all_modifiers[] = {
DRM_FORMAT_MOD_LINEAR,
@ -238,7 +238,7 @@ iris_is_dmabuf_modifier_supported(struct pipe_screen *pscreen,
bool *external_only)
{
struct iris_screen *screen = (void *) pscreen;
const struct gen_device_info *devinfo = &screen->devinfo;
const struct intel_device_info *devinfo = &screen->devinfo;
if (modifier_is_supported(devinfo, pfmt, modifier)) {
if (external_only)
@ -273,7 +273,7 @@ iris_image_view_get_format(struct iris_context *ice,
const struct pipe_image_view *img)
{
struct iris_screen *screen = (struct iris_screen *)ice->ctx.screen;
const struct gen_device_info *devinfo = &screen->devinfo;
const struct intel_device_info *devinfo = &screen->devinfo;
isl_surf_usage_flags_t usage = ISL_SURF_USAGE_STORAGE_BIT;
enum isl_format isl_fmt =
@ -398,7 +398,7 @@ iris_get_depth_stencil_resources(struct pipe_resource *res,
}
enum isl_dim_layout
iris_get_isl_dim_layout(const struct gen_device_info *devinfo,
iris_get_isl_dim_layout(const struct intel_device_info *devinfo,
enum isl_tiling tiling,
enum pipe_texture_target target)
{
@ -531,7 +531,7 @@ create_aux_state_map(struct iris_resource *res, enum isl_aux_state initial)
static unsigned
iris_get_aux_clear_color_state_size(struct iris_screen *screen)
{
const struct gen_device_info *devinfo = &screen->devinfo;
const struct intel_device_info *devinfo = &screen->devinfo;
return devinfo->ver >= 10 ? screen->isl_dev.ss.clear_color_state_size : 0;
}
@ -539,7 +539,7 @@ static void
map_aux_addresses(struct iris_screen *screen, struct iris_resource *res,
enum isl_format format, unsigned plane)
{
const struct gen_device_info *devinfo = &screen->devinfo;
const struct intel_device_info *devinfo = &screen->devinfo;
if (devinfo->ver >= 12 && isl_aux_usage_has_ccs(res->aux.usage)) {
void *aux_map_ctx = iris_bufmgr_get_aux_map_context(screen->bufmgr);
assert(aux_map_ctx);
@ -555,7 +555,7 @@ map_aux_addresses(struct iris_screen *screen, struct iris_resource *res,
}
static bool
want_ccs_e_for_format(const struct gen_device_info *devinfo,
want_ccs_e_for_format(const struct intel_device_info *devinfo,
enum isl_format format)
{
if (!isl_format_supports_ccs_e(devinfo, format))
@ -671,7 +671,7 @@ static bool
iris_resource_configure_aux(struct iris_screen *screen,
struct iris_resource *res, bool imported)
{
const struct gen_device_info *devinfo = &screen->devinfo;
const struct intel_device_info *devinfo = &screen->devinfo;
/* Try to create the auxiliary surfaces allowed by the modifier or by
* the user if no modifier is specified.
@ -978,7 +978,7 @@ iris_resource_create_with_modifiers(struct pipe_screen *pscreen,
int modifiers_count)
{
struct iris_screen *screen = (struct iris_screen *)pscreen;
struct gen_device_info *devinfo = &screen->devinfo;
struct intel_device_info *devinfo = &screen->devinfo;
struct iris_resource *res = iris_alloc_resource(pscreen, templ);
if (!res)

6
src/gallium/drivers/iris/iris_resource.h
View file

@ -305,7 +305,7 @@ iris_mocs(const struct iris_bo *bo,
return isl_mocs(dev, usage, bo && bo->external);
}
struct iris_format_info iris_format_for_usage(const struct gen_device_info *,
struct iris_format_info iris_format_for_usage(const struct intel_device_info *,
enum pipe_format pf,
isl_surf_usage_flags_t usage);
@ -459,7 +459,7 @@ iris_resource_access_raw(struct iris_context *ice,
}
}
enum isl_dim_layout iris_get_isl_dim_layout(const struct gen_device_info *devinfo,
enum isl_dim_layout iris_get_isl_dim_layout(const struct intel_device_info *devinfo,
enum isl_tiling tiling,
enum pipe_texture_target target);
static inline enum isl_surf_dim
@ -522,7 +522,7 @@ void iris_resource_check_level_layer(const struct iris_resource *res,
bool iris_resource_level_has_hiz(const struct iris_resource *res,
uint32_t level);
bool iris_sample_with_depth_aux(const struct gen_device_info *devinfo,
bool iris_sample_with_depth_aux(const struct intel_device_info *devinfo,
const struct iris_resource *res);
bool iris_has_color_unresolved(const struct iris_resource *res,

12
src/gallium/drivers/iris/iris_screen.c
View file

@ -113,7 +113,7 @@ static void
iris_get_driver_uuid(struct pipe_screen *pscreen, char *uuid)
{
struct iris_screen *screen = (struct iris_screen *)pscreen;
const struct gen_device_info *devinfo = &screen->devinfo;
const struct intel_device_info *devinfo = &screen->devinfo;
intel_uuid_compute_driver_id((uint8_t *)uuid, devinfo, PIPE_UUID_SIZE);
}
@ -158,7 +158,7 @@ static int
iris_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
{
struct iris_screen *screen = (struct iris_screen *)pscreen;
const struct gen_device_info *devinfo = &screen->devinfo;
const struct intel_device_info *devinfo = &screen->devinfo;
switch (param) {
case PIPE_CAP_NPOT_TEXTURES:
@ -524,7 +524,7 @@ iris_get_compute_param(struct pipe_screen *pscreen,
void *ret)
{
struct iris_screen *screen = (struct iris_screen *)pscreen;
const struct gen_device_info *devinfo = &screen->devinfo;
const struct intel_device_info *devinfo = &screen->devinfo;
/* Limit max_threads to 64 for the GPGPU_WALKER command. */
const unsigned max_threads = MIN2(64, devinfo->max_cs_threads);
@ -611,7 +611,7 @@ iris_get_timestamp(struct pipe_screen *pscreen)
iris_reg_read(screen->bufmgr, TIMESTAMP | 1, &result);
result = gen_device_info_timebase_scale(&screen->devinfo, result);
result = intel_device_info_timebase_scale(&screen->devinfo, result);
result &= (1ull << TIMESTAMP_BITS) - 1;
return result;
@ -684,7 +684,7 @@ iris_getparam_integer(int fd, int param)
}
static const struct intel_l3_config *
iris_get_default_l3_config(const struct gen_device_info *devinfo,
iris_get_default_l3_config(const struct intel_device_info *devinfo,
bool compute)
{
bool wants_dc_cache = true;
@ -848,7 +848,7 @@ iris_screen_create(int fd, const struct pipe_screen_config *config)
slab_create_parent(&screen->transfer_pool,
sizeof(struct iris_transfer), 64);
screen->subslice_total = gen_device_info_subslice_total(&screen->devinfo);
screen->subslice_total = intel_device_info_subslice_total(&screen->devinfo);
assert(screen->subslice_total >= 1);
iris_detect_kernel_features(screen);

4
src/gallium/drivers/iris/iris_screen.h
View file

@ -110,7 +110,7 @@ struct iris_vtable {
uint32_t report_id);
unsigned (*derived_program_state_size)(enum iris_program_cache_id id);
void (*store_derived_program_state)(const struct gen_device_info *devinfo,
void (*store_derived_program_state)(const struct intel_device_info *devinfo,
enum iris_program_cache_id cache_id,
struct iris_compiled_shader *shader);
uint32_t *(*create_so_decl_list)(const struct pipe_stream_output_info *sol,
@ -198,7 +198,7 @@ struct iris_screen {
*/
uint64_t last_seqno;
struct gen_device_info devinfo;
struct intel_device_info devinfo;
struct isl_device isl_dev;
struct iris_bufmgr *bufmgr;
struct brw_compiler *compiler;

42
src/gallium/drivers/iris/iris_state.c
View file

@ -382,7 +382,7 @@ emit_state(struct iris_batch *batch,
static void
flush_before_state_base_change(struct iris_batch *batch)
{
const struct gen_device_info *devinfo = &batch->screen->devinfo;
const struct intel_device_info *devinfo = &batch->screen->devinfo;
/* Flush before emitting STATE_BASE_ADDRESS.
*
@ -838,7 +838,7 @@ calculate_pixel_hashing_table(unsigned n, unsigned m,
static void
gfx11_upload_pixel_hashing_tables(struct iris_batch *batch)
{
const struct gen_device_info *devinfo = &batch->screen->devinfo;
const struct intel_device_info *devinfo = &batch->screen->devinfo;
assert(devinfo->ppipe_subslices[2] == 0);
if (devinfo->ppipe_subslices[0] == devinfo->ppipe_subslices[1])
@ -874,7 +874,7 @@ gfx11_upload_pixel_hashing_tables(struct iris_batch *batch)
static void
gfx12_upload_pixel_hashing_tables(struct iris_batch *batch)
{
const struct gen_device_info *devinfo = &batch->screen->devinfo;
const struct intel_device_info *devinfo = &batch->screen->devinfo;
/* For each n calculate ppipes_of[n], equal to the number of pixel pipes
* present with n active dual subslices.
*/
@ -977,7 +977,7 @@ iris_init_common_context(struct iris_batch *batch)
static void
iris_init_render_context(struct iris_batch *batch)
{
UNUSED const struct gen_device_info *devinfo = &batch->screen->devinfo;
UNUSED const struct intel_device_info *devinfo = &batch->screen->devinfo;
iris_batch_sync_region_start(batch);
@ -1087,7 +1087,7 @@ iris_init_render_context(struct iris_batch *batch)
static void
iris_init_compute_context(struct iris_batch *batch)
{
UNUSED const struct gen_device_info *devinfo = &batch->screen->devinfo;
UNUSED const struct intel_device_info *devinfo = &batch->screen->devinfo;
iris_batch_sync_region_start(batch);
@ -1511,7 +1511,7 @@ static bool
want_pma_fix(struct iris_context *ice)
{
UNUSED struct iris_screen *screen = (void *) ice->ctx.screen;
UNUSED const struct gen_device_info *devinfo = &screen->devinfo;
UNUSED const struct intel_device_info *devinfo = &screen->devinfo;
const struct brw_wm_prog_data *wm_prog_data = (void *)
ice->shaders.prog[MESA_SHADER_FRAGMENT]->prog_data;
const struct pipe_framebuffer_state *cso_fb = &ice->state.framebuffer;
@ -2313,7 +2313,7 @@ update_surface_state_addrs(struct u_upload_mgr *mgr,
* to the single slice of the texture being read.
*/
static void
get_rt_read_isl_surf(const struct gen_device_info *devinfo,
get_rt_read_isl_surf(const struct intel_device_info *devinfo,
struct iris_resource *res,
enum pipe_texture_target target,
struct isl_view *view,
@ -2413,7 +2413,7 @@ iris_create_sampler_view(struct pipe_context *ctx,
const struct pipe_sampler_view *tmpl)
{
struct iris_screen *screen = (struct iris_screen *)ctx->screen;
const struct gen_device_info *devinfo = &screen->devinfo;
const struct intel_device_info *devinfo = &screen->devinfo;
struct iris_sampler_view *isv = calloc(1, sizeof(struct iris_sampler_view));
if (!isv)
@ -2520,7 +2520,7 @@ iris_create_surface(struct pipe_context *ctx,
const struct pipe_surface *tmpl)
{
struct iris_screen *screen = (struct iris_screen *)ctx->screen;
const struct gen_device_info *devinfo = &screen->devinfo;
const struct intel_device_info *devinfo = &screen->devinfo;
isl_surf_usage_flags_t usage = 0;
if (tmpl->writable)
@ -3549,7 +3549,7 @@ iris_create_vertex_elements(struct pipe_context *ctx,
const struct pipe_vertex_element *state)
{
struct iris_screen *screen = (struct iris_screen *)ctx->screen;
const struct gen_device_info *devinfo = &screen->devinfo;
const struct intel_device_info *devinfo = &screen->devinfo;
struct iris_vertex_element_state *cso =
malloc(sizeof(struct iris_vertex_element_state));
@ -4364,7 +4364,7 @@ KSP(const struct iris_compiled_shader *shader)
* Encode most of 3DSTATE_VS based on the compiled shader.
*/
static void
iris_store_vs_state(const struct gen_device_info *devinfo,
iris_store_vs_state(const struct intel_device_info *devinfo,
struct iris_compiled_shader *shader)
{
struct brw_stage_prog_data *prog_data = shader->prog_data;
@ -4383,7 +4383,7 @@ iris_store_vs_state(const struct gen_device_info *devinfo,
* Encode most of 3DSTATE_HS based on the compiled shader.
*/
static void
iris_store_tcs_state(const struct gen_device_info *devinfo,
iris_store_tcs_state(const struct intel_device_info *devinfo,
struct iris_compiled_shader *shader)
{
struct brw_stage_prog_data *prog_data = shader->prog_data;
@ -4427,7 +4427,7 @@ iris_store_tcs_state(const struct gen_device_info *devinfo,
* Encode 3DSTATE_TE and most of 3DSTATE_DS based on the compiled shader.
*/
static void
iris_store_tes_state(const struct gen_device_info *devinfo,
iris_store_tes_state(const struct intel_device_info *devinfo,
struct iris_compiled_shader *shader)
{
struct brw_stage_prog_data *prog_data = shader->prog_data;
@ -4464,7 +4464,7 @@ iris_store_tes_state(const struct gen_device_info *devinfo,
* Encode most of 3DSTATE_GS based on the compiled shader.
*/
static void
iris_store_gs_state(const struct gen_device_info *devinfo,
iris_store_gs_state(const struct intel_device_info *devinfo,
struct iris_compiled_shader *shader)
{
struct brw_stage_prog_data *prog_data = shader->prog_data;
@ -4511,7 +4511,7 @@ iris_store_gs_state(const struct gen_device_info *devinfo,
* Encode most of 3DSTATE_PS and 3DSTATE_PS_EXTRA based on the shader.
*/
static void
iris_store_fs_state(const struct gen_device_info *devinfo,
iris_store_fs_state(const struct intel_device_info *devinfo,
struct iris_compiled_shader *shader)
{
struct brw_stage_prog_data *prog_data = shader->prog_data;
@ -4571,7 +4571,7 @@ iris_store_fs_state(const struct gen_device_info *devinfo,
* This must match the data written by the iris_store_xs_state() functions.
*/
static void
iris_store_cs_state(const struct gen_device_info *devinfo,
iris_store_cs_state(const struct intel_device_info *devinfo,
struct iris_compiled_shader *shader)
{
struct brw_cs_prog_data *cs_prog_data = (void *) shader->prog_data;
@ -4628,7 +4628,7 @@ iris_derived_program_state_size(enum iris_program_cache_id cache_id)
* get most of the state packet without having to reconstruct it.
*/
static void
iris_store_derived_program_state(const struct gen_device_info *devinfo,
iris_store_derived_program_state(const struct intel_device_info *devinfo,
enum iris_program_cache_id cache_id,
struct iris_compiled_shader *shader)
{
@ -6845,7 +6845,7 @@ iris_upload_compute_walker(struct iris_context *ice,
{
const uint64_t stage_dirty = ice->state.stage_dirty;
struct iris_screen *screen = batch->screen;
const struct gen_device_info *devinfo = &screen->devinfo;
const struct intel_device_info *devinfo = &screen->devinfo;
struct iris_binder *binder = &ice->state.binder;
struct iris_shader_state *shs = &ice->state.shaders[MESA_SHADER_COMPUTE];
struct iris_compiled_shader *shader =
@ -6907,7 +6907,7 @@ iris_upload_gpgpu_walker(struct iris_context *ice,
{
const uint64_t stage_dirty = ice->state.stage_dirty;
struct iris_screen *screen = batch->screen;
const struct gen_device_info *devinfo = &screen->devinfo;
const struct intel_device_info *devinfo = &screen->devinfo;
struct iris_binder *binder = &ice->state.binder;
struct iris_shader_state *shs = &ice->state.shaders[MESA_SHADER_COMPUTE];
struct iris_uncompiled_shader *ish =
@ -7408,7 +7408,7 @@ iris_emit_raw_pipe_control(struct iris_batch *batch,
uint32_t offset,
uint64_t imm)
{
UNUSED const struct gen_device_info *devinfo = &batch->screen->devinfo;
UNUSED const struct intel_device_info *devinfo = &batch->screen->devinfo;
enum pipe_control_flags post_sync_flags = get_post_sync_flags(flags);
enum pipe_control_flags non_lri_post_sync_flags =
post_sync_flags & ~PIPE_CONTROL_LRI_POST_SYNC_OP;
@ -7921,7 +7921,7 @@ genX(emit_hashing_mode)(struct iris_context *ice, struct iris_batch *batch,
unsigned width, unsigned height, unsigned scale)
{
#if GFX_VER == 9
const struct gen_device_info *devinfo = &batch->screen->devinfo;
const struct intel_device_info *devinfo = &batch->screen->devinfo;
const unsigned slice_hashing[] = {
/* Because all Gfx9 platforms with more than one slice require
* three-way subslice hashing, a single "normal" 16x16 slice hashing

2
src/intel/blorp/blorp.c
View file

@ -335,7 +335,7 @@ blorp_hiz_op(struct blorp_batch *batch, struct blorp_surf *surf,
uint32_t level, uint32_t start_layer, uint32_t num_layers,
enum isl_aux_op op)
{
const struct gen_device_info *devinfo = batch->blorp->isl_dev->info;
const struct intel_device_info *devinfo = batch->blorp->isl_dev->info;
struct blorp_params params;
blorp_params_init(&params);

2
src/intel/blorp/blorp.h
View file

@ -187,7 +187,7 @@ blorp_clear_depth_stencil(struct blorp_batch *batch,
bool clear_depth, float depth_value,
uint8_t stencil_mask, uint8_t stencil_value);
bool
blorp_can_hiz_clear_depth(const struct gen_device_info *devinfo,
blorp_can_hiz_clear_depth(const struct intel_device_info *devinfo,
const struct isl_surf *surf,
enum isl_aux_usage aux_usage,
uint32_t level, uint32_t layer,

8
src/intel/blorp/blorp_blit.c
View file

@ -1165,7 +1165,7 @@ static nir_shader *
brw_blorp_build_nir_shader(struct blorp_context *blorp, void *mem_ctx,
const struct brw_blorp_blit_prog_key *key)
{
const struct gen_device_info *devinfo = blorp->isl_dev->info;
const struct intel_device_info *devinfo = blorp->isl_dev->info;
nir_ssa_def *src_pos, *dst_pos, *color;
/* Sanity checks */
@ -1695,7 +1695,7 @@ can_shrink_surface(const struct brw_blorp_surface_info *surf)
}
static unsigned
get_max_surface_size(const struct gen_device_info *devinfo,
get_max_surface_size(const struct intel_device_info *devinfo,
const struct brw_blorp_surface_info *surf)
{
const unsigned max = devinfo->ver >= 7 ? 16384 : 8192;
@ -1803,7 +1803,7 @@ try_blorp_blit(struct blorp_batch *batch,
struct brw_blorp_blit_prog_key *wm_prog_key,
struct blt_coords *coords)
{
const struct gen_device_info *devinfo = batch->blorp->isl_dev->info;
const struct intel_device_info *devinfo = batch->blorp->isl_dev->info;
if (params->dst.surf.usage & ISL_SURF_USAGE_DEPTH_BIT) {
if (devinfo->ver >= 7) {
@ -2846,7 +2846,7 @@ blorp_buffer_copy(struct blorp_batch *batch,
struct blorp_address dst,
uint64_t size)
{
const struct gen_device_info *devinfo = batch->blorp->isl_dev->info;
const struct intel_device_info *devinfo = batch->blorp->isl_dev->info;
uint64_t copy_size = size;
/* This is maximum possible width/height our HW can handle */

2
src/intel/blorp/blorp_clear.c
View file

@ -756,7 +756,7 @@ blorp_clear_depth_stencil(struct blorp_batch *batch,
}
bool
blorp_can_hiz_clear_depth(const struct gen_device_info *devinfo,
blorp_can_hiz_clear_depth(const struct intel_device_info *devinfo,
const struct isl_surf *surf,
enum isl_aux_usage aux_usage,
uint32_t level, uint32_t layer,

2
src/intel/common/intel_aux_map.c
View file

@ -200,7 +200,7 @@ intel_aux_map_get_state_num(struct intel_aux_map_context *ctx)
struct intel_aux_map_context *
intel_aux_map_init(void *driver_ctx,
struct gen_mapped_pinned_buffer_alloc *buffer_alloc,
const struct gen_device_info *devinfo)
const struct intel_device_info *devinfo)
{
struct intel_aux_map_context *ctx;
if (devinfo->ver < 12)

4
src/intel/common/intel_aux_map.h
View file

@ -41,7 +41,7 @@ extern "C" {
*/
struct intel_aux_map_context;
struct gen_device_info;
struct intel_device_info;
#define INTEL_AUX_MAP_ADDRESS_MASK 0x0000ffffffffff00ull
#define INTEL_AUX_MAP_FORMAT_BITS_MASK 0xfff0000000000000ull
@ -54,7 +54,7 @@ struct gen_device_info;
struct intel_aux_map_context *
intel_aux_map_init(void *driver_ctx,
struct gen_mapped_pinned_buffer_alloc *buffer_alloc,
const struct gen_device_info *devinfo);
const struct intel_device_info *devinfo);
void
intel_aux_map_finish(struct intel_aux_map_context *ctx);

2
src/intel/common/intel_batch_decoder.c
View file

@ -30,7 +30,7 @@
void
intel_batch_decode_ctx_init(struct intel_batch_decode_ctx *ctx,
const struct gen_device_info *devinfo,
const struct intel_device_info *devinfo,
FILE *fp, enum intel_batch_decode_flags flags,
const char *xml_path,
struct intel_batch_decode_bo (*get_bo)(void *,

2
src/intel/common/intel_batch_decoder_stub.c
View file

@ -26,7 +26,7 @@
void
intel_batch_decode_ctx_init(struct intel_batch_decode_ctx *ctx,
const struct gen_device_info *devinfo,
const struct intel_device_info *devinfo,
FILE *fp, enum intel_batch_decode_flags flags,
const char *xml_path,
struct intel_batch_decode_bo (*get_bo)(void *,

6
src/intel/common/intel_decoder.c
View file

@ -508,7 +508,7 @@ character_data(void *data, const XML_Char *s, int len)
}
static int
devinfo_to_gen(const struct gen_device_info *devinfo, bool x10)
devinfo_to_gen(const struct intel_device_info *devinfo, bool x10)
{
if (devinfo->is_baytrail || devinfo->is_haswell) {
return devinfo->ver * 10 + 5;
@ -595,7 +595,7 @@ intel_spec_init(void)
}
struct intel_spec *
intel_spec_load(const struct gen_device_info *devinfo)
intel_spec_load(const struct intel_device_info *devinfo)
{
struct parser_context ctx;
void *buf;
@ -735,7 +735,7 @@ intel_spec_load_filename(const char *filename)
}
struct intel_spec *
intel_spec_load_from_path(const struct gen_device_info *devinfo,
intel_spec_load_from_path(const struct intel_device_info *devinfo,
const char *path)
{
size_t filename_len = strlen(path) + 20;

8
src/intel/common/intel_decoder.h
View file

@ -51,8 +51,8 @@ static inline uint32_t intel_make_gen(uint32_t major, uint32_t minor)
}
struct intel_group *intel_spec_find_struct(struct intel_spec *spec, const char *name);
struct intel_spec *intel_spec_load(const struct gen_device_info *devinfo);
struct intel_spec *intel_spec_load_from_path(const struct gen_device_info *devinfo,
struct intel_spec *intel_spec_load(const struct intel_device_info *devinfo);
struct intel_spec *intel_spec_load_from_path(const struct intel_device_info *devinfo,
const char *path);
struct intel_spec *intel_spec_load_filename(const char *filename);
void intel_spec_destroy(struct intel_spec *spec);
@ -236,7 +236,7 @@ struct intel_batch_decode_ctx {
void *user_data;
FILE *fp;
struct gen_device_info devinfo;
struct intel_device_info devinfo;
struct intel_spec *spec;
enum intel_batch_decode_flags flags;
@ -254,7 +254,7 @@ struct intel_batch_decode_ctx {
};
void intel_batch_decode_ctx_init(struct intel_batch_decode_ctx *ctx,
const struct gen_device_info *devinfo,
const struct intel_device_info *devinfo,
FILE *fp, enum intel_batch_decode_flags flags,
const char *xml_path,
struct intel_batch_decode_bo (*get_bo)(void *,

4
src/intel/common/intel_disasm.c
View file

@ -38,7 +38,7 @@ is_send(uint32_t opcode)
}
static int
intel_disasm_find_end(const struct gen_device_info *devinfo,
intel_disasm_find_end(const struct intel_device_info *devinfo,
const void *assembly, int start)
{
int offset = start;
@ -64,7 +64,7 @@ intel_disasm_find_end(const struct gen_device_info *devinfo,
}
void
intel_disassemble(const struct gen_device_info *devinfo,
intel_disassemble(const struct intel_device_info *devinfo,
const void *assembly, int start, FILE *out)
{
int end = intel_disasm_find_end(devinfo, assembly, start);

2
src/intel/common/intel_disasm.h
View file

@ -30,7 +30,7 @@
extern "C" {
#endif
void intel_disassemble(const struct gen_device_info *devinfo,
void intel_disassemble(const struct intel_device_info *devinfo,
const void *assembly, int start, FILE *out);
#ifdef __cplusplus

16
src/intel/common/intel_l3_config.c
View file

@ -161,7 +161,7 @@ DECLARE_L3_LIST(dg1);
* specified device.
*/
static const struct intel_l3_list *
get_l3_list(const struct gen_device_info *devinfo)
get_l3_list(const struct intel_device_info *devinfo)
{
switch (devinfo->ver) {
case 7:
@ -257,7 +257,7 @@ intel_diff_l3_weights(struct intel_l3_weights w0, struct intel_l3_weights w1)
* is intended to approximately resemble the hardware defaults.
*/
struct intel_l3_weights
intel_get_default_l3_weights(const struct gen_device_info *devinfo,
intel_get_default_l3_weights(const struct intel_device_info *devinfo,
bool needs_dc, bool needs_slm)
{
struct intel_l3_weights w = {{ 0 }};
@ -279,7 +279,7 @@ intel_get_default_l3_weights(const struct gen_device_info *devinfo,
* Get the default L3 configuration
*/
const struct intel_l3_config *
intel_get_default_l3_config(const struct gen_device_info *devinfo)
intel_get_default_l3_config(const struct intel_device_info *devinfo)
{
/* For efficiency assume that the first entry of the array matches the
* default configuration.
@ -301,7 +301,7 @@ intel_get_default_l3_config(const struct gen_device_info *devinfo)
* weight vector.
*/
const struct intel_l3_config *
intel_get_l3_config(const struct gen_device_info *devinfo,
intel_get_l3_config(const struct intel_device_info *devinfo,
struct intel_l3_weights w0)
{
const struct intel_l3_list *const list = get_l3_list(devinfo);
@ -327,7 +327,7 @@ intel_get_l3_config(const struct gen_device_info *devinfo,
* Return the size of an L3 way in KB.
*/
static unsigned
get_l3_way_size(const struct gen_device_info *devinfo)
get_l3_way_size(const struct intel_device_info *devinfo)
{
const unsigned way_size_per_bank =
(devinfo->ver >= 9 && devinfo->l3_banks == 1) || devinfo->ver >= 11 ?
@ -339,16 +339,16 @@ get_l3_way_size(const struct gen_device_info *devinfo)
/**
* Return the unit brw_context::urb::size is expressed in, in KB. \sa
* gen_device_info::urb::size.
* intel_device_info::urb::size.
*/
static unsigned
get_urb_size_scale(const struct gen_device_info *devinfo)
get_urb_size_scale(const struct intel_device_info *devinfo)
{
return (devinfo->ver >= 8 ? devinfo->num_slices : 1);
}
unsigned
intel_get_l3_config_urb_size(const struct gen_device_info *devinfo,
intel_get_l3_config_urb_size(const struct intel_device_info *devinfo,
const struct intel_l3_config *cfg)
{
/* We don't have to program the URB size in DG1, it's a fixed value. */

10
src/intel/common/intel_l3_config.h
View file

@ -73,21 +73,21 @@ struct intel_l3_weights {
float intel_diff_l3_weights(struct intel_l3_weights w0, struct intel_l3_weights w1);
struct intel_l3_weights
intel_get_default_l3_weights(const struct gen_device_info *devinfo,
intel_get_default_l3_weights(const struct intel_device_info *devinfo,
bool needs_dc, bool needs_slm);
struct intel_l3_weights
intel_get_l3_config_weights(const struct intel_l3_config *cfg);
const struct intel_l3_config *
intel_get_default_l3_config(const struct gen_device_info *devinfo);
intel_get_default_l3_config(const struct intel_device_info *devinfo);
const struct intel_l3_config *
intel_get_l3_config(const struct gen_device_info *devinfo,
intel_get_l3_config(const struct intel_device_info *devinfo,
struct intel_l3_weights w0);
unsigned
intel_get_l3_config_urb_size(const struct gen_device_info *devinfo,
intel_get_l3_config_urb_size(const struct intel_device_info *devinfo,
const struct intel_l3_config *cfg);
void intel_dump_l3_config(const struct intel_l3_config *cfg, FILE *fp);
@ -98,7 +98,7 @@ enum intel_urb_deref_block_size {
INTEL_URB_DEREF_BLOCK_SIZE_8 = 2,
};
void intel_get_urb_config(const struct gen_device_info *devinfo,
void intel_get_urb_config(const struct intel_device_info *devinfo,
const struct intel_l3_config *l3_cfg,
bool tess_present, bool gs_present,
const unsigned entry_size[4],

10
src/intel/common/intel_measure.c
View file

@ -563,7 +563,7 @@ buffered_event_count(struct intel_measure_device *device)
static void
print_combined_results(struct intel_measure_device *measure_device,
int result_count,
struct gen_device_info *info)
struct intel_device_info *info)
{
if (result_count == 0)
return;
@ -601,8 +601,8 @@ print_combined_results(struct intel_measure_device *measure_device,
begin->event_name, begin->count,
begin->vs, begin->tcs, begin->tes, begin->gs, begin->fs, begin->cs,
begin->framebuffer,
gen_device_info_timebase_scale(info, start_result->idle_duration),
gen_device_info_timebase_scale(info, duration_ts));
intel_device_info_timebase_scale(info, start_result->idle_duration),
intel_device_info_timebase_scale(info, duration_ts));
}
/**
@ -610,7 +610,7 @@ print_combined_results(struct intel_measure_device *measure_device,
*/
static void
intel_measure_print(struct intel_measure_device *device,
struct gen_device_info *info)
struct intel_device_info *info)
{
while (true) {
const int events_to_combine = buffered_event_count(device);
@ -626,7 +626,7 @@ intel_measure_print(struct intel_measure_device *device,
*/
void
intel_measure_gather(struct intel_measure_device *measure_device,
struct gen_device_info *info)
struct intel_device_info *info)
{
pthread_mutex_lock(&measure_device->mutex);

4
src/intel/common/intel_measure.h
View file

@ -158,8 +158,8 @@ void intel_measure_frame_transition(unsigned frame);
bool intel_measure_ready(struct intel_measure_batch *batch);
struct gen_device_info;
struct intel_device_info;
void intel_measure_gather(struct intel_measure_device *device,
struct gen_device_info *info);
struct intel_device_info *info);
#endif /* INTEL_MEASURE_H */

2
src/intel/common/intel_urb_config.c
View file

@ -60,7 +60,7 @@
* \param[out] constrained - true if we wanted more space than we had
*/
void
intel_get_urb_config(const struct gen_device_info *devinfo,
intel_get_urb_config(const struct intel_device_info *devinfo,
const struct intel_l3_config *l3_cfg,
bool tess_present, bool gs_present,
const unsigned entry_size[4],

4
src/intel/common/intel_uuid.c
View file

@ -32,7 +32,7 @@ intel_uuid_compute_device_id(uint8_t *uuid,
{
struct mesa_sha1 sha1_ctx;
uint8_t sha1[20];
const struct gen_device_info *devinfo = isldev->info;
const struct intel_device_info *devinfo = isldev->info;
assert(size <= sizeof(sha1));
@ -53,7 +53,7 @@ intel_uuid_compute_device_id(uint8_t *uuid,
void
intel_uuid_compute_driver_id(uint8_t *uuid,
const struct gen_device_info *devinfo,
const struct intel_device_info *devinfo,
size_t size)
{
const char* intelDriver = PACKAGE_VERSION MESA_GIT_SHA1;

2
src/intel/common/intel_uuid.h
View file

@ -37,7 +37,7 @@ void intel_uuid_compute_device_id(uint8_t *uuid,
size_t size);
void intel_uuid_compute_driver_id(uint8_t *uuid,
const struct gen_device_info *devinfo,
const struct intel_device_info *devinfo,
size_t size);
#ifdef __cplusplus

4
src/intel/common/mi_builder.h
View file

@ -129,7 +129,7 @@ mi_adjust_reg_num(uint32_t reg)
#endif
struct mi_builder {
const struct gen_device_info *devinfo;
const struct intel_device_info *devinfo;
__gen_user_data *user_data;
#if GFX_VERx10 >= 75
@ -143,7 +143,7 @@ struct mi_builder {
static inline void
mi_builder_init(struct mi_builder *b,
const struct gen_device_info *devinfo,
const struct intel_device_info *devinfo,
__gen_user_data *user_data)
{
memset(b, 0, sizeof(*b));

2
src/intel/common/tests/mi_builder_test.cpp
View file

@ -128,7 +128,7 @@ public:
int fd;
int ctx_id;
gen_device_info devinfo;
intel_device_info devinfo;
uint32_t batch_bo_handle;
#if GFX_VER >= 8

2
src/intel/compiler/brw_clip_line.c
View file

@ -37,7 +37,7 @@
static void brw_clip_line_alloc_regs( struct brw_clip_compile *c )
{
const struct gen_device_info *devinfo = c->func.devinfo;
const struct intel_device_info *devinfo = c->func.devinfo;
GLuint i = 0,j;
/* Register usage is static, precompute here:

2
src/intel/compiler/brw_clip_tri.c
View file

@ -44,7 +44,7 @@ static void release_tmps( struct brw_clip_compile *c )
void brw_clip_tri_alloc_regs( struct brw_clip_compile *c,
GLuint nr_verts )
{
const struct gen_device_info *devinfo = c->func.devinfo;
const struct intel_device_info *devinfo = c->func.devinfo;
GLuint i = 0,j;
/* Register usage is static, precompute here:

4
src/intel/compiler/brw_compiler.c
View file

@ -94,7 +94,7 @@ static const struct nir_shader_compiler_options vector_nir_options = {
};
struct brw_compiler *
brw_compiler_create(void *mem_ctx, const struct gen_device_info *devinfo)
brw_compiler_create(void *mem_ctx, const struct intel_device_info *devinfo)
{
struct brw_compiler *compiler = rzalloc(mem_ctx, struct brw_compiler);
@ -274,7 +274,7 @@ brw_prog_key_size(gl_shader_stage stage)
}
void
brw_write_shader_relocs(const struct gen_device_info *devinfo,
brw_write_shader_relocs(const struct intel_device_info *devinfo,
void *program,
const struct brw_stage_prog_data *prog_data,
struct brw_shader_reloc_value *values,

12
src/intel/compiler/brw_compiler.h
View file

@ -41,7 +41,7 @@ struct brw_program;
typedef struct nir_shader nir_shader;
struct brw_compiler {
const struct gen_device_info *devinfo;
const struct intel_device_info *devinfo;
struct {
struct ra_regs *regs;
@ -1155,7 +1155,7 @@ GLuint brw_varying_to_offset(const struct brw_vue_map *vue_map, GLuint varying)
return brw_vue_slot_to_offset(vue_map->varying_to_slot[varying]);
}
void brw_compute_vue_map(const struct gen_device_info *devinfo,
void brw_compute_vue_map(const struct intel_device_info *devinfo,
struct brw_vue_map *vue_map,
uint64_t slots_valid,
bool separate_shader,
@ -1413,7 +1413,7 @@ struct brw_compile_stats {
/** @} */
struct brw_compiler *
brw_compiler_create(void *mem_ctx, const struct gen_device_info *devinfo);
brw_compiler_create(void *mem_ctx, const struct intel_device_info *devinfo);
/**
* Returns a compiler configuration for use with disk shader cache
@ -1691,12 +1691,12 @@ brw_cs_push_const_total_size(const struct brw_cs_prog_data *cs_prog_data,
unsigned threads);
unsigned
brw_cs_simd_size_for_group_size(const struct gen_device_info *devinfo,
brw_cs_simd_size_for_group_size(const struct intel_device_info *devinfo,
const struct brw_cs_prog_data *cs_prog_data,
unsigned group_size);
void
brw_write_shader_relocs(const struct gen_device_info *devinfo,
brw_write_shader_relocs(const struct intel_device_info *devinfo,
void *program,
const struct brw_stage_prog_data *prog_data,
struct brw_shader_reloc_value *values,
@ -1722,7 +1722,7 @@ brw_cs_right_mask(unsigned group_size, unsigned simd_size)
* '2^n - 1' for some n.
*/
static inline bool
brw_stage_has_packed_dispatch(ASSERTED const struct gen_device_info *devinfo,
brw_stage_has_packed_dispatch(ASSERTED const struct intel_device_info *devinfo,
gl_shader_stage stage,
const struct brw_stage_prog_data *prog_data)
{

52
src/intel/compiler/brw_disasm.c
View file

@ -33,7 +33,7 @@
#include "util/half_float.h"
bool
brw_has_jip(const struct gen_device_info *devinfo, enum opcode opcode)
brw_has_jip(const struct intel_device_info *devinfo, enum opcode opcode)
{
if (devinfo->ver < 6)
return false;
@ -48,7 +48,7 @@ brw_has_jip(const struct gen_device_info *devinfo, enum opcode opcode)
}
bool
brw_has_uip(const struct gen_device_info *devinfo, enum opcode opcode)
brw_has_uip(const struct intel_device_info *devinfo, enum opcode opcode)
{
if (devinfo->ver < 6)
return false;
@ -61,7 +61,7 @@ brw_has_uip(const struct gen_device_info *devinfo, enum opcode opcode)
}
static bool
has_branch_ctrl(const struct gen_device_info *devinfo, enum opcode opcode)
has_branch_ctrl(const struct intel_device_info *devinfo, enum opcode opcode)
{
if (devinfo->ver < 8)
return false;
@ -90,7 +90,7 @@ is_send(unsigned opcode)
}
static bool
is_split_send(UNUSED const struct gen_device_info *devinfo, unsigned opcode)
is_split_send(UNUSED const struct intel_device_info *devinfo, unsigned opcode)
{
if (devinfo->ver >= 12)
return is_send(opcode);
@ -391,7 +391,7 @@ static const char *const dp_rc_msg_type_gfx9[16] = {
};
static const char *const *
dp_rc_msg_type(const struct gen_device_info *devinfo)
dp_rc_msg_type(const struct intel_device_info *devinfo)
{
return (devinfo->ver >= 9 ? dp_rc_msg_type_gfx9 :
devinfo->ver >= 7 ? dp_rc_msg_type_gfx7 :
@ -676,7 +676,7 @@ control(FILE *file, const char *name, const char *const ctrl[],
}
static int
print_opcode(FILE *file, const struct gen_device_info *devinfo,
print_opcode(FILE *file, const struct intel_device_info *devinfo,
enum opcode id)
{
const struct opcode_desc *desc = brw_opcode_desc(devinfo, id);
@ -751,7 +751,7 @@ reg(FILE *file, unsigned _reg_file, unsigned _reg_nr)
}
static int
dest(FILE *file, const struct gen_device_info *devinfo, const brw_inst *inst)
dest(FILE *file, const struct intel_device_info *devinfo, const brw_inst *inst)
{
enum brw_reg_type type = brw_inst_dst_type(devinfo, inst);
unsigned elem_size = brw_reg_type_to_size(type);
@ -831,7 +831,7 @@ dest(FILE *file, const struct gen_device_info *devinfo, const brw_inst *inst)
}
static int
dest_3src(FILE *file, const struct gen_device_info *devinfo, const brw_inst *inst)
dest_3src(FILE *file, const struct intel_device_info *devinfo, const brw_inst *inst)
{
bool is_align1 = brw_inst_3src_access_mode(devinfo, inst) == BRW_ALIGN_1;
int err = 0;
@ -895,7 +895,7 @@ src_align1_region(FILE *file,
static int
src_da1(FILE *file,
const struct gen_device_info *devinfo,
const struct intel_device_info *devinfo,
unsigned opcode,
enum brw_reg_type type, unsigned _reg_file,
unsigned _vert_stride, unsigned _width, unsigned _horiz_stride,
@ -925,7 +925,7 @@ src_da1(FILE *file,
static int
src_ia1(FILE *file,
const struct gen_device_info *devinfo,
const struct intel_device_info *devinfo,
unsigned opcode,
enum brw_reg_type type,
int _addr_imm,
@ -978,7 +978,7 @@ src_swizzle(FILE *file, unsigned swiz)
static int
src_da16(FILE *file,
const struct gen_device_info *devinfo,
const struct intel_device_info *devinfo,
unsigned opcode,
enum brw_reg_type type,
unsigned _reg_file,
@ -1017,7 +1017,7 @@ src_da16(FILE *file,
}
static enum brw_vertical_stride
vstride_from_align1_3src_vstride(const struct gen_device_info *devinfo,
vstride_from_align1_3src_vstride(const struct intel_device_info *devinfo,
enum gfx10_align1_3src_vertical_stride vstride)
{
switch (vstride) {
@ -1102,7 +1102,7 @@ implied_width(enum brw_vertical_stride _vert_stride,
}
static int
src0_3src(FILE *file, const struct gen_device_info *devinfo, const brw_inst *inst)
src0_3src(FILE *file, const struct intel_device_info *devinfo, const brw_inst *inst)
{
int err = 0;
unsigned reg_nr, subreg_nr;
@ -1188,7 +1188,7 @@ src0_3src(FILE *file, const struct gen_device_info *devinfo, const brw_inst *ins
}
static int
src1_3src(FILE *file, const struct gen_device_info *devinfo, const brw_inst *inst)
src1_3src(FILE *file, const struct intel_device_info *devinfo, const brw_inst *inst)
{
int err = 0;
unsigned reg_nr, subreg_nr;
@ -1261,7 +1261,7 @@ src1_3src(FILE *file, const struct gen_device_info *devinfo, const brw_inst *ins
}
static int
src2_3src(FILE *file, const struct gen_device_info *devinfo, const brw_inst *inst)
src2_3src(FILE *file, const struct intel_device_info *devinfo, const brw_inst *inst)
{
int err = 0;
unsigned reg_nr, subreg_nr;
@ -1348,7 +1348,7 @@ src2_3src(FILE *file, const struct gen_device_info *devinfo, const brw_inst *ins
}
static int
imm(FILE *file, const struct gen_device_info *devinfo, enum brw_reg_type type,
imm(FILE *file, const struct intel_device_info *devinfo, enum brw_reg_type type,
const brw_inst *inst)
{
switch (type) {
@ -1417,7 +1417,7 @@ imm(FILE *file, const struct gen_device_info *devinfo, enum brw_reg_type type,
static int
src_sends_da(FILE *file,
const struct gen_device_info *devinfo,
const struct intel_device_info *devinfo,
enum brw_reg_type type,
enum brw_reg_file _reg_file,
unsigned _reg_nr,
@ -1437,7 +1437,7 @@ src_sends_da(FILE *file,
static int
src_sends_ia(FILE *file,
const struct gen_device_info *devinfo,
const struct intel_device_info *devinfo,
enum brw_reg_type type,
int _addr_imm,
unsigned _addr_subreg_nr)
@ -1455,7 +1455,7 @@ src_sends_ia(FILE *file,
static int
src_send_desc_ia(FILE *file,
const struct gen_device_info *devinfo,
const struct intel_device_info *devinfo,
unsigned _addr_subreg_nr)
{
string(file, "a0");
@ -1467,7 +1467,7 @@ src_send_desc_ia(FILE *file,
}
static int
src0(FILE *file, const struct gen_device_info *devinfo, const brw_inst *inst)
src0(FILE *file, const struct intel_device_info *devinfo, const brw_inst *inst)
{
if (is_split_send(devinfo, brw_inst_opcode(devinfo, inst))) {
if (devinfo->ver >= 12) {
@ -1544,7 +1544,7 @@ src0(FILE *file, const struct gen_device_info *devinfo, const brw_inst *inst)
}
static int
src1(FILE *file, const struct gen_device_info *devinfo, const brw_inst *inst)
src1(FILE *file, const struct intel_device_info *devinfo, const brw_inst *inst)
{
if (is_split_send(devinfo, brw_inst_opcode(devinfo, inst))) {
return src_sends_da(file,
@ -1606,7 +1606,7 @@ src1(FILE *file, const struct gen_device_info *devinfo, const brw_inst *inst)
}
static int
qtr_ctrl(FILE *file, const struct gen_device_info *devinfo, const brw_inst *inst)
qtr_ctrl(FILE *file, const struct intel_device_info *devinfo, const brw_inst *inst)
{
int qtr_ctl = brw_inst_qtr_control(devinfo, inst);
int exec_size = 1 << brw_inst_exec_size(devinfo, inst);
@ -1640,7 +1640,7 @@ qtr_ctrl(FILE *file, const struct gen_device_info *devinfo, const brw_inst *inst
}
static int
swsb(FILE *file, const struct gen_device_info *devinfo, const brw_inst *inst)
swsb(FILE *file, const struct intel_device_info *devinfo, const brw_inst *inst)
{
const enum opcode opcode = brw_inst_opcode(devinfo, inst);
const uint8_t x = brw_inst_swsb(devinfo, inst);
@ -1661,7 +1661,7 @@ swsb(FILE *file, const struct gen_device_info *devinfo, const brw_inst *inst)
#ifdef DEBUG
static __attribute__((__unused__)) int
brw_disassemble_imm(const struct gen_device_info *devinfo,
brw_disassemble_imm(const struct intel_device_info *devinfo,
uint32_t dw3, uint32_t dw2, uint32_t dw1, uint32_t dw0)
{
brw_inst inst;
@ -1672,7 +1672,7 @@ brw_disassemble_imm(const struct gen_device_info *devinfo,
#endif
static void
write_label(FILE *file, const struct gen_device_info *devinfo,
write_label(FILE *file, const struct intel_device_info *devinfo,
const struct brw_label *root_label,
int offset, int jump)
{
@ -1687,7 +1687,7 @@ write_label(FILE *file, const struct gen_device_info *devinfo,
}
int
brw_disassemble_inst(FILE *file, const struct gen_device_info *devinfo,
brw_disassemble_inst(FILE *file, const struct intel_device_info *devinfo,
const brw_inst *inst, bool is_compacted,
int offset, const struct brw_label *root_label)
{

6
src/intel/compiler/brw_disasm_info.c
View file

@ -34,7 +34,7 @@ void
dump_assembly(void *assembly, int start_offset, int end_offset,
struct disasm_info *disasm, const unsigned *block_latency)
{
const struct gen_device_info *devinfo = disasm->devinfo;
const struct intel_device_info *devinfo = disasm->devinfo;
const char *last_annotation_string = NULL;
const void *last_annotation_ir = NULL;
@ -104,7 +104,7 @@ dump_assembly(void *assembly, int start_offset, int end_offset,
}
struct disasm_info *
disasm_initialize(const struct gen_device_info *devinfo,
disasm_initialize(const struct intel_device_info *devinfo,
const struct cfg_t *cfg)
{
struct disasm_info *disasm = ralloc(NULL, struct disasm_info);
@ -129,7 +129,7 @@ void
disasm_annotate(struct disasm_info *disasm,
struct backend_instruction *inst, unsigned offset)
{
const struct gen_device_info *devinfo = disasm->devinfo;
const struct intel_device_info *devinfo = disasm->devinfo;
const struct cfg_t *cfg = disasm->cfg;
struct inst_group *group;

6
src/intel/compiler/brw_disasm_info.h
View file

@ -32,7 +32,7 @@ extern "C" {
struct cfg_t;
struct backend_instruction;
struct gen_device_info;
struct intel_device_info;
struct inst_group {
struct exec_node link;
@ -56,7 +56,7 @@ struct inst_group {
struct disasm_info {
struct exec_list group_list;
const struct gen_device_info *devinfo;
const struct intel_device_info *devinfo;
const struct cfg_t *cfg;
/** Block index in the cfg. */
@ -69,7 +69,7 @@ dump_assembly(void *assembly, int start_offset, int end_offset,
struct disasm_info *disasm, const unsigned *block_latency);
struct disasm_info *
disasm_initialize(const struct gen_device_info *devinfo,
disasm_initialize(const struct intel_device_info *devinfo,
const struct cfg_t *cfg);
struct inst_group *

18
src/intel/compiler/brw_eu.cpp
View file

@ -216,7 +216,7 @@ brw_set_default_compression_control(struct brw_codegen *p,
* the currently selected channel enable group untouched.
*/
void
brw_inst_set_compression(const struct gen_device_info *devinfo,
brw_inst_set_compression(const struct intel_device_info *devinfo,
brw_inst *inst, bool on)
{
if (devinfo->ver >= 6) {
@ -248,7 +248,7 @@ brw_set_default_compression(struct brw_codegen *p, bool on)
* [group, group + exec_size) to the instruction passed as argument.
*/
void
brw_inst_set_group(const struct gen_device_info *devinfo,
brw_inst_set_group(const struct intel_device_info *devinfo,
brw_inst *inst, unsigned group)
{
if (devinfo->ver >= 7) {
@ -317,7 +317,7 @@ void brw_pop_insn_state( struct brw_codegen *p )
/***********************************************************************
*/
void
brw_init_codegen(const struct gen_device_info *devinfo,
brw_init_codegen(const struct intel_device_info *devinfo,
struct brw_codegen *p, void *mem_ctx)
{
memset(p, 0, sizeof(*p));
@ -465,7 +465,7 @@ brw_create_label(struct brw_label **labels, int offset, void *mem_ctx)
}
const struct brw_label *
brw_label_assembly(const struct gen_device_info *devinfo,
brw_label_assembly(const struct intel_device_info *devinfo,
const void *assembly, int start, int end, void *mem_ctx)
{
struct brw_label *root_label = NULL;
@ -512,7 +512,7 @@ brw_label_assembly(const struct gen_device_info *devinfo,
}
void
brw_disassemble_with_labels(const struct gen_device_info *devinfo,
brw_disassemble_with_labels(const struct intel_device_info *devinfo,
const void *assembly, int start, int end, FILE *out)
{
void *mem_ctx = ralloc_context(NULL);
@ -525,7 +525,7 @@ brw_disassemble_with_labels(const struct gen_device_info *devinfo,
}
void
brw_disassemble(const struct gen_device_info *devinfo,
brw_disassemble(const struct intel_device_info *devinfo,
const void *assembly, int start, int end,
const struct brw_label *root_label, FILE *out)
{
@ -711,7 +711,7 @@ lookup_opcode_desc(gen *index_gen,
const opcode_desc **index_descs,
unsigned index_size,
unsigned opcode_desc::*key,
const gen_device_info *devinfo,
const intel_device_info *devinfo,
unsigned k)
{
if (*index_gen != gen_from_devinfo(devinfo)) {
@ -740,7 +740,7 @@ lookup_opcode_desc(gen *index_gen,
* generation, or NULL if the opcode is not supported by the device.
*/
const struct opcode_desc *
brw_opcode_desc(const struct gen_device_info *devinfo, enum opcode opcode)
brw_opcode_desc(const struct intel_device_info *devinfo, enum opcode opcode)
{
static __thread gen index_gen = {};
static __thread const opcode_desc *index_descs[NUM_BRW_OPCODES];
@ -753,7 +753,7 @@ brw_opcode_desc(const struct gen_device_info *devinfo, enum opcode opcode)
* generation, or NULL if the opcode is not supported by the device.
*/
const struct opcode_desc *
brw_opcode_desc_from_hw(const struct gen_device_info *devinfo, unsigned hw)
brw_opcode_desc_from_hw(const struct intel_device_info *devinfo, unsigned hw)
{
static __thread gen index_gen = {};
static __thread const opcode_desc *index_descs[128];

142
src/intel/compiler/brw_eu.h
View file

@ -110,7 +110,7 @@ struct brw_codegen {
bool automatic_exec_sizes;
bool single_program_flow;
const struct gen_device_info *devinfo;
const struct intel_device_info *devinfo;
/* Control flow stacks:
* - if_stack contains IF and ELSE instructions which must be patched
@ -158,10 +158,10 @@ void brw_set_default_exec_size(struct brw_codegen *p, unsigned value);
void brw_set_default_mask_control( struct brw_codegen *p, unsigned value );
void brw_set_default_saturate( struct brw_codegen *p, bool enable );
void brw_set_default_access_mode( struct brw_codegen *p, unsigned access_mode );
void brw_inst_set_compression(const struct gen_device_info *devinfo,
void brw_inst_set_compression(const struct intel_device_info *devinfo,
brw_inst *inst, bool on);
void brw_set_default_compression(struct brw_codegen *p, bool on);
void brw_inst_set_group(const struct gen_device_info *devinfo,
void brw_inst_set_group(const struct intel_device_info *devinfo,
brw_inst *inst, unsigned group);
void brw_set_default_group(struct brw_codegen *p, unsigned group);
void brw_set_default_compression_control(struct brw_codegen *p, enum brw_compression c);
@ -171,21 +171,21 @@ void brw_set_default_flag_reg(struct brw_codegen *p, int reg, int subreg);
void brw_set_default_acc_write_control(struct brw_codegen *p, unsigned value);
void brw_set_default_swsb(struct brw_codegen *p, struct tgl_swsb value);
void brw_init_codegen(const struct gen_device_info *, struct brw_codegen *p,
void brw_init_codegen(const struct intel_device_info *, struct brw_codegen *p,
void *mem_ctx);
bool brw_has_jip(const struct gen_device_info *devinfo, enum opcode opcode);
bool brw_has_uip(const struct gen_device_info *devinfo, enum opcode opcode);
bool brw_has_jip(const struct intel_device_info *devinfo, enum opcode opcode);
bool brw_has_uip(const struct intel_device_info *devinfo, enum opcode opcode);
const struct brw_label *brw_find_label(const struct brw_label *root, int offset);
void brw_create_label(struct brw_label **labels, int offset, void *mem_ctx);
int brw_disassemble_inst(FILE *file, const struct gen_device_info *devinfo,
int brw_disassemble_inst(FILE *file, const struct intel_device_info *devinfo,
const struct brw_inst *inst, bool is_compacted,
int offset, const struct brw_label *root_label);
const struct brw_label *brw_label_assembly(const struct gen_device_info *devinfo,
const struct brw_label *brw_label_assembly(const struct intel_device_info *devinfo,
const void *assembly, int start, int end,
void *mem_ctx);
void brw_disassemble_with_labels(const struct gen_device_info *devinfo,
void brw_disassemble_with_labels(const struct intel_device_info *devinfo,
const void *assembly, int start, int end, FILE *out);
void brw_disassemble(const struct gen_device_info *devinfo,
void brw_disassemble(const struct intel_device_info *devinfo,
const void *assembly, int start, int end,
const struct brw_label *root_label, FILE *out);
const struct brw_shader_reloc *brw_get_shader_relocs(struct brw_codegen *p,
@ -283,7 +283,7 @@ ALU2(SUBB)
* descriptor controls.
*/
static inline uint32_t
brw_message_desc(const struct gen_device_info *devinfo,
brw_message_desc(const struct intel_device_info *devinfo,
unsigned msg_length,
unsigned response_length,
bool header_present)
@ -299,7 +299,7 @@ brw_message_desc(const struct gen_device_info *devinfo,
}
static inline unsigned
brw_message_desc_mlen(const struct gen_device_info *devinfo, uint32_t desc)
brw_message_desc_mlen(const struct intel_device_info *devinfo, uint32_t desc)
{
if (devinfo->ver >= 5)
return GET_BITS(desc, 28, 25);
@ -308,7 +308,7 @@ brw_message_desc_mlen(const struct gen_device_info *devinfo, uint32_t desc)
}
static inline unsigned
brw_message_desc_rlen(const struct gen_device_info *devinfo, uint32_t desc)
brw_message_desc_rlen(const struct intel_device_info *devinfo, uint32_t desc)
{
if (devinfo->ver >= 5)
return GET_BITS(desc, 24, 20);
@ -317,7 +317,7 @@ brw_message_desc_rlen(const struct gen_device_info *devinfo, uint32_t desc)
}
static inline bool
brw_message_desc_header_present(ASSERTED const struct gen_device_info *devinfo,
brw_message_desc_header_present(ASSERTED const struct intel_device_info *devinfo,
uint32_t desc)
{
assert(devinfo->ver >= 5);
@ -325,21 +325,21 @@ brw_message_desc_header_present(ASSERTED const struct gen_device_info *devinfo,
}
static inline unsigned
brw_message_ex_desc(UNUSED const struct gen_device_info *devinfo,
brw_message_ex_desc(UNUSED const struct intel_device_info *devinfo,
unsigned ex_msg_length)
{
return SET_BITS(ex_msg_length, 9, 6);
}
static inline unsigned
brw_message_ex_desc_ex_mlen(UNUSED const struct gen_device_info *devinfo,
brw_message_ex_desc_ex_mlen(UNUSED const struct intel_device_info *devinfo,
uint32_t ex_desc)
{
return GET_BITS(ex_desc, 9, 6);
}
static inline uint32_t
brw_urb_desc(const struct gen_device_info *devinfo,
brw_urb_desc(const struct intel_device_info *devinfo,
unsigned msg_type,
bool per_slot_offset_present,
bool channel_mask_present,
@ -361,7 +361,7 @@ brw_urb_desc(const struct gen_device_info *devinfo,
}
static inline uint32_t
brw_urb_desc_msg_type(ASSERTED const struct gen_device_info *devinfo,
brw_urb_desc_msg_type(ASSERTED const struct intel_device_info *devinfo,
uint32_t desc)
{
assert(devinfo->ver >= 7);
@ -373,7 +373,7 @@ brw_urb_desc_msg_type(ASSERTED const struct gen_device_info *devinfo,
* function controls.
*/
static inline uint32_t
brw_sampler_desc(const struct gen_device_info *devinfo,
brw_sampler_desc(const struct intel_device_info *devinfo,
unsigned binding_table_index,
unsigned sampler,
unsigned msg_type,
@ -396,20 +396,20 @@ brw_sampler_desc(const struct gen_device_info *devinfo,
}
static inline unsigned
brw_sampler_desc_binding_table_index(UNUSED const struct gen_device_info *devinfo,
brw_sampler_desc_binding_table_index(UNUSED const struct intel_device_info *devinfo,
uint32_t desc)
{
return GET_BITS(desc, 7, 0);
}
static inline unsigned
brw_sampler_desc_sampler(UNUSED const struct gen_device_info *devinfo, uint32_t desc)
brw_sampler_desc_sampler(UNUSED const struct intel_device_info *devinfo, uint32_t desc)
{
return GET_BITS(desc, 11, 8);
}
static inline unsigned
brw_sampler_desc_msg_type(const struct gen_device_info *devinfo, uint32_t desc)
brw_sampler_desc_msg_type(const struct intel_device_info *devinfo, uint32_t desc)
{
if (devinfo->ver >= 7)
return GET_BITS(desc, 16, 12);
@ -420,7 +420,7 @@ brw_sampler_desc_msg_type(const struct gen_device_info *devinfo, uint32_t desc)
}
static inline unsigned
brw_sampler_desc_simd_mode(const struct gen_device_info *devinfo, uint32_t desc)
brw_sampler_desc_simd_mode(const struct intel_device_info *devinfo, uint32_t desc)
{
assert(devinfo->ver >= 5);
if (devinfo->ver >= 7)
@ -430,7 +430,7 @@ brw_sampler_desc_simd_mode(const struct gen_device_info *devinfo, uint32_t desc)
}
static inline unsigned
brw_sampler_desc_return_format(ASSERTED const struct gen_device_info *devinfo,
brw_sampler_desc_return_format(ASSERTED const struct intel_device_info *devinfo,
uint32_t desc)
{
assert(devinfo->ver == 4 && !devinfo->is_g4x);
@ -441,7 +441,7 @@ brw_sampler_desc_return_format(ASSERTED const struct gen_device_info *devinfo,
* Construct a message descriptor for the dataport
*/
static inline uint32_t
brw_dp_desc(const struct gen_device_info *devinfo,
brw_dp_desc(const struct intel_device_info *devinfo,
unsigned binding_table_index,
unsigned msg_type,
unsigned msg_control)
@ -464,14 +464,14 @@ brw_dp_desc(const struct gen_device_info *devinfo,
}
static inline unsigned
brw_dp_desc_binding_table_index(UNUSED const struct gen_device_info *devinfo,
brw_dp_desc_binding_table_index(UNUSED const struct intel_device_info *devinfo,
uint32_t desc)
{
return GET_BITS(desc, 7, 0);
}
static inline unsigned
brw_dp_desc_msg_type(const struct gen_device_info *devinfo, uint32_t desc)
brw_dp_desc_msg_type(const struct intel_device_info *devinfo, uint32_t desc)
{
assert(devinfo->ver >= 6);
if (devinfo->ver >= 8)
@ -483,7 +483,7 @@ brw_dp_desc_msg_type(const struct gen_device_info *devinfo, uint32_t desc)
}
static inline unsigned
brw_dp_desc_msg_control(const struct gen_device_info *devinfo, uint32_t desc)
brw_dp_desc_msg_control(const struct intel_device_info *devinfo, uint32_t desc)
{
assert(devinfo->ver >= 6);
if (devinfo->ver >= 7)
@ -497,7 +497,7 @@ brw_dp_desc_msg_control(const struct gen_device_info *devinfo, uint32_t desc)
* function controls.
*/
static inline uint32_t
brw_dp_read_desc(const struct gen_device_info *devinfo,
brw_dp_read_desc(const struct intel_device_info *devinfo,
unsigned binding_table_index,
unsigned msg_control,
unsigned msg_type,
@ -518,7 +518,7 @@ brw_dp_read_desc(const struct gen_device_info *devinfo,
}
static inline unsigned
brw_dp_read_desc_msg_type(const struct gen_device_info *devinfo, uint32_t desc)
brw_dp_read_desc_msg_type(const struct intel_device_info *devinfo, uint32_t desc)
{
if (devinfo->ver >= 6)
return brw_dp_desc_msg_type(devinfo, desc);
@ -529,7 +529,7 @@ brw_dp_read_desc_msg_type(const struct gen_device_info *devinfo, uint32_t desc)
}
static inline unsigned
brw_dp_read_desc_msg_control(const struct gen_device_info *devinfo,
brw_dp_read_desc_msg_control(const struct intel_device_info *devinfo,
uint32_t desc)
{
if (devinfo->ver >= 6)
@ -545,7 +545,7 @@ brw_dp_read_desc_msg_control(const struct gen_device_info *devinfo,
* function controls.
*/
static inline uint32_t
brw_dp_write_desc(const struct gen_device_info *devinfo,
brw_dp_write_desc(const struct intel_device_info *devinfo,
unsigned binding_table_index,
unsigned msg_control,
unsigned msg_type,
@ -566,7 +566,7 @@ brw_dp_write_desc(const struct gen_device_info *devinfo,
}
static inline unsigned
brw_dp_write_desc_msg_type(const struct gen_device_info *devinfo,
brw_dp_write_desc_msg_type(const struct intel_device_info *devinfo,
uint32_t desc)
{
if (devinfo->ver >= 6)
@ -576,7 +576,7 @@ brw_dp_write_desc_msg_type(const struct gen_device_info *devinfo,
}
static inline unsigned
brw_dp_write_desc_msg_control(const struct gen_device_info *devinfo,
brw_dp_write_desc_msg_control(const struct intel_device_info *devinfo,
uint32_t desc)
{
if (devinfo->ver >= 6)
@ -586,7 +586,7 @@ brw_dp_write_desc_msg_control(const struct gen_device_info *devinfo,
}
static inline bool
brw_dp_write_desc_last_render_target(const struct gen_device_info *devinfo,
brw_dp_write_desc_last_render_target(const struct intel_device_info *devinfo,
uint32_t desc)
{
if (devinfo->ver >= 6)
@ -596,7 +596,7 @@ brw_dp_write_desc_last_render_target(const struct gen_device_info *devinfo,
}
static inline bool
brw_dp_write_desc_write_commit(const struct gen_device_info *devinfo,
brw_dp_write_desc_write_commit(const struct intel_device_info *devinfo,
uint32_t desc)
{
assert(devinfo->ver <= 6);
@ -611,7 +611,7 @@ brw_dp_write_desc_write_commit(const struct gen_device_info *devinfo,
* surface function controls.
*/
static inline uint32_t
brw_dp_surface_desc(const struct gen_device_info *devinfo,
brw_dp_surface_desc(const struct intel_device_info *devinfo,
unsigned msg_type,
unsigned msg_control)
{
@ -621,7 +621,7 @@ brw_dp_surface_desc(const struct gen_device_info *devinfo,
}
static inline uint32_t
brw_dp_untyped_atomic_desc(const struct gen_device_info *devinfo,
brw_dp_untyped_atomic_desc(const struct intel_device_info *devinfo,
unsigned exec_size, /**< 0 for SIMD4x2 */
unsigned atomic_op,
bool response_expected)
@ -648,7 +648,7 @@ brw_dp_untyped_atomic_desc(const struct gen_device_info *devinfo,
}
static inline uint32_t
brw_dp_untyped_atomic_float_desc(const struct gen_device_info *devinfo,
brw_dp_untyped_atomic_float_desc(const struct intel_device_info *devinfo,
unsigned exec_size,
unsigned atomic_op,
bool response_expected)
@ -675,7 +675,7 @@ brw_mdc_cmask(unsigned num_channels)
}
static inline uint32_t
brw_dp_untyped_surface_rw_desc(const struct gen_device_info *devinfo,
brw_dp_untyped_surface_rw_desc(const struct intel_device_info *devinfo,
unsigned exec_size, /**< 0 for SIMD4x2 */
unsigned num_channels,
bool write)
@ -729,7 +729,7 @@ brw_mdc_ds(unsigned bit_size)
}
static inline uint32_t
brw_dp_byte_scattered_rw_desc(const struct gen_device_info *devinfo,
brw_dp_byte_scattered_rw_desc(const struct intel_device_info *devinfo,
unsigned exec_size,
unsigned bit_size,
bool write)
@ -750,7 +750,7 @@ brw_dp_byte_scattered_rw_desc(const struct gen_device_info *devinfo,
}
static inline uint32_t
brw_dp_dword_scattered_rw_desc(const struct gen_device_info *devinfo,
brw_dp_dword_scattered_rw_desc(const struct intel_device_info *devinfo,
unsigned exec_size,
bool write)
{
@ -781,7 +781,7 @@ brw_dp_dword_scattered_rw_desc(const struct gen_device_info *devinfo,
}
static inline uint32_t
brw_dp_oword_block_rw_desc(const struct gen_device_info *devinfo,
brw_dp_oword_block_rw_desc(const struct intel_device_info *devinfo,
bool align_16B,
unsigned num_dwords,
bool write)
@ -801,7 +801,7 @@ brw_dp_oword_block_rw_desc(const struct gen_device_info *devinfo,
}
static inline uint32_t
brw_dp_a64_untyped_surface_rw_desc(const struct gen_device_info *devinfo,
brw_dp_a64_untyped_surface_rw_desc(const struct intel_device_info *devinfo,
unsigned exec_size, /**< 0 for SIMD4x2 */
unsigned num_channels,
bool write)
@ -826,7 +826,7 @@ brw_dp_a64_untyped_surface_rw_desc(const struct gen_device_info *devinfo,
}
static inline uint32_t
brw_dp_a64_oword_block_rw_desc(const struct gen_device_info *devinfo,
brw_dp_a64_oword_block_rw_desc(const struct intel_device_info *devinfo,
bool align_16B,
unsigned num_dwords,
bool write)
@ -864,7 +864,7 @@ brw_mdc_a64_ds(unsigned elems)
}
static inline uint32_t
brw_dp_a64_byte_scattered_rw_desc(const struct gen_device_info *devinfo,
brw_dp_a64_byte_scattered_rw_desc(const struct intel_device_info *devinfo,
unsigned exec_size, /**< 0 for SIMD4x2 */
unsigned bit_size,
bool write)
@ -886,7 +886,7 @@ brw_dp_a64_byte_scattered_rw_desc(const struct gen_device_info *devinfo,
}
static inline uint32_t
brw_dp_a64_untyped_atomic_desc(const struct gen_device_info *devinfo,
brw_dp_a64_untyped_atomic_desc(const struct intel_device_info *devinfo,
ASSERTED unsigned exec_size, /**< 0 for SIMD4x2 */
unsigned bit_size,
unsigned atomic_op,
@ -911,7 +911,7 @@ brw_dp_a64_untyped_atomic_desc(const struct gen_device_info *devinfo,
}
static inline uint32_t
brw_dp_a64_untyped_atomic_float_desc(const struct gen_device_info *devinfo,
brw_dp_a64_untyped_atomic_float_desc(const struct intel_device_info *devinfo,
ASSERTED unsigned exec_size,
unsigned bit_size,
unsigned atomic_op,
@ -936,7 +936,7 @@ brw_dp_a64_untyped_atomic_float_desc(const struct gen_device_info *devinfo,
}
static inline uint32_t
brw_dp_typed_atomic_desc(const struct gen_device_info *devinfo,
brw_dp_typed_atomic_desc(const struct intel_device_info *devinfo,
unsigned exec_size,
unsigned exec_group,
unsigned atomic_op,
@ -969,7 +969,7 @@ brw_dp_typed_atomic_desc(const struct gen_device_info *devinfo,
}
static inline uint32_t
brw_dp_typed_surface_rw_desc(const struct gen_device_info *devinfo,
brw_dp_typed_surface_rw_desc(const struct intel_device_info *devinfo,
unsigned exec_size,
unsigned exec_group,
unsigned num_channels,
@ -1034,7 +1034,7 @@ brw_mdc_sm2_exec_size(uint32_t sm2)
}
static inline uint32_t
brw_btd_spawn_desc(ASSERTED const struct gen_device_info *devinfo,
brw_btd_spawn_desc(ASSERTED const struct intel_device_info *devinfo,
unsigned exec_size, unsigned msg_type)
{
assert(devinfo->has_ray_tracing);
@ -1045,21 +1045,21 @@ brw_btd_spawn_desc(ASSERTED const struct gen_device_info *devinfo,
}
static inline uint32_t
brw_btd_spawn_msg_type(UNUSED const struct gen_device_info *devinfo,
brw_btd_spawn_msg_type(UNUSED const struct intel_device_info *devinfo,
uint32_t desc)
{
return GET_BITS(desc, 17, 14);
}
static inline uint32_t
brw_btd_spawn_exec_size(UNUSED const struct gen_device_info *devinfo,
brw_btd_spawn_exec_size(UNUSED const struct intel_device_info *devinfo,
uint32_t desc)
{
return brw_mdc_sm2_exec_size(GET_BITS(desc, 8, 8));
}
static inline uint32_t
brw_rt_trace_ray_desc(ASSERTED const struct gen_device_info *devinfo,
brw_rt_trace_ray_desc(ASSERTED const struct intel_device_info *devinfo,
unsigned exec_size)
{
assert(devinfo->has_ray_tracing);
@ -1070,7 +1070,7 @@ brw_rt_trace_ray_desc(ASSERTED const struct gen_device_info *devinfo,
}
static inline uint32_t
brw_rt_trace_ray_desc_exec_size(UNUSED const struct gen_device_info *devinfo,
brw_rt_trace_ray_desc_exec_size(UNUSED const struct intel_device_info *devinfo,
uint32_t desc)
{
return brw_mdc_sm2_exec_size(GET_BITS(desc, 8, 8));
@ -1081,7 +1081,7 @@ brw_rt_trace_ray_desc_exec_size(UNUSED const struct gen_device_info *devinfo,
* interpolator function controls.
*/
static inline uint32_t
brw_pixel_interp_desc(UNUSED const struct gen_device_info *devinfo,
brw_pixel_interp_desc(UNUSED const struct intel_device_info *devinfo,
unsigned msg_type,
bool noperspective,
unsigned simd_mode,
@ -1229,7 +1229,7 @@ void brw_shader_time_add(struct brw_codegen *p,
* instruction.
*/
static inline unsigned
brw_jump_scale(const struct gen_device_info *devinfo)
brw_jump_scale(const struct intel_device_info *devinfo)
{
/* Broadwell measures jump targets in bytes. */
if (devinfo->ver >= 8)
@ -1356,7 +1356,7 @@ brw_float_controls_mode(struct brw_codegen *p,
unsigned mode, unsigned mask);
void
brw_update_reloc_imm(const struct gen_device_info *devinfo,
brw_update_reloc_imm(const struct intel_device_info *devinfo,
brw_inst *inst,
uint32_t value);
@ -1413,24 +1413,24 @@ enum brw_conditional_mod brw_swap_cmod(enum brw_conditional_mod cmod);
/* brw_eu_compact.c */
void brw_compact_instructions(struct brw_codegen *p, int start_offset,
struct disasm_info *disasm);
void brw_uncompact_instruction(const struct gen_device_info *devinfo,
void brw_uncompact_instruction(const struct intel_device_info *devinfo,
brw_inst *dst, brw_compact_inst *src);
bool brw_try_compact_instruction(const struct gen_device_info *devinfo,
bool brw_try_compact_instruction(const struct intel_device_info *devinfo,
brw_compact_inst *dst, const brw_inst *src);
void brw_debug_compact_uncompact(const struct gen_device_info *devinfo,
void brw_debug_compact_uncompact(const struct intel_device_info *devinfo,
brw_inst *orig, brw_inst *uncompacted);
/* brw_eu_validate.c */
bool brw_validate_instruction(const struct gen_device_info *devinfo,
bool brw_validate_instruction(const struct intel_device_info *devinfo,
const brw_inst *inst, int offset,
struct disasm_info *disasm);
bool brw_validate_instructions(const struct gen_device_info *devinfo,
bool brw_validate_instructions(const struct intel_device_info *devinfo,
const void *assembly, int start_offset, int end_offset,
struct disasm_info *disasm);
static inline int
next_offset(const struct gen_device_info *devinfo, void *store, int offset)
next_offset(const struct intel_device_info *devinfo, void *store, int offset)
{
brw_inst *insn = (brw_inst *)((char *)store + offset);
@ -1450,39 +1450,39 @@ struct opcode_desc {
};
const struct opcode_desc *
brw_opcode_desc(const struct gen_device_info *devinfo, enum opcode opcode);
brw_opcode_desc(const struct intel_device_info *devinfo, enum opcode opcode);
const struct opcode_desc *
brw_opcode_desc_from_hw(const struct gen_device_info *devinfo, unsigned hw);
brw_opcode_desc_from_hw(const struct intel_device_info *devinfo, unsigned hw);
static inline unsigned
brw_opcode_encode(const struct gen_device_info *devinfo, enum opcode opcode)
brw_opcode_encode(const struct intel_device_info *devinfo, enum opcode opcode)
{
return brw_opcode_desc(devinfo, opcode)->hw;
}
static inline enum opcode
brw_opcode_decode(const struct gen_device_info *devinfo, unsigned hw)
brw_opcode_decode(const struct intel_device_info *devinfo, unsigned hw)
{
const struct opcode_desc *desc = brw_opcode_desc_from_hw(devinfo, hw);
return desc ? (enum opcode)desc->ir : BRW_OPCODE_ILLEGAL;
}
static inline void
brw_inst_set_opcode(const struct gen_device_info *devinfo,
brw_inst_set_opcode(const struct intel_device_info *devinfo,
brw_inst *inst, enum opcode opcode)
{
brw_inst_set_hw_opcode(devinfo, inst, brw_opcode_encode(devinfo, opcode));
}
static inline enum opcode
brw_inst_opcode(const struct gen_device_info *devinfo, const brw_inst *inst)
brw_inst_opcode(const struct intel_device_info *devinfo, const brw_inst *inst)
{
return brw_opcode_decode(devinfo, brw_inst_hw_opcode(devinfo, inst));
}
static inline bool
is_3src(const struct gen_device_info *devinfo, enum opcode opcode)
is_3src(const struct intel_device_info *devinfo, enum opcode opcode)
{
const struct opcode_desc *desc = brw_opcode_desc(devinfo, opcode);
return desc && desc->nsrc == 3;

70
src/intel/compiler/brw_eu_compact.c
View file

@ -1065,7 +1065,7 @@ static const uint32_t gfx12_3src_subreg_table[32] = {
};
struct compaction_state {
const struct gen_device_info *devinfo;
const struct intel_device_info *devinfo;
const uint32_t *control_index_table;
const uint32_t *datatype_table;
const uint16_t *subreg_table;
@ -1074,13 +1074,13 @@ struct compaction_state {
};
static void compaction_state_init(struct compaction_state *c,
const struct gen_device_info *devinfo);
const struct intel_device_info *devinfo);
static bool
set_control_index(const struct compaction_state *c,
brw_compact_inst *dst, const brw_inst *src)
{
const struct gen_device_info *devinfo = c->devinfo;
const struct intel_device_info *devinfo = c->devinfo;
uint32_t uncompacted; /* 17b/G45; 19b/IVB+; 21b/TGL+ */
if (devinfo->ver >= 12) {
@ -1125,7 +1125,7 @@ static bool
set_datatype_index(const struct compaction_state *c, brw_compact_inst *dst,
const brw_inst *src, bool is_immediate)
{
const struct gen_device_info *devinfo = c->devinfo;
const struct intel_device_info *devinfo = c->devinfo;
uint32_t uncompacted; /* 18b/G45+; 21b/BDW+; 20b/TGL+ */
if (devinfo->ver >= 12) {
@ -1168,7 +1168,7 @@ static bool
set_subreg_index(const struct compaction_state *c, brw_compact_inst *dst,
const brw_inst *src, bool is_immediate)
{
const struct gen_device_info *devinfo = c->devinfo;
const struct intel_device_info *devinfo = c->devinfo;
uint16_t uncompacted; /* 15b */
if (devinfo->ver >= 12) {
@ -1199,7 +1199,7 @@ static bool
set_src0_index(const struct compaction_state *c, brw_compact_inst *dst,
const brw_inst *src)
{
const struct gen_device_info *devinfo = c->devinfo;
const struct intel_device_info *devinfo = c->devinfo;
uint16_t uncompacted; /* 12b */
int table_len;
@ -1229,7 +1229,7 @@ static bool
set_src1_index(const struct compaction_state *c, brw_compact_inst *dst,
const brw_inst *src, bool is_immediate, unsigned imm)
{
const struct gen_device_info *devinfo = c->devinfo;
const struct intel_device_info *devinfo = c->devinfo;
if (is_immediate) {
if (devinfo->ver >= 12) {
/* src1 index takes the low 4 bits of the 12-bit compacted value */
@ -1267,7 +1267,7 @@ set_src1_index(const struct compaction_state *c, brw_compact_inst *dst,
}
static bool
set_3src_control_index(const struct gen_device_info *devinfo,
set_3src_control_index(const struct intel_device_info *devinfo,
brw_compact_inst *dst, const brw_inst *src)
{
assert(devinfo->ver >= 8);
@ -1348,7 +1348,7 @@ set_3src_control_index(const struct gen_device_info *devinfo,
}
static bool
set_3src_source_index(const struct gen_device_info *devinfo,
set_3src_source_index(const struct intel_device_info *devinfo,
brw_compact_inst *dst, const brw_inst *src)
{
assert(devinfo->ver >= 8);
@ -1415,7 +1415,7 @@ set_3src_source_index(const struct gen_device_info *devinfo,
}
static bool
set_3src_subreg_index(const struct gen_device_info *devinfo,
set_3src_subreg_index(const struct intel_device_info *devinfo,
brw_compact_inst *dst, const brw_inst *src)
{
assert(devinfo->ver >= 12);
@ -1437,7 +1437,7 @@ set_3src_subreg_index(const struct gen_device_info *devinfo,
}
static bool
has_unmapped_bits(const struct gen_device_info *devinfo, const brw_inst *src)
has_unmapped_bits(const struct intel_device_info *devinfo, const brw_inst *src)
{
/* EOT can only be mapped on a send if the src1 is an immediate */
if ((brw_inst_opcode(devinfo, src) == BRW_OPCODE_SENDC ||
@ -1471,7 +1471,7 @@ has_unmapped_bits(const struct gen_device_info *devinfo, const brw_inst *src)
}
static bool
has_3src_unmapped_bits(const struct gen_device_info *devinfo,
has_3src_unmapped_bits(const struct intel_device_info *devinfo,
const brw_inst *src)
{
/* Check for three-source instruction bits that don't map to any of the
@ -1499,7 +1499,7 @@ has_3src_unmapped_bits(const struct gen_device_info *devinfo,
}
static bool
brw_try_compact_3src_instruction(const struct gen_device_info *devinfo,
brw_try_compact_3src_instruction(const struct intel_device_info *devinfo,
brw_compact_inst *dst, const brw_inst *src)
{
assert(devinfo->ver >= 8);
@ -1565,7 +1565,7 @@ brw_try_compact_3src_instruction(const struct gen_device_info *devinfo,
* Returns the compacted immediate, or -1 if immediate cannot be compacted
*/
static int
compact_immediate(const struct gen_device_info *devinfo,
compact_immediate(const struct intel_device_info *devinfo,
enum brw_reg_type type, unsigned imm)
{
if (devinfo->ver >= 12) {
@ -1636,7 +1636,7 @@ compact_immediate(const struct gen_device_info *devinfo,
}
static int
uncompact_immediate(const struct gen_device_info *devinfo,
uncompact_immediate(const struct intel_device_info *devinfo,
enum brw_reg_type type, unsigned compact_imm)
{
if (devinfo->ver >= 12) {
@ -1677,7 +1677,7 @@ uncompact_immediate(const struct gen_device_info *devinfo,
}
static bool
has_immediate(const struct gen_device_info *devinfo, const brw_inst *inst,
has_immediate(const struct intel_device_info *devinfo, const brw_inst *inst,
enum brw_reg_type *type)
{
if (brw_inst_src0_reg_file(devinfo, inst) == BRW_IMMEDIATE_VALUE) {
@ -1696,7 +1696,7 @@ has_immediate(const struct gen_device_info *devinfo, const brw_inst *inst,
* compaction.
*/
static brw_inst
precompact(const struct gen_device_info *devinfo, brw_inst inst)
precompact(const struct intel_device_info *devinfo, brw_inst inst)
{
if (brw_inst_src0_reg_file(devinfo, &inst) != BRW_IMMEDIATE_VALUE)
return inst;
@ -1791,7 +1791,7 @@ static bool
try_compact_instruction(const struct compaction_state *c,
brw_compact_inst *dst, const brw_inst *src)
{
const struct gen_device_info *devinfo = c->devinfo;
const struct intel_device_info *devinfo = c->devinfo;
brw_compact_inst temp;
assert(brw_inst_cmpt_control(devinfo, src) == 0);
@ -1895,7 +1895,7 @@ try_compact_instruction(const struct compaction_state *c,
}
bool
brw_try_compact_instruction(const struct gen_device_info *devinfo,
brw_try_compact_instruction(const struct intel_device_info *devinfo,
brw_compact_inst *dst, const brw_inst *src)
{
struct compaction_state c;
@ -1907,7 +1907,7 @@ static void
set_uncompacted_control(const struct compaction_state *c, brw_inst *dst,
brw_compact_inst *src)
{
const struct gen_device_info *devinfo = c->devinfo;
const struct intel_device_info *devinfo = c->devinfo;
uint32_t uncompacted =
c->control_index_table[brw_compact_inst_control_index(devinfo, src)];
@ -1941,7 +1941,7 @@ static void
set_uncompacted_datatype(const struct compaction_state *c, brw_inst *dst,
brw_compact_inst *src)
{
const struct gen_device_info *devinfo = c->devinfo;
const struct intel_device_info *devinfo = c->devinfo;
uint32_t uncompacted =
c->datatype_table[brw_compact_inst_datatype_index(devinfo, src)];
@ -1970,7 +1970,7 @@ static void
set_uncompacted_subreg(const struct compaction_state *c, brw_inst *dst,
brw_compact_inst *src)
{
const struct gen_device_info *devinfo = c->devinfo;
const struct intel_device_info *devinfo = c->devinfo;
uint16_t uncompacted =
c->subreg_table[brw_compact_inst_subreg_index(devinfo, src)];
@ -1989,7 +1989,7 @@ static void
set_uncompacted_src0(const struct compaction_state *c, brw_inst *dst,
brw_compact_inst *src)
{
const struct gen_device_info *devinfo = c->devinfo;
const struct intel_device_info *devinfo = c->devinfo;
uint32_t compacted = brw_compact_inst_src0_index(devinfo, src);
uint16_t uncompacted = c->src0_index_table[compacted];
@ -2008,7 +2008,7 @@ static void
set_uncompacted_src1(const struct compaction_state *c, brw_inst *dst,
brw_compact_inst *src)
{
const struct gen_device_info *devinfo = c->devinfo;
const struct intel_device_info *devinfo = c->devinfo;
uint16_t uncompacted =
c->src1_index_table[brw_compact_inst_src1_index(devinfo, src)];
@ -2027,7 +2027,7 @@ static void
set_uncompacted_3src_control_index(const struct compaction_state *c,
brw_inst *dst, brw_compact_inst *src)
{
const struct gen_device_info *devinfo = c->devinfo;
const struct intel_device_info *devinfo = c->devinfo;
assert(devinfo->ver >= 8);
if (devinfo->verx10 >= 125) {
@ -2088,7 +2088,7 @@ set_uncompacted_3src_control_index(const struct compaction_state *c,
}
static void
set_uncompacted_3src_source_index(const struct gen_device_info *devinfo,
set_uncompacted_3src_source_index(const struct intel_device_info *devinfo,
brw_inst *dst, brw_compact_inst *src)
{
assert(devinfo->ver >= 8);
@ -2137,7 +2137,7 @@ set_uncompacted_3src_source_index(const struct gen_device_info *devinfo,
}
static void
set_uncompacted_3src_subreg_index(const struct gen_device_info *devinfo,
set_uncompacted_3src_subreg_index(const struct intel_device_info *devinfo,
brw_inst *dst, brw_compact_inst *src)
{
assert(devinfo->ver >= 12);
@ -2155,7 +2155,7 @@ static void
brw_uncompact_3src_instruction(const struct compaction_state *c,
brw_inst *dst, brw_compact_inst *src)
{
const struct gen_device_info *devinfo = c->devinfo;
const struct intel_device_info *devinfo = c->devinfo;
assert(devinfo->ver >= 8);
#define uncompact(field) \
@ -2203,7 +2203,7 @@ static void
uncompact_instruction(const struct compaction_state *c, brw_inst *dst,
brw_compact_inst *src)
{
const struct gen_device_info *devinfo = c->devinfo;
const struct intel_device_info *devinfo = c->devinfo;
memset(dst, 0, sizeof(*dst));
if (devinfo->ver >= 8 &&
@ -2263,7 +2263,7 @@ uncompact_instruction(const struct compaction_state *c, brw_inst *dst,
}
void
brw_uncompact_instruction(const struct gen_device_info *devinfo, brw_inst *dst,
brw_uncompact_instruction(const struct intel_device_info *devinfo, brw_inst *dst,
brw_compact_inst *src)
{
struct compaction_state c;
@ -2271,7 +2271,7 @@ brw_uncompact_instruction(const struct gen_device_info *devinfo, brw_inst *dst,
uncompact_instruction(&c, dst, src);
}
void brw_debug_compact_uncompact(const struct gen_device_info *devinfo,
void brw_debug_compact_uncompact(const struct intel_device_info *devinfo,
brw_inst *orig,
brw_inst *uncompacted)
{
@ -2308,7 +2308,7 @@ compacted_between(int old_ip, int old_target_ip, int *compacted_counts)
}
static void
update_uip_jip(const struct gen_device_info *devinfo, brw_inst *insn,
update_uip_jip(const struct intel_device_info *devinfo, brw_inst *insn,
int this_old_ip, int *compacted_counts)
{
/* JIP and UIP are in units of:
@ -2336,7 +2336,7 @@ update_uip_jip(const struct gen_device_info *devinfo, brw_inst *insn,
}
static void
update_gfx4_jump_count(const struct gen_device_info *devinfo, brw_inst *insn,
update_gfx4_jump_count(const struct intel_device_info *devinfo, brw_inst *insn,
int this_old_ip, int *compacted_counts)
{
assert(devinfo->ver == 5 || devinfo->is_g4x);
@ -2360,7 +2360,7 @@ update_gfx4_jump_count(const struct gen_device_info *devinfo, brw_inst *insn,
static void
compaction_state_init(struct compaction_state *c,
const struct gen_device_info *devinfo)
const struct intel_device_info *devinfo)
{
assert(g45_control_index_table[ARRAY_SIZE(g45_control_index_table) - 1] != 0);
assert(g45_datatype_table[ARRAY_SIZE(g45_datatype_table) - 1] != 0);
@ -2450,7 +2450,7 @@ brw_compact_instructions(struct brw_codegen *p, int start_offset,
if (INTEL_DEBUG & DEBUG_NO_COMPACTION)
return;
const struct gen_device_info *devinfo = p->devinfo;
const struct intel_device_info *devinfo = p->devinfo;
void *store = p->store + start_offset / 16;
/* For an instruction at byte offset 16*i before compaction, this is the
* number of compacted instructions minus the number of padding NOP/NENOPs

4
src/intel/compiler/brw_eu_defines.h
View file

@ -1194,7 +1194,7 @@ tgl_swsb_src_dep(struct tgl_swsb swsb)
* SWSB annotation.
*/
static inline uint8_t
tgl_swsb_encode(const struct gen_device_info *devinfo, struct tgl_swsb swsb)
tgl_swsb_encode(const struct intel_device_info *devinfo, struct tgl_swsb swsb)
{
if (!swsb.mode) {
const unsigned pipe = devinfo->verx10 < 125 ? 0 :
@ -1216,7 +1216,7 @@ tgl_swsb_encode(const struct gen_device_info *devinfo, struct tgl_swsb swsb)
* tgl_swsb.
*/
static inline struct tgl_swsb
tgl_swsb_decode(const struct gen_device_info *devinfo, const enum opcode opcode,
tgl_swsb_decode(const struct intel_device_info *devinfo, const enum opcode opcode,
const uint8_t x)
{
if (x & 0x80) {

128
src/intel/compiler/brw_eu_emit.c
View file

@ -47,7 +47,7 @@ gfx6_resolve_implied_move(struct brw_codegen *p,
struct brw_reg *src,
unsigned msg_reg_nr)
{
const struct gen_device_info *devinfo = p->devinfo;
const struct intel_device_info *devinfo = p->devinfo;
if (devinfo->ver < 6)
return;
@ -78,7 +78,7 @@ gfx7_convert_mrf_to_grf(struct brw_codegen *p, struct brw_reg *reg)
* Since we're pretending to have 16 MRFs anyway, we may as well use the
* registers required for messages with EOT.
*/
const struct gen_device_info *devinfo = p->devinfo;
const struct intel_device_info *devinfo = p->devinfo;
if (devinfo->ver >= 7 && reg->file == BRW_MESSAGE_REGISTER_FILE) {
reg->file = BRW_GENERAL_REGISTER_FILE;
reg->nr += GFX7_MRF_HACK_START;
@ -88,7 +88,7 @@ gfx7_convert_mrf_to_grf(struct brw_codegen *p, struct brw_reg *reg)
void
brw_set_dest(struct brw_codegen *p, brw_inst *inst, struct brw_reg dest)
{
const struct gen_device_info *devinfo = p->devinfo;
const struct intel_device_info *devinfo = p->devinfo;
if (dest.file == BRW_MESSAGE_REGISTER_FILE)
assert((dest.nr & ~BRW_MRF_COMPR4) < BRW_MAX_MRF(devinfo->ver));
@ -208,7 +208,7 @@ brw_set_dest(struct brw_codegen *p, brw_inst *inst, struct brw_reg dest)
void
brw_set_src0(struct brw_codegen *p, brw_inst *inst, struct brw_reg reg)
{
const struct gen_device_info *devinfo = p->devinfo;
const struct intel_device_info *devinfo = p->devinfo;
if (reg.file == BRW_MESSAGE_REGISTER_FILE)
assert((reg.nr & ~BRW_MRF_COMPR4) < BRW_MAX_MRF(devinfo->ver));
@ -344,7 +344,7 @@ brw_set_src0(struct brw_codegen *p, brw_inst *inst, struct brw_reg reg)
void
brw_set_src1(struct brw_codegen *p, brw_inst *inst, struct brw_reg reg)
{
const struct gen_device_info *devinfo = p->devinfo;
const struct intel_device_info *devinfo = p->devinfo;
if (reg.file == BRW_GENERAL_REGISTER_FILE)
assert(reg.nr < 128);
@ -455,7 +455,7 @@ void
brw_set_desc_ex(struct brw_codegen *p, brw_inst *inst,
unsigned desc, unsigned ex_desc)
{
const struct gen_device_info *devinfo = p->devinfo;
const struct intel_device_info *devinfo = p->devinfo;
assert(brw_inst_opcode(devinfo, inst) == BRW_OPCODE_SEND ||
brw_inst_opcode(devinfo, inst) == BRW_OPCODE_SENDC);
if (devinfo->ver < 12)
@ -473,7 +473,7 @@ static void brw_set_math_message( struct brw_codegen *p,
bool low_precision,
unsigned dataType )
{
const struct gen_device_info *devinfo = p->devinfo;
const struct intel_device_info *devinfo = p->devinfo;
unsigned msg_length;
unsigned response_length;
@ -520,7 +520,7 @@ static void brw_set_ff_sync_message(struct brw_codegen *p,
unsigned response_length,
bool end_of_thread)
{
const struct gen_device_info *devinfo = p->devinfo;
const struct intel_device_info *devinfo = p->devinfo;
brw_set_desc(p, insn, brw_message_desc(
devinfo, 1, response_length, true));
@ -544,7 +544,7 @@ static void brw_set_urb_message( struct brw_codegen *p,
unsigned offset,
unsigned swizzle_control )
{
const struct gen_device_info *devinfo = p->devinfo;
const struct intel_device_info *devinfo = p->devinfo;
assert(devinfo->ver < 7 || swizzle_control != BRW_URB_SWIZZLE_TRANSPOSE);
assert(devinfo->ver < 7 || !(flags & BRW_URB_WRITE_ALLOCATE));
@ -591,7 +591,7 @@ gfx7_set_dp_scratch_message(struct brw_codegen *p,
unsigned rlen,
bool header_present)
{
const struct gen_device_info *devinfo = p->devinfo;
const struct intel_device_info *devinfo = p->devinfo;
assert(num_regs == 1 || num_regs == 2 || num_regs == 4 ||
(devinfo->ver >= 8 && num_regs == 8));
const unsigned block_size = (devinfo->ver >= 8 ? util_logbase2(num_regs) :
@ -610,7 +610,7 @@ gfx7_set_dp_scratch_message(struct brw_codegen *p,
}
static void
brw_inst_set_state(const struct gen_device_info *devinfo,
brw_inst_set_state(const struct intel_device_info *devinfo,
brw_inst *insn,
const struct brw_insn_state *state)
{
@ -694,7 +694,7 @@ brw_append_data(struct brw_codegen *p, void *data,
brw_inst *
brw_next_insn(struct brw_codegen *p, unsigned opcode)
{
const struct gen_device_info *devinfo = p->devinfo;
const struct intel_device_info *devinfo = p->devinfo;
brw_inst *insn = brw_append_insns(p, 1, sizeof(brw_inst));
memset(insn, 0, sizeof(*insn));
@ -742,7 +742,7 @@ get_3src_subreg_nr(struct brw_reg reg)
}
static enum gfx10_align1_3src_vertical_stride
to_3src_align1_vstride(const struct gen_device_info *devinfo,
to_3src_align1_vstride(const struct intel_device_info *devinfo,
enum brw_vertical_stride vstride)
{
switch (vstride) {
@ -786,7 +786,7 @@ static brw_inst *
brw_alu3(struct brw_codegen *p, unsigned opcode, struct brw_reg dest,
struct brw_reg src0, struct brw_reg src1, struct brw_reg src2)
{
const struct gen_device_info *devinfo = p->devinfo;
const struct intel_device_info *devinfo = p->devinfo;
brw_inst *inst = next_insn(p, opcode);
gfx7_convert_mrf_to_grf(p, &dest);
@ -1102,7 +1102,7 @@ ALU2(SUBB)
brw_inst *
brw_MOV(struct brw_codegen *p, struct brw_reg dest, struct brw_reg src0)
{
const struct gen_device_info *devinfo = p->devinfo;
const struct intel_device_info *devinfo = p->devinfo;
/* When converting F->DF on IVB/BYT, every odd source channel is ignored.
* To avoid the problems that causes, we use an <X,2,0> source region to
@ -1227,7 +1227,7 @@ brw_PLN(struct brw_codegen *p, struct brw_reg dest,
brw_inst *
brw_F32TO16(struct brw_codegen *p, struct brw_reg dst, struct brw_reg src)
{
const struct gen_device_info *devinfo = p->devinfo;
const struct intel_device_info *devinfo = p->devinfo;
const bool align16 = brw_get_default_access_mode(p) == BRW_ALIGN_16;
/* The F32TO16 instruction doesn't support 32-bit destination types in
* Align1 mode, and neither does the Gfx8 implementation in terms of a
@ -1277,7 +1277,7 @@ brw_F32TO16(struct brw_codegen *p, struct brw_reg dst, struct brw_reg src)
brw_inst *
brw_F16TO32(struct brw_codegen *p, struct brw_reg dst, struct brw_reg src)
{
const struct gen_device_info *devinfo = p->devinfo;
const struct intel_device_info *devinfo = p->devinfo;
bool align16 = brw_get_default_access_mode(p) == BRW_ALIGN_16;
if (align16) {
@ -1327,7 +1327,7 @@ brw_inst *
brw_JMPI(struct brw_codegen *p, struct brw_reg index,
unsigned predicate_control)
{
const struct gen_device_info *devinfo = p->devinfo;
const struct intel_device_info *devinfo = p->devinfo;
struct brw_reg ip = brw_ip_reg();
brw_inst *inst = brw_alu2(p, BRW_OPCODE_JMPI, ip, ip, index);
@ -1397,7 +1397,7 @@ get_inner_do_insn(struct brw_codegen *p)
brw_inst *
brw_IF(struct brw_codegen *p, unsigned execute_size)
{
const struct gen_device_info *devinfo = p->devinfo;
const struct intel_device_info *devinfo = p->devinfo;
brw_inst *insn;
insn = next_insn(p, BRW_OPCODE_IF);
@ -1446,7 +1446,7 @@ brw_inst *
gfx6_IF(struct brw_codegen *p, enum brw_conditional_mod conditional,
struct brw_reg src0, struct brw_reg src1)
{
const struct gen_device_info *devinfo = p->devinfo;
const struct intel_device_info *devinfo = p->devinfo;
brw_inst *insn;
insn = next_insn(p, BRW_OPCODE_IF);
@ -1472,7 +1472,7 @@ static void
convert_IF_ELSE_to_ADD(struct brw_codegen *p,
brw_inst *if_inst, brw_inst *else_inst)
{
const struct gen_device_info *devinfo = p->devinfo;
const struct intel_device_info *devinfo = p->devinfo;
/* The next instruction (where the ENDIF would be, if it existed) */
brw_inst *next_inst = &p->store[p->nr_insn];
@ -1513,7 +1513,7 @@ static void
patch_IF_ELSE(struct brw_codegen *p,
brw_inst *if_inst, brw_inst *else_inst, brw_inst *endif_inst)
{
const struct gen_device_info *devinfo = p->devinfo;
const struct intel_device_info *devinfo = p->devinfo;
/* We shouldn't be patching IF and ELSE instructions in single program flow
* mode when gen < 6, because in single program flow mode on those
@ -1600,7 +1600,7 @@ patch_IF_ELSE(struct brw_codegen *p,
void
brw_ELSE(struct brw_codegen *p)
{
const struct gen_device_info *devinfo = p->devinfo;
const struct intel_device_info *devinfo = p->devinfo;
brw_inst *insn;
insn = next_insn(p, BRW_OPCODE_ELSE);
@ -1639,7 +1639,7 @@ brw_ELSE(struct brw_codegen *p)
void
brw_ENDIF(struct brw_codegen *p)
{
const struct gen_device_info *devinfo = p->devinfo;
const struct intel_device_info *devinfo = p->devinfo;
brw_inst *insn = NULL;
brw_inst *else_inst = NULL;
brw_inst *if_inst = NULL;
@ -1720,7 +1720,7 @@ brw_ENDIF(struct brw_codegen *p)
brw_inst *
brw_BREAK(struct brw_codegen *p)
{
const struct gen_device_info *devinfo = p->devinfo;
const struct intel_device_info *devinfo = p->devinfo;
brw_inst *insn;
insn = next_insn(p, BRW_OPCODE_BREAK);
@ -1747,7 +1747,7 @@ brw_BREAK(struct brw_codegen *p)
brw_inst *
brw_CONT(struct brw_codegen *p)
{
const struct gen_device_info *devinfo = p->devinfo;
const struct intel_device_info *devinfo = p->devinfo;
brw_inst *insn;
insn = next_insn(p, BRW_OPCODE_CONTINUE);
@ -1771,7 +1771,7 @@ brw_CONT(struct brw_codegen *p)
brw_inst *
brw_HALT(struct brw_codegen *p)
{
const struct gen_device_info *devinfo = p->devinfo;
const struct intel_device_info *devinfo = p->devinfo;
brw_inst *insn;
insn = next_insn(p, BRW_OPCODE_HALT);
@ -1816,7 +1816,7 @@ brw_HALT(struct brw_codegen *p)
brw_inst *
brw_DO(struct brw_codegen *p, unsigned execute_size)
{
const struct gen_device_info *devinfo = p->devinfo;
const struct intel_device_info *devinfo = p->devinfo;
if (devinfo->ver >= 6 || p->single_program_flow) {
push_loop_stack(p, &p->store[p->nr_insn]);
@ -1850,7 +1850,7 @@ brw_DO(struct brw_codegen *p, unsigned execute_size)
static void
brw_patch_break_cont(struct brw_codegen *p, brw_inst *while_inst)
{
const struct gen_device_info *devinfo = p->devinfo;
const struct intel_device_info *devinfo = p->devinfo;
brw_inst *do_inst = get_inner_do_insn(p);
brw_inst *inst;
unsigned br = brw_jump_scale(devinfo);
@ -1875,7 +1875,7 @@ brw_patch_break_cont(struct brw_codegen *p, brw_inst *while_inst)
brw_inst *
brw_WHILE(struct brw_codegen *p)
{
const struct gen_device_info *devinfo = p->devinfo;
const struct intel_device_info *devinfo = p->devinfo;
brw_inst *insn, *do_insn;
unsigned br = brw_jump_scale(devinfo);
@ -1939,7 +1939,7 @@ brw_WHILE(struct brw_codegen *p)
*/
void brw_land_fwd_jump(struct brw_codegen *p, int jmp_insn_idx)
{
const struct gen_device_info *devinfo = p->devinfo;
const struct intel_device_info *devinfo = p->devinfo;
brw_inst *jmp_insn = &p->store[jmp_insn_idx];
unsigned jmpi = 1;
@ -1963,7 +1963,7 @@ void brw_CMP(struct brw_codegen *p,
struct brw_reg src0,
struct brw_reg src1)
{
const struct gen_device_info *devinfo = p->devinfo;
const struct intel_device_info *devinfo = p->devinfo;
brw_inst *insn = next_insn(p, BRW_OPCODE_CMP);
brw_inst_set_cond_modifier(devinfo, insn, conditional);
@ -1992,7 +1992,7 @@ void brw_CMPN(struct brw_codegen *p,
struct brw_reg src0,
struct brw_reg src1)
{
const struct gen_device_info *devinfo = p->devinfo;
const struct intel_device_info *devinfo = p->devinfo;
brw_inst *insn = next_insn(p, BRW_OPCODE_CMPN);
brw_inst_set_cond_modifier(devinfo, insn, conditional);
@ -2029,7 +2029,7 @@ void gfx4_math(struct brw_codegen *p,
struct brw_reg src,
unsigned precision )
{
const struct gen_device_info *devinfo = p->devinfo;
const struct intel_device_info *devinfo = p->devinfo;
brw_inst *insn = next_insn(p, BRW_OPCODE_SEND);
unsigned data_type;
if (has_scalar_region(src)) {
@ -2062,7 +2062,7 @@ void gfx6_math(struct brw_codegen *p,
struct brw_reg src0,
struct brw_reg src1)
{
const struct gen_device_info *devinfo = p->devinfo;
const struct intel_device_info *devinfo = p->devinfo;
brw_inst *insn = next_insn(p, BRW_OPCODE_MATH);
assert(devinfo->ver >= 6);
@ -2131,7 +2131,7 @@ void brw_oword_block_write_scratch(struct brw_codegen *p,
int num_regs,
unsigned offset)
{
const struct gen_device_info *devinfo = p->devinfo;
const struct intel_device_info *devinfo = p->devinfo;
const unsigned target_cache =
(devinfo->ver >= 7 ? GFX7_SFID_DATAPORT_DATA_CACHE :
devinfo->ver >= 6 ? GFX6_SFID_DATAPORT_RENDER_CACHE :
@ -2244,7 +2244,7 @@ brw_oword_block_read_scratch(struct brw_codegen *p,
int num_regs,
unsigned offset)
{
const struct gen_device_info *devinfo = p->devinfo;
const struct intel_device_info *devinfo = p->devinfo;
const struct tgl_swsb swsb = brw_get_default_swsb(p);
if (devinfo->ver >= 6)
@ -2357,7 +2357,7 @@ void brw_oword_block_read(struct brw_codegen *p,
uint32_t offset,
uint32_t bind_table_index)
{
const struct gen_device_info *devinfo = p->devinfo;
const struct intel_device_info *devinfo = p->devinfo;
const unsigned target_cache =
(devinfo->ver >= 6 ? GFX6_SFID_DATAPORT_CONSTANT_CACHE :
BRW_SFID_DATAPORT_READ);
@ -2429,7 +2429,7 @@ brw_fb_WRITE(struct brw_codegen *p,
bool last_render_target,
bool header_present)
{
const struct gen_device_info *devinfo = p->devinfo;
const struct intel_device_info *devinfo = p->devinfo;
const unsigned target_cache =
(devinfo->ver >= 6 ? GFX6_SFID_DATAPORT_RENDER_CACHE :
BRW_SFID_DATAPORT_WRITE);
@ -2485,7 +2485,7 @@ gfx9_fb_READ(struct brw_codegen *p,
unsigned response_length,
bool per_sample)
{
const struct gen_device_info *devinfo = p->devinfo;
const struct intel_device_info *devinfo = p->devinfo;
assert(devinfo->ver >= 9);
const unsigned msg_subtype =
brw_get_default_exec_size(p) == BRW_EXECUTE_16 ? 0 : 1;
@ -2524,7 +2524,7 @@ void brw_SAMPLE(struct brw_codegen *p,
unsigned simd_mode,
unsigned return_format)
{
const struct gen_device_info *devinfo = p->devinfo;
const struct intel_device_info *devinfo = p->devinfo;
brw_inst *insn;
if (msg_reg_nr != -1)
@ -2576,7 +2576,7 @@ void brw_adjust_sampler_state_pointer(struct brw_codegen *p,
* exclusively use the offset - we have to use both.
*/
const struct gen_device_info *devinfo = p->devinfo;
const struct intel_device_info *devinfo = p->devinfo;
if (sampler_index.file == BRW_IMMEDIATE_VALUE) {
const int sampler_state_size = 16; /* 16 bytes */
@ -2623,7 +2623,7 @@ void brw_urb_WRITE(struct brw_codegen *p,
unsigned offset,
unsigned swizzle)
{
const struct gen_device_info *devinfo = p->devinfo;
const struct intel_device_info *devinfo = p->devinfo;
brw_inst *insn;
gfx6_resolve_implied_move(p, &src0, msg_reg_nr);
@ -2670,7 +2670,7 @@ brw_send_indirect_message(struct brw_codegen *p,
unsigned desc_imm,
bool eot)
{
const struct gen_device_info *devinfo = p->devinfo;
const struct intel_device_info *devinfo = p->devinfo;
struct brw_inst *send;
dst = retype(dst, BRW_REGISTER_TYPE_UW);
@ -2727,7 +2727,7 @@ brw_send_indirect_split_message(struct brw_codegen *p,
unsigned ex_desc_imm,
bool eot)
{
const struct gen_device_info *devinfo = p->devinfo;
const struct intel_device_info *devinfo = p->devinfo;
struct brw_inst *send;
dst = retype(dst, BRW_REGISTER_TYPE_UW);
@ -2869,7 +2869,7 @@ brw_send_indirect_surface_message(struct brw_codegen *p,
}
static bool
while_jumps_before_offset(const struct gen_device_info *devinfo,
while_jumps_before_offset(const struct intel_device_info *devinfo,
brw_inst *insn, int while_offset, int start_offset)
{
int scale = 16 / brw_jump_scale(devinfo);
@ -2885,7 +2885,7 @@ brw_find_next_block_end(struct brw_codegen *p, int start_offset)
{
int offset;
void *store = p->store;
const struct gen_device_info *devinfo = p->devinfo;
const struct intel_device_info *devinfo = p->devinfo;
int depth = 0;
@ -2930,7 +2930,7 @@ brw_find_next_block_end(struct brw_codegen *p, int start_offset)
static int
brw_find_loop_end(struct brw_codegen *p, int start_offset)
{
const struct gen_device_info *devinfo = p->devinfo;
const struct intel_device_info *devinfo = p->devinfo;
int offset;
void *store = p->store;
@ -2959,7 +2959,7 @@ brw_find_loop_end(struct brw_codegen *p, int start_offset)
void
brw_set_uip_jip(struct brw_codegen *p, int start_offset)
{
const struct gen_device_info *devinfo = p->devinfo;
const struct intel_device_info *devinfo = p->devinfo;
int offset;
int br = brw_jump_scale(devinfo);
int scale = 16 / br;
@ -3037,7 +3037,7 @@ void brw_ff_sync(struct brw_codegen *p,
unsigned response_length,
bool eot)
{
const struct gen_device_info *devinfo = p->devinfo;
const struct intel_device_info *devinfo = p->devinfo;
brw_inst *insn;
gfx6_resolve_implied_move(p, &src0, msg_reg_nr);
@ -3076,7 +3076,7 @@ brw_svb_write(struct brw_codegen *p,
unsigned binding_table_index,
bool send_commit_msg)
{
const struct gen_device_info *devinfo = p->devinfo;
const struct intel_device_info *devinfo = p->devinfo;
const unsigned target_cache =
(devinfo->ver >= 7 ? GFX7_SFID_DATAPORT_DATA_CACHE :
devinfo->ver >= 6 ? GFX6_SFID_DATAPORT_RENDER_CACHE :
@ -3120,7 +3120,7 @@ brw_untyped_atomic(struct brw_codegen *p,
bool response_expected,
bool header_present)
{
const struct gen_device_info *devinfo = p->devinfo;
const struct intel_device_info *devinfo = p->devinfo;
const unsigned sfid = (devinfo->ver >= 8 || devinfo->is_haswell ?
HSW_SFID_DATAPORT_DATA_CACHE_1 :
GFX7_SFID_DATAPORT_DATA_CACHE);
@ -3155,7 +3155,7 @@ brw_untyped_surface_read(struct brw_codegen *p,
unsigned msg_length,
unsigned num_channels)
{
const struct gen_device_info *devinfo = p->devinfo;
const struct intel_device_info *devinfo = p->devinfo;
const unsigned sfid = (devinfo->ver >= 8 || devinfo->is_haswell ?
HSW_SFID_DATAPORT_DATA_CACHE_1 :
GFX7_SFID_DATAPORT_DATA_CACHE);
@ -3178,7 +3178,7 @@ brw_untyped_surface_write(struct brw_codegen *p,
unsigned num_channels,
bool header_present)
{
const struct gen_device_info *devinfo = p->devinfo;
const struct intel_device_info *devinfo = p->devinfo;
const unsigned sfid = (devinfo->ver >= 8 || devinfo->is_haswell ?
HSW_SFID_DATAPORT_DATA_CACHE_1 :
GFX7_SFID_DATAPORT_DATA_CACHE);
@ -3204,7 +3204,7 @@ brw_set_memory_fence_message(struct brw_codegen *p,
bool commit_enable,
unsigned bti)
{
const struct gen_device_info *devinfo = p->devinfo;
const struct intel_device_info *devinfo = p->devinfo;
brw_set_desc(p, insn, brw_message_desc(
devinfo, 1, (commit_enable ? 1 : 0), true));
@ -3238,7 +3238,7 @@ brw_memory_fence(struct brw_codegen *p,
bool commit_enable,
unsigned bti)
{
const struct gen_device_info *devinfo = p->devinfo;
const struct intel_device_info *devinfo = p->devinfo;
dst = retype(vec1(dst), BRW_REGISTER_TYPE_UW);
src = retype(vec1(src), BRW_REGISTER_TYPE_UD);
@ -3264,7 +3264,7 @@ brw_pixel_interpolator_query(struct brw_codegen *p,
unsigned msg_length,
unsigned response_length)
{
const struct gen_device_info *devinfo = p->devinfo;
const struct intel_device_info *devinfo = p->devinfo;
const uint16_t exec_size = brw_get_default_exec_size(p);
const unsigned slot_group = brw_get_default_group(p) / 16;
const unsigned simd_mode = (exec_size == BRW_EXECUTE_16);
@ -3289,7 +3289,7 @@ void
brw_find_live_channel(struct brw_codegen *p, struct brw_reg dst,
struct brw_reg mask)
{
const struct gen_device_info *devinfo = p->devinfo;
const struct intel_device_info *devinfo = p->devinfo;
const unsigned exec_size = 1 << brw_get_default_exec_size(p);
const unsigned qtr_control = brw_get_default_group(p) / 8;
brw_inst *inst;
@ -3414,7 +3414,7 @@ brw_broadcast(struct brw_codegen *p,
struct brw_reg src,
struct brw_reg idx)
{
const struct gen_device_info *devinfo = p->devinfo;
const struct intel_device_info *devinfo = p->devinfo;
const bool align1 = brw_get_default_access_mode(p) == BRW_ALIGN_1;
brw_inst *inst;
@ -3494,7 +3494,7 @@ brw_broadcast(struct brw_codegen *p,
/* Use indirect addressing to fetch the specified component. */
if (type_sz(src.type) > 4 &&
(devinfo->is_cherryview || gen_device_info_is_9lp(devinfo) ||
(devinfo->is_cherryview || intel_device_info_is_9lp(devinfo) ||
!devinfo->has_64bit_float)) {
/* From the Cherryview PRM Vol 7. "Register Region Restrictions":
*
@ -3562,7 +3562,7 @@ void brw_shader_time_add(struct brw_codegen *p,
struct brw_reg payload,
uint32_t surf_index)
{
const struct gen_device_info *devinfo = p->devinfo;
const struct intel_device_info *devinfo = p->devinfo;
const unsigned sfid = (devinfo->ver >= 8 || devinfo->is_haswell ?
HSW_SFID_DATAPORT_DATA_CACHE_1 :
GFX7_SFID_DATAPORT_DATA_CACHE);
@ -3598,7 +3598,7 @@ void brw_shader_time_add(struct brw_codegen *p,
void
brw_barrier(struct brw_codegen *p, struct brw_reg src)
{
const struct gen_device_info *devinfo = p->devinfo;
const struct intel_device_info *devinfo = p->devinfo;
struct brw_inst *inst;
assert(devinfo->ver >= 7);
@ -3626,7 +3626,7 @@ brw_barrier(struct brw_codegen *p, struct brw_reg src)
void
brw_WAIT(struct brw_codegen *p)
{
const struct gen_device_info *devinfo = p->devinfo;
const struct intel_device_info *devinfo = p->devinfo;
struct brw_inst *insn;
struct brw_reg src = brw_notification_reg();
@ -3674,7 +3674,7 @@ brw_float_controls_mode(struct brw_codegen *p,
}
void
brw_update_reloc_imm(const struct gen_device_info *devinfo,
brw_update_reloc_imm(const struct intel_device_info *devinfo,
brw_inst *inst,
uint32_t value)
{

70
src/intel/compiler/brw_eu_validate.c
View file

@ -90,7 +90,7 @@ contains(const struct string haystack, const struct string needle)
#define WIDTH(width) (1 << (width))
static bool
inst_is_send(const struct gen_device_info *devinfo, const brw_inst *inst)
inst_is_send(const struct intel_device_info *devinfo, const brw_inst *inst)
{
switch (brw_inst_opcode(devinfo, inst)) {
case BRW_OPCODE_SEND:
@ -104,7 +104,7 @@ inst_is_send(const struct gen_device_info *devinfo, const brw_inst *inst)
}
static bool
inst_is_split_send(const struct gen_device_info *devinfo, const brw_inst *inst)
inst_is_split_send(const struct intel_device_info *devinfo, const brw_inst *inst)
{
if (devinfo->ver >= 12) {
return inst_is_send(devinfo, inst);
@ -132,14 +132,14 @@ signed_type(unsigned type)
}
static enum brw_reg_type
inst_dst_type(const struct gen_device_info *devinfo, const brw_inst *inst)
inst_dst_type(const struct intel_device_info *devinfo, const brw_inst *inst)
{
return (devinfo->ver < 12 || !inst_is_send(devinfo, inst)) ?
brw_inst_dst_type(devinfo, inst) : BRW_REGISTER_TYPE_D;
}
static bool
inst_is_raw_move(const struct gen_device_info *devinfo, const brw_inst *inst)
inst_is_raw_move(const struct intel_device_info *devinfo, const brw_inst *inst)
{
unsigned dst_type = signed_type(inst_dst_type(devinfo, inst));
unsigned src_type = signed_type(brw_inst_src0_type(devinfo, inst));
@ -162,14 +162,14 @@ inst_is_raw_move(const struct gen_device_info *devinfo, const brw_inst *inst)
}
static bool
dst_is_null(const struct gen_device_info *devinfo, const brw_inst *inst)
dst_is_null(const struct intel_device_info *devinfo, const brw_inst *inst)
{
return brw_inst_dst_reg_file(devinfo, inst) == BRW_ARCHITECTURE_REGISTER_FILE &&
brw_inst_dst_da_reg_nr(devinfo, inst) == BRW_ARF_NULL;
}
static bool
src0_is_null(const struct gen_device_info *devinfo, const brw_inst *inst)
src0_is_null(const struct intel_device_info *devinfo, const brw_inst *inst)
{
return brw_inst_src0_address_mode(devinfo, inst) == BRW_ADDRESS_DIRECT &&
brw_inst_src0_reg_file(devinfo, inst) == BRW_ARCHITECTURE_REGISTER_FILE &&
@ -177,28 +177,28 @@ src0_is_null(const struct gen_device_info *devinfo, const brw_inst *inst)
}
static bool
src1_is_null(const struct gen_device_info *devinfo, const brw_inst *inst)
src1_is_null(const struct intel_device_info *devinfo, const brw_inst *inst)
{
return brw_inst_src1_reg_file(devinfo, inst) == BRW_ARCHITECTURE_REGISTER_FILE &&
brw_inst_src1_da_reg_nr(devinfo, inst) == BRW_ARF_NULL;
}
static bool
src0_is_acc(const struct gen_device_info *devinfo, const brw_inst *inst)
src0_is_acc(const struct intel_device_info *devinfo, const brw_inst *inst)
{
return brw_inst_src0_reg_file(devinfo, inst) == BRW_ARCHITECTURE_REGISTER_FILE &&
(brw_inst_src0_da_reg_nr(devinfo, inst) & 0xF0) == BRW_ARF_ACCUMULATOR;
}
static bool
src1_is_acc(const struct gen_device_info *devinfo, const brw_inst *inst)
src1_is_acc(const struct intel_device_info *devinfo, const brw_inst *inst)
{
return brw_inst_src1_reg_file(devinfo, inst) == BRW_ARCHITECTURE_REGISTER_FILE &&
(brw_inst_src1_da_reg_nr(devinfo, inst) & 0xF0) == BRW_ARF_ACCUMULATOR;
}
static bool
src0_has_scalar_region(const struct gen_device_info *devinfo, const brw_inst *inst)
src0_has_scalar_region(const struct intel_device_info *devinfo, const brw_inst *inst)
{
return brw_inst_src0_vstride(devinfo, inst) == BRW_VERTICAL_STRIDE_0 &&
brw_inst_src0_width(devinfo, inst) == BRW_WIDTH_1 &&
@ -206,7 +206,7 @@ src0_has_scalar_region(const struct gen_device_info *devinfo, const brw_inst *in
}
static bool
src1_has_scalar_region(const struct gen_device_info *devinfo, const brw_inst *inst)
src1_has_scalar_region(const struct intel_device_info *devinfo, const brw_inst *inst)
{
return brw_inst_src1_vstride(devinfo, inst) == BRW_VERTICAL_STRIDE_0 &&
brw_inst_src1_width(devinfo, inst) == BRW_WIDTH_1 &&
@ -214,7 +214,7 @@ src1_has_scalar_region(const struct gen_device_info *devinfo, const brw_inst *in
}
static unsigned
num_sources_from_inst(const struct gen_device_info *devinfo,
num_sources_from_inst(const struct intel_device_info *devinfo,
const brw_inst *inst)
{
const struct opcode_desc *desc =
@ -269,7 +269,7 @@ num_sources_from_inst(const struct gen_device_info *devinfo,
}
static struct string
invalid_values(const struct gen_device_info *devinfo, const brw_inst *inst)
invalid_values(const struct intel_device_info *devinfo, const brw_inst *inst)
{
unsigned num_sources = num_sources_from_inst(devinfo, inst);
struct string error_msg = { .str = NULL, .len = 0 };
@ -339,7 +339,7 @@ invalid_values(const struct gen_device_info *devinfo, const brw_inst *inst)
}
static struct string
sources_not_null(const struct gen_device_info *devinfo,
sources_not_null(const struct intel_device_info *devinfo,
const brw_inst *inst)
{
unsigned num_sources = num_sources_from_inst(devinfo, inst);
@ -367,7 +367,7 @@ sources_not_null(const struct gen_device_info *devinfo,
}
static struct string
alignment_supported(const struct gen_device_info *devinfo,
alignment_supported(const struct intel_device_info *devinfo,
const brw_inst *inst)
{
struct string error_msg = { .str = NULL, .len = 0 };
@ -379,7 +379,7 @@ alignment_supported(const struct gen_device_info *devinfo,
}
static bool
inst_uses_src_acc(const struct gen_device_info *devinfo, const brw_inst *inst)
inst_uses_src_acc(const struct intel_device_info *devinfo, const brw_inst *inst)
{
/* Check instructions that use implicit accumulator sources */
switch (brw_inst_opcode(devinfo, inst)) {
@ -399,7 +399,7 @@ inst_uses_src_acc(const struct gen_device_info *devinfo, const brw_inst *inst)
}
static struct string
send_restrictions(const struct gen_device_info *devinfo,
send_restrictions(const struct intel_device_info *devinfo,
const brw_inst *inst)
{
struct string error_msg = { .str = NULL, .len = 0 };
@ -466,7 +466,7 @@ send_restrictions(const struct gen_device_info *devinfo,
}
static bool
is_unsupported_inst(const struct gen_device_info *devinfo,
is_unsupported_inst(const struct intel_device_info *devinfo,
const brw_inst *inst)
{
return brw_inst_opcode(devinfo, inst) == BRW_OPCODE_ILLEGAL;
@ -519,7 +519,7 @@ execution_type_for_type(enum brw_reg_type type)
* Returns the execution type of an instruction \p inst
*/
static enum brw_reg_type
execution_type(const struct gen_device_info *devinfo, const brw_inst *inst)
execution_type(const struct intel_device_info *devinfo, const brw_inst *inst)
{
unsigned num_sources = num_sources_from_inst(devinfo, inst);
enum brw_reg_type src0_exec_type, src1_exec_type;
@ -602,7 +602,7 @@ is_packed(unsigned vstride, unsigned width, unsigned hstride)
* to/from half-float.
*/
static bool
is_half_float_conversion(const struct gen_device_info *devinfo,
is_half_float_conversion(const struct intel_device_info *devinfo,
const brw_inst *inst)
{
enum brw_reg_type dst_type = brw_inst_dst_type(devinfo, inst);
@ -627,7 +627,7 @@ is_half_float_conversion(const struct gen_device_info *devinfo,
* Returns whether an instruction is using mixed float operation mode
*/
static bool
is_mixed_float(const struct gen_device_info *devinfo, const brw_inst *inst)
is_mixed_float(const struct intel_device_info *devinfo, const brw_inst *inst)
{
if (devinfo->ver < 8)
return false;
@ -662,7 +662,7 @@ is_mixed_float(const struct gen_device_info *devinfo, const brw_inst *inst)
* to/from byte.
*/
static bool
is_byte_conversion(const struct gen_device_info *devinfo,
is_byte_conversion(const struct intel_device_info *devinfo,
const brw_inst *inst)
{
enum brw_reg_type dst_type = brw_inst_dst_type(devinfo, inst);
@ -687,7 +687,7 @@ is_byte_conversion(const struct gen_device_info *devinfo,
* in the "Register Region Restrictions" section.
*/
static struct string
general_restrictions_based_on_operand_types(const struct gen_device_info *devinfo,
general_restrictions_based_on_operand_types(const struct intel_device_info *devinfo,
const brw_inst *inst)
{
const struct opcode_desc *desc =
@ -919,7 +919,7 @@ general_restrictions_based_on_operand_types(const struct gen_device_info *devinf
* in the "Register Region Restrictions" section.
*/
static struct string
general_restrictions_on_region_parameters(const struct gen_device_info *devinfo,
general_restrictions_on_region_parameters(const struct intel_device_info *devinfo,
const brw_inst *inst)
{
const struct opcode_desc *desc =
@ -1078,7 +1078,7 @@ general_restrictions_on_region_parameters(const struct gen_device_info *devinfo,
}
static struct string
special_restrictions_for_mixed_float_mode(const struct gen_device_info *devinfo,
special_restrictions_for_mixed_float_mode(const struct intel_device_info *devinfo,
const brw_inst *inst)
{
struct string error_msg = { .str = NULL, .len = 0 };
@ -1359,7 +1359,7 @@ registers_read(const uint64_t access_mask[static 32])
* Region Restrictions" section.
*/
static struct string
region_alignment_rules(const struct gen_device_info *devinfo,
region_alignment_rules(const struct intel_device_info *devinfo,
const brw_inst *inst)
{
const struct opcode_desc *desc =
@ -1673,7 +1673,7 @@ region_alignment_rules(const struct gen_device_info *devinfo,
}
static struct string
vector_immediate_restrictions(const struct gen_device_info *devinfo,
vector_immediate_restrictions(const struct intel_device_info *devinfo,
const brw_inst *inst)
{
unsigned num_sources = num_sources_from_inst(devinfo, inst);
@ -1735,7 +1735,7 @@ vector_immediate_restrictions(const struct gen_device_info *devinfo,
static struct string
special_requirements_for_handling_double_precision_data_types(
const struct gen_device_info *devinfo,
const struct intel_device_info *devinfo,
const brw_inst *inst)
{
unsigned num_sources = num_sources_from_inst(devinfo, inst);
@ -1817,7 +1817,7 @@ special_requirements_for_handling_double_precision_data_types(
*/
if (is_double_precision &&
brw_inst_access_mode(devinfo, inst) == BRW_ALIGN_1 &&
(devinfo->is_cherryview || gen_device_info_is_9lp(devinfo))) {
(devinfo->is_cherryview || intel_device_info_is_9lp(devinfo))) {
ERROR_IF(!is_scalar_region &&
(src_stride % 8 != 0 ||
dst_stride % 8 != 0 ||
@ -1842,7 +1842,7 @@ special_requirements_for_handling_double_precision_data_types(
* We assume that the restriction applies to GLK as well.
*/
if (is_double_precision &&
(devinfo->is_cherryview || gen_device_info_is_9lp(devinfo))) {
(devinfo->is_cherryview || intel_device_info_is_9lp(devinfo))) {
ERROR_IF(BRW_ADDRESS_REGISTER_INDIRECT_REGISTER == address_mode ||
BRW_ADDRESS_REGISTER_INDIRECT_REGISTER == dst_address_mode,
"Indirect addressing is not allowed when the execution type "
@ -1859,7 +1859,7 @@ special_requirements_for_handling_double_precision_data_types(
* We assume that the restriction does not apply to the null register.
*/
if (is_double_precision &&
(devinfo->is_cherryview || gen_device_info_is_9lp(devinfo))) {
(devinfo->is_cherryview || intel_device_info_is_9lp(devinfo))) {
ERROR_IF(brw_inst_opcode(devinfo, inst) == BRW_OPCODE_MAC ||
brw_inst_acc_wr_control(devinfo, inst) ||
(BRW_ARCHITECTURE_REGISTER_FILE == file &&
@ -1946,7 +1946,7 @@ special_requirements_for_handling_double_precision_data_types(
* We assume that the restriction applies to GLK as well.
*/
if (is_double_precision &&
(devinfo->is_cherryview || gen_device_info_is_9lp(devinfo))) {
(devinfo->is_cherryview || intel_device_info_is_9lp(devinfo))) {
ERROR_IF(brw_inst_no_dd_check(devinfo, inst) ||
brw_inst_no_dd_clear(devinfo, inst),
"DepCtrl is not allowed when the execution type is 64-bit");
@ -1956,7 +1956,7 @@ special_requirements_for_handling_double_precision_data_types(
}
static struct string
instruction_restrictions(const struct gen_device_info *devinfo,
instruction_restrictions(const struct intel_device_info *devinfo,
const brw_inst *inst)
{
struct string error_msg = { .str = NULL, .len = 0 };
@ -2026,7 +2026,7 @@ instruction_restrictions(const struct gen_device_info *devinfo,
}
bool
brw_validate_instruction(const struct gen_device_info *devinfo,
brw_validate_instruction(const struct intel_device_info *devinfo,
const brw_inst *inst, int offset,
struct disasm_info *disasm)
{
@ -2060,7 +2060,7 @@ brw_validate_instruction(const struct gen_device_info *devinfo,
}
bool
brw_validate_instructions(const struct gen_device_info *devinfo,
brw_validate_instructions(const struct intel_device_info *devinfo,
const void *assembly, int start_offset, int end_offset,
struct disasm_info *disasm)
{

54
src/intel/compiler/brw_fs.cpp
View file

@ -44,7 +44,7 @@
using namespace brw;
static unsigned get_lowered_simd_width(const struct gen_device_info *devinfo,
static unsigned get_lowered_simd_width(const struct intel_device_info *devinfo,
const fs_inst *inst);
void
@ -431,7 +431,7 @@ fs_inst::has_source_and_destination_hazard() const
}
bool
fs_inst::can_do_source_mods(const struct gen_device_info *devinfo) const
fs_inst::can_do_source_mods(const struct intel_device_info *devinfo) const
{
if (devinfo->ver == 6 && is_math())
return false;
@ -1092,7 +1092,7 @@ namespace {
}
unsigned
fs_inst::flags_read(const gen_device_info *devinfo) const
fs_inst::flags_read(const intel_device_info *devinfo) const
{
if (predicate == BRW_PREDICATE_ALIGN1_ANYV ||
predicate == BRW_PREDICATE_ALIGN1_ALLV) {
@ -1794,7 +1794,7 @@ brw_compute_urb_setup_index(struct brw_wm_prog_data *wm_prog_data)
}
static void
calculate_urb_setup(const struct gen_device_info *devinfo,
calculate_urb_setup(const struct intel_device_info *devinfo,
const struct brw_wm_prog_key *key,
struct brw_wm_prog_data *prog_data,
const nir_shader *nir)
@ -2267,7 +2267,7 @@ fs_visitor::compact_virtual_grfs()
}
static int
get_subgroup_id_param_index(const gen_device_info *devinfo,
get_subgroup_id_param_index(const intel_device_info *devinfo,
const brw_stage_prog_data *prog_data)
{
if (prog_data->nr_params == 0)
@ -4459,7 +4459,7 @@ lower_fb_write_logical_send(const fs_builder &bld, fs_inst *inst,
const fs_visitor::thread_payload &payload)
{
assert(inst->src[FB_WRITE_LOGICAL_SRC_COMPONENTS].file == IMM);
const gen_device_info *devinfo = bld.shader->devinfo;
const intel_device_info *devinfo = bld.shader->devinfo;
const fs_reg &color0 = inst->src[FB_WRITE_LOGICAL_SRC_COLOR0];
const fs_reg &color1 = inst->src[FB_WRITE_LOGICAL_SRC_COLOR1];
const fs_reg &src0_alpha = inst->src[FB_WRITE_LOGICAL_SRC_SRC0_ALPHA];
@ -4718,7 +4718,7 @@ lower_fb_write_logical_send(const fs_builder &bld, fs_inst *inst,
static void
lower_fb_read_logical_send(const fs_builder &bld, fs_inst *inst)
{
const gen_device_info *devinfo = bld.shader->devinfo;
const intel_device_info *devinfo = bld.shader->devinfo;
const fs_builder &ubld = bld.exec_all().group(8, 0);
const unsigned length = 2;
const fs_reg header = ubld.vgrf(BRW_REGISTER_TYPE_UD, length);
@ -4960,7 +4960,7 @@ lower_sampler_logical_send_gfx5(const fs_builder &bld, fs_inst *inst, opcode op,
}
static bool
is_high_sampler(const struct gen_device_info *devinfo, const fs_reg &sampler)
is_high_sampler(const struct intel_device_info *devinfo, const fs_reg &sampler)
{
if (devinfo->ver < 8 && !devinfo->is_haswell)
return false;
@ -4969,7 +4969,7 @@ is_high_sampler(const struct gen_device_info *devinfo, const fs_reg &sampler)
}
static unsigned
sampler_msg_type(const gen_device_info *devinfo,
sampler_msg_type(const intel_device_info *devinfo,
opcode opcode, bool shadow_compare)
{
assert(devinfo->ver >= 5);
@ -5044,7 +5044,7 @@ lower_sampler_logical_send_gfx7(const fs_builder &bld, fs_inst *inst, opcode op,
unsigned coord_components,
unsigned grad_components)
{
const gen_device_info *devinfo = bld.shader->devinfo;
const intel_device_info *devinfo = bld.shader->devinfo;
const brw_stage_prog_data *prog_data = bld.shader->stage_prog_data;
unsigned reg_width = bld.dispatch_width() / 8;
unsigned header_size = 0, length = 0;
@ -5420,7 +5420,7 @@ lower_sampler_logical_send_gfx7(const fs_builder &bld, fs_inst *inst, opcode op,
static void
lower_sampler_logical_send(const fs_builder &bld, fs_inst *inst, opcode op)
{
const gen_device_info *devinfo = bld.shader->devinfo;
const intel_device_info *devinfo = bld.shader->devinfo;
const fs_reg &coordinate = inst->src[TEX_LOGICAL_SRC_COORDINATE];
const fs_reg &shadow_c = inst->src[TEX_LOGICAL_SRC_SHADOW_C];
const fs_reg &lod = inst->src[TEX_LOGICAL_SRC_LOD];
@ -5502,7 +5502,7 @@ static void
setup_surface_descriptors(const fs_builder &bld, fs_inst *inst, uint32_t desc,
const fs_reg &surface, const fs_reg &surface_handle)
{
const ASSERTED gen_device_info *devinfo = bld.shader->devinfo;
const ASSERTED intel_device_info *devinfo = bld.shader->devinfo;
/* We must have exactly one of surface and surface_handle */
assert((surface.file == BAD_FILE) != (surface_handle.file == BAD_FILE));
@ -5534,7 +5534,7 @@ setup_surface_descriptors(const fs_builder &bld, fs_inst *inst, uint32_t desc,
static void
lower_surface_logical_send(const fs_builder &bld, fs_inst *inst)
{
const gen_device_info *devinfo = bld.shader->devinfo;
const intel_device_info *devinfo = bld.shader->devinfo;
/* Get the logical send arguments. */
const fs_reg &addr = inst->src[SURFACE_LOGICAL_SRC_ADDRESS];
@ -5781,7 +5781,7 @@ lower_surface_logical_send(const fs_builder &bld, fs_inst *inst)
static void
lower_surface_block_logical_send(const fs_builder &bld, fs_inst *inst)
{
const gen_device_info *devinfo = bld.shader->devinfo;
const intel_device_info *devinfo = bld.shader->devinfo;
assert(devinfo->ver >= 9);
/* Get the logical send arguments. */
@ -5867,7 +5867,7 @@ emit_a64_oword_block_header(const fs_builder &bld, const fs_reg &addr)
static void
lower_a64_logical_send(const fs_builder &bld, fs_inst *inst)
{
const gen_device_info *devinfo = bld.shader->devinfo;
const intel_device_info *devinfo = bld.shader->devinfo;
const fs_reg &addr = inst->src[0];
const fs_reg &src = inst->src[1];
@ -6026,7 +6026,7 @@ lower_a64_logical_send(const fs_builder &bld, fs_inst *inst)
static void
lower_varying_pull_constant_logical_send(const fs_builder &bld, fs_inst *inst)
{
const gen_device_info *devinfo = bld.shader->devinfo;
const intel_device_info *devinfo = bld.shader->devinfo;
const brw_compiler *compiler = bld.shader->compiler;
if (devinfo->ver >= 7) {
@ -6148,7 +6148,7 @@ lower_math_logical_send(const fs_builder &bld, fs_inst *inst)
static void
lower_btd_logical_send(const fs_builder &bld, fs_inst *inst)
{
const gen_device_info *devinfo = bld.shader->devinfo;
const intel_device_info *devinfo = bld.shader->devinfo;
fs_reg global_addr = inst->src[0];
const fs_reg &btd_record = inst->src[1];
@ -6218,7 +6218,7 @@ lower_btd_logical_send(const fs_builder &bld, fs_inst *inst)
static void
lower_trace_ray_logical_send(const fs_builder &bld, fs_inst *inst)
{
const gen_device_info *devinfo = bld.shader->devinfo;
const intel_device_info *devinfo = bld.shader->devinfo;
const fs_reg &bvh_level = inst->src[0];
assert(inst->src[1].file == BRW_IMMEDIATE_VALUE);
const uint32_t trace_ray_control = inst->src[1].ud;
@ -6489,7 +6489,7 @@ is_mixed_float_with_packed_fp16_dst(const fs_inst *inst)
* excessively restrictive.
*/
static unsigned
get_fpu_lowered_simd_width(const struct gen_device_info *devinfo,
get_fpu_lowered_simd_width(const struct intel_device_info *devinfo,
const fs_inst *inst)
{
/* Maximum execution size representable in the instruction controls. */
@ -6594,7 +6594,7 @@ get_fpu_lowered_simd_width(const struct gen_device_info *devinfo,
max_width = MIN2(max_width, 16);
/* From the IVB PRMs (applies to other devices that don't have the
* gen_device_info::supports_simd16_3src flag set):
* intel_device_info::supports_simd16_3src flag set):
* "In Align16 access mode, SIMD16 is not allowed for DW operations and
* SIMD8 is not allowed for DF operations."
*/
@ -6686,7 +6686,7 @@ get_fpu_lowered_simd_width(const struct gen_device_info *devinfo,
* represent).
*/
static unsigned
get_sampler_lowered_simd_width(const struct gen_device_info *devinfo,
get_sampler_lowered_simd_width(const struct intel_device_info *devinfo,
const fs_inst *inst)
{
/* If we have a min_lod parameter on anything other than a simple sample
@ -6747,7 +6747,7 @@ get_sampler_lowered_simd_width(const struct gen_device_info *devinfo,
* original execution size.
*/
static unsigned
get_lowered_simd_width(const struct gen_device_info *devinfo,
get_lowered_simd_width(const struct intel_device_info *devinfo,
const fs_inst *inst)
{
switch (inst->opcode) {
@ -8844,7 +8844,7 @@ is_used_in_not_interp_frag_coord(nir_ssa_def *def)
* also need the BRW_BARYCENTRIC_[NON]PERSPECTIVE_CENTROID mode set up.
*/
static unsigned
brw_compute_barycentric_interp_modes(const struct gen_device_info *devinfo,
brw_compute_barycentric_interp_modes(const struct intel_device_info *devinfo,
const nir_shader *shader)
{
unsigned barycentric_interp_modes = 0;
@ -9053,7 +9053,7 @@ brw_nir_demote_sample_qualifiers(nir_shader *nir)
void
brw_nir_populate_wm_prog_data(const nir_shader *shader,
const struct gen_device_info *devinfo,
const struct intel_device_info *devinfo,
const struct brw_wm_prog_key *key,
struct brw_wm_prog_data *prog_data)
{
@ -9134,7 +9134,7 @@ brw_compile_fs(const struct brw_compiler *compiler,
prog_data->base.stage = MESA_SHADER_FRAGMENT;
const struct gen_device_info *devinfo = compiler->devinfo;
const struct intel_device_info *devinfo = compiler->devinfo;
const unsigned max_subgroup_size = compiler->devinfo->ver >= 6 ? 32 : 16;
brw_nir_apply_key(nir, compiler, &key->base, max_subgroup_size, true);
@ -9388,7 +9388,7 @@ fill_push_const_block_info(struct brw_push_const_block *block, unsigned dwords)
}
static void
cs_fill_push_const_info(const struct gen_device_info *devinfo,
cs_fill_push_const_info(const struct intel_device_info *devinfo,
struct brw_cs_prog_data *cs_prog_data)
{
const struct brw_stage_prog_data *prog_data = &cs_prog_data->base;
@ -9735,7 +9735,7 @@ brw_compile_cs(const struct brw_compiler *compiler,
}
unsigned
brw_cs_simd_size_for_group_size(const struct gen_device_info *devinfo,
brw_cs_simd_size_for_group_size(const struct intel_device_info *devinfo,
const struct brw_cs_prog_data *cs_prog_data,
unsigned group_size)
{

2
src/intel/compiler/brw_fs.h
View file

@ -567,7 +567,7 @@ private:
const struct brw_compiler *compiler;
void *log_data; /* Passed to compiler->*_log functions */
const struct gen_device_info *devinfo;
const struct intel_device_info *devinfo;
struct brw_codegen *p;
struct brw_stage_prog_data * const prog_data;

4
src/intel/compiler/brw_fs_bank_conflicts.cpp
View file

@ -597,7 +597,7 @@ namespace {
* found experimentally.
*/
bool
is_conflict_optimized_out(const gen_device_info *devinfo, const fs_inst *inst)
is_conflict_optimized_out(const intel_device_info *devinfo, const fs_inst *inst)
{
return devinfo->ver >= 9 &&
((is_grf(inst->src[0]) && (reg_of(inst->src[0]) == reg_of(inst->src[1]) ||
@ -941,7 +941,7 @@ fs_visitor::opt_bank_conflicts()
* we don't know which bank each VGRF is going to end up aligned to.
*/
bool
has_bank_conflict(const gen_device_info *devinfo, const fs_inst *inst)
has_bank_conflict(const intel_device_info *devinfo, const fs_inst *inst)
{
return inst->is_3src(devinfo) &&
is_grf(inst->src[1]) && is_grf(inst->src[2]) &&

6
src/intel/compiler/brw_fs_cmod_propagation.cpp
View file

@ -51,7 +51,7 @@
using namespace brw;
static bool
cmod_propagate_cmp_to_add(const gen_device_info *devinfo, bblock_t *block,
cmod_propagate_cmp_to_add(const intel_device_info *devinfo, bblock_t *block,
fs_inst *inst)
{
bool read_flag = false;
@ -166,7 +166,7 @@ cmod_propagate_cmp_to_add(const gen_device_info *devinfo, bblock_t *block,
* or.z.f0(8) g78<8,8,1> g76<8,8,1>UD g77<8,8,1>UD
*/
static bool
cmod_propagate_not(const gen_device_info *devinfo, bblock_t *block,
cmod_propagate_not(const intel_device_info *devinfo, bblock_t *block,
fs_inst *inst)
{
const enum brw_conditional_mod cond = brw_negate_cmod(inst->conditional_mod);
@ -220,7 +220,7 @@ cmod_propagate_not(const gen_device_info *devinfo, bblock_t *block,
}
static bool
opt_cmod_propagation_local(const gen_device_info *devinfo, bblock_t *block)
opt_cmod_propagation_local(const intel_device_info *devinfo, bblock_t *block)
{
bool progress = false;
int ip = block->end_ip + 1;

8
src/intel/compiler/brw_fs_combine_constants.cpp
View file

@ -46,7 +46,7 @@ static const bool debug = false;
* replaced with a GRF source.
*/
static bool
could_coissue(const struct gen_device_info *devinfo, const fs_inst *inst)
could_coissue(const struct intel_device_info *devinfo, const fs_inst *inst)
{
if (devinfo->ver != 7)
return false;
@ -73,7 +73,7 @@ could_coissue(const struct gen_device_info *devinfo, const fs_inst *inst)
* Returns true for instructions that don't support immediate sources.
*/
static bool
must_promote_imm(const struct gen_device_info *devinfo, const fs_inst *inst)
must_promote_imm(const struct intel_device_info *devinfo, const fs_inst *inst)
{
switch (inst->opcode) {
case SHADER_OPCODE_POW:
@ -211,7 +211,7 @@ compare(const void *_a, const void *_b)
}
static bool
get_constant_value(const struct gen_device_info *devinfo,
get_constant_value(const struct intel_device_info *devinfo,
const fs_inst *inst, uint32_t src_idx,
void *out, brw_reg_type *out_type)
{
@ -336,7 +336,7 @@ representable_as_hf(float f, uint16_t *hf)
}
static bool
represent_src_as_imm(const struct gen_device_info *devinfo,
represent_src_as_imm(const struct intel_device_info *devinfo,
fs_reg *src)
{
/* TODO - Fix the codepath below to use a bfloat16 immediate on XeHP,

2
src/intel/compiler/brw_fs_copy_propagation.cpp
View file

@ -369,7 +369,7 @@ is_logic_op(enum opcode opcode)
static bool
can_take_stride(fs_inst *inst, brw_reg_type dst_type,
unsigned arg, unsigned stride,
const gen_device_info *devinfo)
const intel_device_info *devinfo)
{
if (stride > 4)
return false;

8
src/intel/compiler/brw_fs_generator.cpp
View file

@ -54,7 +54,7 @@ brw_file_from_reg(fs_reg *reg)
}
static struct brw_reg
brw_reg_from_fs_reg(const struct gen_device_info *devinfo, fs_inst *inst,
brw_reg_from_fs_reg(const struct intel_device_info *devinfo, fs_inst *inst,
fs_reg *reg, bool compressed)
{
struct brw_reg brw_reg;
@ -550,7 +550,7 @@ fs_generator::generate_mov_indirect(fs_inst *inst,
if (type_sz(reg.type) > 4 &&
((devinfo->ver == 7 && !devinfo->is_haswell) ||
devinfo->is_cherryview || gen_device_info_is_9lp(devinfo) ||
devinfo->is_cherryview || intel_device_info_is_9lp(devinfo) ||
!devinfo->has_64bit_float || devinfo->verx10 >= 125)) {
/* IVB has an issue (which we found empirically) where it reads two
* address register components per channel for indirectly addressed
@ -715,7 +715,7 @@ fs_generator::generate_shuffle(fs_inst *inst,
if (type_sz(src.type) > 4 &&
((devinfo->ver == 7 && !devinfo->is_haswell) ||
devinfo->is_cherryview || gen_device_info_is_9lp(devinfo) ||
devinfo->is_cherryview || intel_device_info_is_9lp(devinfo) ||
!devinfo->has_64bit_float)) {
/* IVB has an issue (which we found empirically) where it reads
* two address register components per channel for indirectly
@ -2538,7 +2538,7 @@ fs_generator::generate_code(const cfg_t *cfg, int dispatch_width,
struct brw_reg strided = stride(suboffset(src[0], component),
vstride, width, 0);
if (type_sz(src[0].type) > 4 &&
(devinfo->is_cherryview || gen_device_info_is_9lp(devinfo) ||
(devinfo->is_cherryview || intel_device_info_is_9lp(devinfo) ||
!devinfo->has_64bit_float)) {
/* IVB has an issue (which we found empirically) where it reads
* two address register components per channel for indirectly

2
src/intel/compiler/brw_fs_live_variables.h
View file

@ -138,7 +138,7 @@ protected:
void compute_live_variables();
void compute_start_end();
const struct gen_device_info *devinfo;
const struct intel_device_info *devinfo;
const cfg_t *cfg;
void *mem_ctx;
};

16
src/intel/compiler/brw_fs_lower_regioning.cpp
View file

@ -124,7 +124,7 @@ namespace {
* specified for the i-th source region.
*/
bool
has_invalid_src_region(const gen_device_info *devinfo, const fs_inst *inst,
has_invalid_src_region(const intel_device_info *devinfo, const fs_inst *inst,
unsigned i)
{
if (is_unordered(inst) || inst->is_control_source(i))
@ -165,7 +165,7 @@ namespace {
* specified for the destination region.
*/
bool
has_invalid_dst_region(const gen_device_info *devinfo,
has_invalid_dst_region(const intel_device_info *devinfo,
const fs_inst *inst)
{
if (is_unordered(inst)) {
@ -192,7 +192,7 @@ namespace {
* source or destination modifiers into separate MOV instructions.
*/
unsigned
has_invalid_exec_type(const gen_device_info *devinfo, const fs_inst *inst)
has_invalid_exec_type(const intel_device_info *devinfo, const fs_inst *inst)
{
switch (inst->opcode) {
case SHADER_OPCODE_QUAD_SWIZZLE:
@ -202,7 +202,7 @@ namespace {
case SHADER_OPCODE_BROADCAST:
case SHADER_OPCODE_MOV_INDIRECT:
return (((devinfo->ver == 7 && !devinfo->is_haswell) ||
devinfo->is_cherryview || gen_device_info_is_9lp(devinfo) ||
devinfo->is_cherryview || intel_device_info_is_9lp(devinfo) ||
devinfo->verx10 >= 125) && type_sz(inst->src[0].type) > 4) ||
(devinfo->verx10 >= 125 &&
brw_reg_type_is_floating_point(inst->src[0].type)) ?
@ -218,7 +218,7 @@ namespace {
* specified for the i-th source region.
*/
bool
has_invalid_src_modifiers(const gen_device_info *devinfo, const fs_inst *inst,
has_invalid_src_modifiers(const intel_device_info *devinfo, const fs_inst *inst,
unsigned i)
{
return (!inst->can_do_source_mods(devinfo) &&
@ -233,7 +233,7 @@ namespace {
* specified for the destination.
*/
bool
has_invalid_conversion(const gen_device_info *devinfo, const fs_inst *inst)
has_invalid_conversion(const intel_device_info *devinfo, const fs_inst *inst)
{
switch (inst->opcode) {
case BRW_OPCODE_MOV:
@ -254,7 +254,7 @@ namespace {
* Return whether the instruction has unsupported destination modifiers.
*/
bool
has_invalid_dst_modifiers(const gen_device_info *devinfo, const fs_inst *inst)
has_invalid_dst_modifiers(const intel_device_info *devinfo, const fs_inst *inst)
{
return (has_invalid_exec_type(devinfo, inst) &&
(inst->saturate || inst->conditional_mod)) ||
@ -488,7 +488,7 @@ namespace {
bool
lower_instruction(fs_visitor *v, bblock_t *block, fs_inst *inst)
{
const gen_device_info *devinfo = v->devinfo;
const intel_device_info *devinfo = v->devinfo;
bool progress = false;
if (has_invalid_dst_modifiers(devinfo, inst))

6
src/intel/compiler/brw_fs_nir.cpp
View file

@ -3145,7 +3145,7 @@ fs_inst *
fs_visitor::emit_non_coherent_fb_read(const fs_builder &bld, const fs_reg &dst,
unsigned target)
{
const struct gen_device_info *devinfo = bld.shader->devinfo;
const struct intel_device_info *devinfo = bld.shader->devinfo;
assert(bld.shader->stage == MESA_SHADER_FRAGMENT);
const brw_wm_prog_key *wm_key =
@ -4458,7 +4458,7 @@ fs_visitor::nir_emit_intrinsic(const fs_builder &bld, nir_intrinsic_instr *instr
(instr->num_components - 1) * type_sz(dest.type);
bool supports_64bit_indirects =
!devinfo->is_cherryview && !gen_device_info_is_9lp(devinfo);
!devinfo->is_cherryview && !intel_device_info_is_9lp(devinfo);
if (type_sz(dest.type) != 8 || supports_64bit_indirects) {
for (unsigned j = 0; j < instr->num_components; j++) {
@ -6211,7 +6211,7 @@ shuffle_from_32bit_read(const fs_builder &bld,
fs_reg
setup_imm_df(const fs_builder &bld, double v)
{
const struct gen_device_info *devinfo = bld.shader->devinfo;
const struct intel_device_info *devinfo = bld.shader->devinfo;
assert(devinfo->ver >= 7);
if (devinfo->ver >= 8)

8
src/intel/compiler/brw_fs_reg_allocate.cpp
View file

@ -85,7 +85,7 @@ aligned_bary_size(unsigned dispatch_width)
static void
brw_alloc_reg_set(struct brw_compiler *compiler, int dispatch_width)
{
const struct gen_device_info *devinfo = compiler->devinfo;
const struct intel_device_info *devinfo = compiler->devinfo;
int base_reg_count = BRW_MAX_GRF;
const int index = util_logbase2(dispatch_width / 8);
@ -489,7 +489,7 @@ private:
void *mem_ctx;
fs_visitor *fs;
const gen_device_info *devinfo;
const intel_device_info *devinfo;
const brw_compiler *compiler;
const fs_live_variables &live;
int live_instr_count;
@ -884,7 +884,7 @@ void
fs_reg_alloc::emit_unspill(const fs_builder &bld, fs_reg dst,
uint32_t spill_offset, unsigned count)
{
const gen_device_info *devinfo = bld.shader->devinfo;
const intel_device_info *devinfo = bld.shader->devinfo;
const unsigned reg_size = dst.component_size(bld.dispatch_width()) /
REG_SIZE;
assert(count % reg_size == 0);
@ -940,7 +940,7 @@ void
fs_reg_alloc::emit_spill(const fs_builder &bld, fs_reg src,
uint32_t spill_offset, unsigned count)
{
const gen_device_info *devinfo = bld.shader->devinfo;
const intel_device_info *devinfo = bld.shader->devinfo;
const unsigned reg_size = src.component_size(bld.dispatch_width()) /
REG_SIZE;
assert(count % reg_size == 0);

14
src/intel/compiler/brw_fs_scoreboard.cpp
View file

@ -69,7 +69,7 @@ namespace {
* instruction (e.g. when TGL_PIPE_NONE is specified in tgl_swsb).
*/
tgl_pipe
inferred_sync_pipe(const struct gen_device_info *devinfo, const fs_inst *inst)
inferred_sync_pipe(const struct intel_device_info *devinfo, const fs_inst *inst)
{
if (devinfo->verx10 >= 125) {
bool has_int_src = false, has_long_src = false;
@ -101,7 +101,7 @@ namespace {
* RegDist synchronization mechanism.
*/
tgl_pipe
inferred_exec_pipe(const struct gen_device_info *devinfo, const fs_inst *inst)
inferred_exec_pipe(const struct intel_device_info *devinfo, const fs_inst *inst)
{
const brw_reg_type t = get_exec_type(inst);
const bool is_dword_multiply = !brw_reg_type_is_floating_point(t) &&
@ -143,7 +143,7 @@ namespace {
* instruction.
*/
unsigned
ordered_unit(const struct gen_device_info *devinfo, const fs_inst *inst,
ordered_unit(const struct intel_device_info *devinfo, const fs_inst *inst,
unsigned p)
{
switch (inst->opcode) {
@ -881,7 +881,7 @@ namespace {
* dependency is present.
*/
tgl_sbid_mode
baked_unordered_dependency_mode(const struct gen_device_info *devinfo,
baked_unordered_dependency_mode(const struct intel_device_info *devinfo,
const fs_inst *inst,
const dependency_list &deps,
const ordered_address &jp)
@ -910,7 +910,7 @@ namespace {
* additional SYNC instructions.
*/
bool
baked_ordered_dependency_mode(const struct gen_device_info *devinfo,
baked_ordered_dependency_mode(const struct intel_device_info *devinfo,
const fs_inst *inst,
const dependency_list &deps,
const ordered_address &jp)
@ -948,7 +948,7 @@ namespace {
const fs_inst *inst, unsigned ip, scoreboard &sb)
{
const bool exec_all = inst->force_writemask_all;
const struct gen_device_info *devinfo = shader->devinfo;
const struct intel_device_info *devinfo = shader->devinfo;
const tgl_pipe p = inferred_exec_pipe(devinfo, inst);
const ordered_address jp = p ? ordered_address(p, jps[ip].jp[IDX(p)]) :
ordered_address();
@ -1169,7 +1169,7 @@ namespace {
const ordered_address *jps,
const dependency_list *deps)
{
const struct gen_device_info *devinfo = shader->devinfo;
const struct intel_device_info *devinfo = shader->devinfo;
unsigned ip = 0;
foreach_block_and_inst_safe(block, fs_inst, inst, shader->cfg) {

2
src/intel/compiler/brw_gen_enum.h
View file

@ -45,7 +45,7 @@ enum gen {
#define GFX_LE(gen) (GFX_LT(gen) | (gen))
static enum gen
gen_from_devinfo(const struct gen_device_info *devinfo)
gen_from_devinfo(const struct intel_device_info *devinfo)
{
switch (devinfo->verx10) {
case 40: return GFX4;

98
src/intel/compiler/brw_inst.h
View file

@ -55,7 +55,7 @@ static inline void brw_inst_set_bits(brw_inst *inst,
#define FC(name, hi4, lo4, hi12, lo12, assertions) \
static inline void \
brw_inst_set_##name(const struct gen_device_info *devinfo, \
brw_inst_set_##name(const struct intel_device_info *devinfo, \
brw_inst *inst, uint64_t v) \
{ \
assert(assertions); \
@ -65,7 +65,7 @@ brw_inst_set_##name(const struct gen_device_info *devinfo, \
brw_inst_set_bits(inst, hi4, lo4, v); \
} \
static inline uint64_t \
brw_inst_##name(const struct gen_device_info *devinfo, \
brw_inst_##name(const struct intel_device_info *devinfo, \
const brw_inst *inst) \
{ \
assert(assertions); \
@ -107,7 +107,7 @@ brw_inst_##name(const struct gen_device_info *devinfo, \
#define FF(name, hi4, lo4, hi45, lo45, hi5, lo5, hi6, lo6, \
hi7, lo7, hi8, lo8, hi12, lo12) \
static inline void \
brw_inst_set_##name(const struct gen_device_info *devinfo, \
brw_inst_set_##name(const struct intel_device_info *devinfo, \
brw_inst *inst, uint64_t value) \
{ \
BOUNDS(hi4, lo4, hi45, lo45, hi5, lo5, hi6, lo6, \
@ -115,7 +115,7 @@ brw_inst_set_##name(const struct gen_device_info *devinfo, \
brw_inst_set_bits(inst, high, low, value); \
} \
static inline uint64_t \
brw_inst_##name(const struct gen_device_info *devinfo, const brw_inst *inst) \
brw_inst_##name(const struct intel_device_info *devinfo, const brw_inst *inst) \
{ \
BOUNDS(hi4, lo4, hi45, lo45, hi5, lo5, hi6, lo6, \
hi7, lo7, hi8, lo8, hi12, lo12) \
@ -140,7 +140,7 @@ FF(name, \
#define FFDC(name, hi4, lo4, hi45, lo45, hi5, lo5, hi6, lo6, \
hi7, lo7, hi8, lo8, hi12ex, lo12ex, hi12, lo12, assertions) \
static inline void \
brw_inst_set_##name(const struct gen_device_info *devinfo, \
brw_inst_set_##name(const struct intel_device_info *devinfo, \
brw_inst *inst, uint64_t value) \
{ \
assert(assertions); \
@ -156,7 +156,7 @@ brw_inst_set_##name(const struct gen_device_info *devinfo, \
} \
} \
static inline uint64_t \
brw_inst_##name(const struct gen_device_info *devinfo, const brw_inst *inst) \
brw_inst_##name(const struct intel_device_info *devinfo, const brw_inst *inst) \
{ \
assert(assertions); \
if (devinfo->ver >= 12) { \
@ -190,7 +190,7 @@ brw_inst_##name(const struct gen_device_info *devinfo, const brw_inst *inst) \
*/
#define FI(name, hi4, lo4, hi8, lo8, hi12, lo12) \
static inline void \
brw_inst_set_##name(const struct gen_device_info *devinfo, \
brw_inst_set_##name(const struct intel_device_info *devinfo, \
brw_inst *inst, uint64_t value) \
{ \
if (devinfo->ver >= 12) { \
@ -204,7 +204,7 @@ brw_inst_set_##name(const struct gen_device_info *devinfo, \
} \
} \
static inline uint64_t \
brw_inst_##name(const struct gen_device_info *devinfo, const brw_inst *inst) \
brw_inst_##name(const struct intel_device_info *devinfo, const brw_inst *inst) \
{ \
if (devinfo->ver >= 12) { \
return (brw_inst_bits(inst, hi12, hi12) << 1) | \
@ -222,7 +222,7 @@ brw_inst_##name(const struct gen_device_info *devinfo, const brw_inst *inst) \
*/
#define FK(name, hi4, lo4, const12) \
static inline void \
brw_inst_set_##name(const struct gen_device_info *devinfo, \
brw_inst_set_##name(const struct intel_device_info *devinfo, \
brw_inst *inst, uint64_t v) \
{ \
if (devinfo->ver >= 12) \
@ -231,7 +231,7 @@ brw_inst_set_##name(const struct gen_device_info *devinfo, \
brw_inst_set_bits(inst, hi4, lo4, v); \
} \
static inline uint64_t \
brw_inst_##name(const struct gen_device_info *devinfo, \
brw_inst_##name(const struct intel_device_info *devinfo, \
const brw_inst *inst) \
{ \
if (devinfo->ver >= 12) \
@ -379,7 +379,7 @@ F(3src_hw_opcode, /* 4+ */ 6, 0, /* 12+ */ 6, 0)
#define REG_TYPE(reg) \
static inline void \
brw_inst_set_3src_a16_##reg##_type(const struct gen_device_info *devinfo, \
brw_inst_set_3src_a16_##reg##_type(const struct intel_device_info *devinfo, \
brw_inst *inst, enum brw_reg_type type) \
{ \
unsigned hw_type = brw_reg_type_to_a16_hw_3src_type(devinfo, type); \
@ -387,7 +387,7 @@ brw_inst_set_3src_a16_##reg##_type(const struct gen_device_info *devinfo, \
} \
\
static inline enum brw_reg_type \
brw_inst_3src_a16_##reg##_type(const struct gen_device_info *devinfo, \
brw_inst_3src_a16_##reg##_type(const struct intel_device_info *devinfo, \
const brw_inst *inst) \
{ \
unsigned hw_type = brw_inst_3src_a16_##reg##_hw_type(devinfo, inst); \
@ -441,7 +441,7 @@ FC(3src_a1_exec_type, /* 4+ */ 35, 35, /* 12+ */ 39, 39, devinfo->ver
#define REG_TYPE(reg) \
static inline void \
brw_inst_set_3src_a1_##reg##_type(const struct gen_device_info *devinfo, \
brw_inst_set_3src_a1_##reg##_type(const struct intel_device_info *devinfo, \
brw_inst *inst, enum brw_reg_type type) \
{ \
UNUSED enum gfx10_align1_3src_exec_type exec_type = \
@ -457,7 +457,7 @@ brw_inst_set_3src_a1_##reg##_type(const struct gen_device_info *devinfo, \
} \
\
static inline enum brw_reg_type \
brw_inst_3src_a1_##reg##_type(const struct gen_device_info *devinfo, \
brw_inst_3src_a1_##reg##_type(const struct intel_device_info *devinfo, \
const brw_inst *inst) \
{ \
enum gfx10_align1_3src_exec_type exec_type = \
@ -478,7 +478,7 @@ REG_TYPE(src2)
* @{
*/
static inline uint16_t
brw_inst_3src_a1_src0_imm(ASSERTED const struct gen_device_info *devinfo,
brw_inst_3src_a1_src0_imm(ASSERTED const struct intel_device_info *devinfo,
const brw_inst *insn)
{
assert(devinfo->ver >= 10);
@ -489,7 +489,7 @@ brw_inst_3src_a1_src0_imm(ASSERTED const struct gen_device_info *devinfo,
}
static inline uint16_t
brw_inst_3src_a1_src2_imm(ASSERTED const struct gen_device_info *devinfo,
brw_inst_3src_a1_src2_imm(ASSERTED const struct intel_device_info *devinfo,
const brw_inst *insn)
{
assert(devinfo->ver >= 10);
@ -500,7 +500,7 @@ brw_inst_3src_a1_src2_imm(ASSERTED const struct gen_device_info *devinfo,
}
static inline void
brw_inst_set_3src_a1_src0_imm(ASSERTED const struct gen_device_info *devinfo,
brw_inst_set_3src_a1_src0_imm(ASSERTED const struct intel_device_info *devinfo,
brw_inst *insn, uint16_t value)
{
assert(devinfo->ver >= 10);
@ -511,7 +511,7 @@ brw_inst_set_3src_a1_src0_imm(ASSERTED const struct gen_device_info *devinfo,
}
static inline void
brw_inst_set_3src_a1_src2_imm(ASSERTED const struct gen_device_info *devinfo,
brw_inst_set_3src_a1_src2_imm(ASSERTED const struct intel_device_info *devinfo,
brw_inst *insn, uint16_t value)
{
assert(devinfo->ver >= 10);
@ -527,7 +527,7 @@ brw_inst_set_3src_a1_src2_imm(ASSERTED const struct gen_device_info *devinfo,
* @{
*/
static inline void
brw_inst_set_uip(const struct gen_device_info *devinfo,
brw_inst_set_uip(const struct intel_device_info *devinfo,
brw_inst *inst, int32_t value)
{
assert(devinfo->ver >= 6);
@ -545,7 +545,7 @@ brw_inst_set_uip(const struct gen_device_info *devinfo,
}
static inline int32_t
brw_inst_uip(const struct gen_device_info *devinfo, const brw_inst *inst)
brw_inst_uip(const struct intel_device_info *devinfo, const brw_inst *inst)
{
assert(devinfo->ver >= 6);
@ -557,7 +557,7 @@ brw_inst_uip(const struct gen_device_info *devinfo, const brw_inst *inst)
}
static inline void
brw_inst_set_jip(const struct gen_device_info *devinfo,
brw_inst_set_jip(const struct intel_device_info *devinfo,
brw_inst *inst, int32_t value)
{
assert(devinfo->ver >= 6);
@ -575,7 +575,7 @@ brw_inst_set_jip(const struct gen_device_info *devinfo,
}
static inline int32_t
brw_inst_jip(const struct gen_device_info *devinfo, const brw_inst *inst)
brw_inst_jip(const struct intel_device_info *devinfo, const brw_inst *inst)
{
assert(devinfo->ver >= 6);
@ -589,14 +589,14 @@ brw_inst_jip(const struct gen_device_info *devinfo, const brw_inst *inst)
/** Like FC, but using int16_t to handle negative jump targets. */
#define FJ(name, high, low, assertions) \
static inline void \
brw_inst_set_##name(const struct gen_device_info *devinfo, brw_inst *inst, int16_t v) \
brw_inst_set_##name(const struct intel_device_info *devinfo, brw_inst *inst, int16_t v) \
{ \
assert(assertions); \
(void) devinfo; \
brw_inst_set_bits(inst, high, low, (uint16_t) v); \
} \
static inline int16_t \
brw_inst_##name(const struct gen_device_info *devinfo, const brw_inst *inst) \
brw_inst_##name(const struct intel_device_info *devinfo, const brw_inst *inst) \
{ \
assert(assertions); \
(void) devinfo; \
@ -640,7 +640,7 @@ FC(send_dst_reg_file, /* 4+ */ 35, 35, /* 12+ */ 50, 50, devinfo->ver
* separately.
*/
static inline void
brw_inst_set_send_desc(const struct gen_device_info *devinfo,
brw_inst_set_send_desc(const struct intel_device_info *devinfo,
brw_inst *inst, uint32_t value)
{
if (devinfo->ver >= 12) {
@ -667,7 +667,7 @@ brw_inst_set_send_desc(const struct gen_device_info *devinfo,
* \sa brw_inst_set_send_desc().
*/
static inline uint32_t
brw_inst_send_desc(const struct gen_device_info *devinfo, const brw_inst *inst)
brw_inst_send_desc(const struct intel_device_info *devinfo, const brw_inst *inst)
{
if (devinfo->ver >= 12) {
return (brw_inst_bits(inst, 123, 122) << 30 |
@ -694,7 +694,7 @@ brw_inst_send_desc(const struct gen_device_info *devinfo, const brw_inst *inst)
* separately.
*/
static inline void
brw_inst_set_send_ex_desc(const struct gen_device_info *devinfo,
brw_inst_set_send_ex_desc(const struct intel_device_info *devinfo,
brw_inst *inst, uint32_t value)
{
if (devinfo->ver >= 12) {
@ -724,7 +724,7 @@ brw_inst_set_send_ex_desc(const struct gen_device_info *devinfo,
* separately.
*/
static inline void
brw_inst_set_sends_ex_desc(const struct gen_device_info *devinfo,
brw_inst_set_sends_ex_desc(const struct intel_device_info *devinfo,
brw_inst *inst, uint32_t value)
{
if (devinfo->ver >= 12) {
@ -743,7 +743,7 @@ brw_inst_set_sends_ex_desc(const struct gen_device_info *devinfo,
* \sa brw_inst_set_send_ex_desc().
*/
static inline uint32_t
brw_inst_send_ex_desc(const struct gen_device_info *devinfo,
brw_inst_send_ex_desc(const struct intel_device_info *devinfo,
const brw_inst *inst)
{
if (devinfo->ver >= 12) {
@ -767,7 +767,7 @@ brw_inst_send_ex_desc(const struct gen_device_info *devinfo,
* \sa brw_inst_set_send_ex_desc().
*/
static inline uint32_t
brw_inst_sends_ex_desc(const struct gen_device_info *devinfo,
brw_inst_sends_ex_desc(const struct intel_device_info *devinfo,
const brw_inst *inst)
{
if (devinfo->ver >= 12) {
@ -1052,21 +1052,21 @@ F(pi_message_data, /* 4+ */ MD(7), MD(0), /* 12+ */ MD12(7), MD12(0))
* @{
*/
static inline int
brw_inst_imm_d(const struct gen_device_info *devinfo, const brw_inst *insn)
brw_inst_imm_d(const struct intel_device_info *devinfo, const brw_inst *insn)
{
(void) devinfo;
return brw_inst_bits(insn, 127, 96);
}
static inline unsigned
brw_inst_imm_ud(const struct gen_device_info *devinfo, const brw_inst *insn)
brw_inst_imm_ud(const struct intel_device_info *devinfo, const brw_inst *insn)
{
(void) devinfo;
return brw_inst_bits(insn, 127, 96);
}
static inline uint64_t
brw_inst_imm_uq(ASSERTED const struct gen_device_info *devinfo,
brw_inst_imm_uq(ASSERTED const struct intel_device_info *devinfo,
const brw_inst *insn)
{
assert(devinfo->ver >= 8);
@ -1074,7 +1074,7 @@ brw_inst_imm_uq(ASSERTED const struct gen_device_info *devinfo,
}
static inline float
brw_inst_imm_f(const struct gen_device_info *devinfo, const brw_inst *insn)
brw_inst_imm_f(const struct intel_device_info *devinfo, const brw_inst *insn)
{
union {
float f;
@ -1086,7 +1086,7 @@ brw_inst_imm_f(const struct gen_device_info *devinfo, const brw_inst *insn)
}
static inline double
brw_inst_imm_df(const struct gen_device_info *devinfo, const brw_inst *insn)
brw_inst_imm_df(const struct intel_device_info *devinfo, const brw_inst *insn)
{
union {
double d;
@ -1098,7 +1098,7 @@ brw_inst_imm_df(const struct gen_device_info *devinfo, const brw_inst *insn)
}
static inline void
brw_inst_set_imm_d(const struct gen_device_info *devinfo,
brw_inst_set_imm_d(const struct intel_device_info *devinfo,
brw_inst *insn, int value)
{
(void) devinfo;
@ -1106,7 +1106,7 @@ brw_inst_set_imm_d(const struct gen_device_info *devinfo,
}
static inline void
brw_inst_set_imm_ud(const struct gen_device_info *devinfo,
brw_inst_set_imm_ud(const struct intel_device_info *devinfo,
brw_inst *insn, unsigned value)
{
(void) devinfo;
@ -1114,7 +1114,7 @@ brw_inst_set_imm_ud(const struct gen_device_info *devinfo,
}
static inline void
brw_inst_set_imm_f(const struct gen_device_info *devinfo,
brw_inst_set_imm_f(const struct intel_device_info *devinfo,
brw_inst *insn, float value)
{
union {
@ -1127,7 +1127,7 @@ brw_inst_set_imm_f(const struct gen_device_info *devinfo,
}
static inline void
brw_inst_set_imm_df(const struct gen_device_info *devinfo,
brw_inst_set_imm_df(const struct intel_device_info *devinfo,
brw_inst *insn, double value)
{
union {
@ -1146,7 +1146,7 @@ brw_inst_set_imm_df(const struct gen_device_info *devinfo,
}
static inline void
brw_inst_set_imm_uq(const struct gen_device_info *devinfo,
brw_inst_set_imm_uq(const struct intel_device_info *devinfo,
brw_inst *insn, uint64_t value)
{
(void) devinfo;
@ -1162,7 +1162,7 @@ brw_inst_set_imm_uq(const struct gen_device_info *devinfo,
#define REG_TYPE(reg) \
static inline void \
brw_inst_set_##reg##_file_type(const struct gen_device_info *devinfo, \
brw_inst_set_##reg##_file_type(const struct intel_device_info *devinfo, \
brw_inst *inst, enum brw_reg_file file, \
enum brw_reg_type type) \
{ \
@ -1173,7 +1173,7 @@ brw_inst_set_##reg##_file_type(const struct gen_device_info *devinfo, \
} \
\
static inline enum brw_reg_type \
brw_inst_##reg##_type(const struct gen_device_info *devinfo, \
brw_inst_##reg##_type(const struct intel_device_info *devinfo, \
const brw_inst *inst) \
{ \
unsigned file = __builtin_strcmp("dst", #reg) == 0 ? \
@ -1193,7 +1193,7 @@ REG_TYPE(src1)
#define BRW_IA1_ADDR_IMM(reg, g4_high, g4_low, g8_nine, g8_high, g8_low, \
g12_high, g12_low) \
static inline void \
brw_inst_set_##reg##_ia1_addr_imm(const struct gen_device_info *devinfo, \
brw_inst_set_##reg##_ia1_addr_imm(const struct intel_device_info *devinfo, \
brw_inst *inst, \
unsigned value) \
{ \
@ -1208,7 +1208,7 @@ brw_inst_set_##reg##_ia1_addr_imm(const struct gen_device_info *devinfo, \
} \
} \
static inline unsigned \
brw_inst_##reg##_ia1_addr_imm(const struct gen_device_info *devinfo, \
brw_inst_##reg##_ia1_addr_imm(const struct intel_device_info *devinfo, \
const brw_inst *inst) \
{ \
if (devinfo->ver >= 12) { \
@ -1229,7 +1229,7 @@ BRW_IA1_ADDR_IMM(dst, 57, 48, 47, 56, 48, 59, 50)
#define BRW_IA16_ADDR_IMM(reg, g4_high, g4_low, g8_nine, g8_high, g8_low) \
static inline void \
brw_inst_set_##reg##_ia16_addr_imm(const struct gen_device_info *devinfo, \
brw_inst_set_##reg##_ia16_addr_imm(const struct intel_device_info *devinfo, \
brw_inst *inst, unsigned value) \
{ \
assert(devinfo->ver < 12); \
@ -1243,7 +1243,7 @@ brw_inst_set_##reg##_ia16_addr_imm(const struct gen_device_info *devinfo, \
} \
} \
static inline unsigned \
brw_inst_##reg##_ia16_addr_imm(const struct gen_device_info *devinfo, \
brw_inst_##reg##_ia16_addr_imm(const struct intel_device_info *devinfo, \
const brw_inst *inst) \
{ \
assert(devinfo->ver < 12); \
@ -1356,7 +1356,7 @@ brw_compact_inst_set_bits(brw_compact_inst *inst, unsigned high, unsigned low,
#define FC(name, high, low, gfx12_high, gfx12_low, assertions) \
static inline void \
brw_compact_inst_set_##name(const struct gen_device_info *devinfo, \
brw_compact_inst_set_##name(const struct intel_device_info *devinfo, \
brw_compact_inst *inst, unsigned v) \
{ \
assert(assertions); \
@ -1366,7 +1366,7 @@ brw_compact_inst_set_##name(const struct gen_device_info *devinfo, \
brw_compact_inst_set_bits(inst, high, low, v); \
} \
static inline unsigned \
brw_compact_inst_##name(const struct gen_device_info *devinfo, \
brw_compact_inst_##name(const struct intel_device_info *devinfo, \
const brw_compact_inst *inst) \
{ \
assert(assertions); \
@ -1400,7 +1400,7 @@ F(debug_control, /* 4+ */ 7, 7, /* 12+ */ 7, 7)
F(hw_opcode, /* 4+ */ 6, 0, /* 12+ */ 6, 0) /* Same location as brw_inst */
static inline unsigned
brw_compact_inst_imm(const struct gen_device_info *devinfo,
brw_compact_inst_imm(const struct intel_device_info *devinfo,
const brw_compact_inst *inst)
{
if (devinfo->ver >= 12) {

4
src/intel/compiler/brw_ir.h
View file

@ -90,7 +90,7 @@ struct backend_reg : private brw_reg
struct bblock_t;
struct backend_instruction : public exec_node {
bool is_3src(const struct gen_device_info *devinfo) const;
bool is_3src(const struct intel_device_info *devinfo) const;
bool is_tex() const;
bool is_math() const;
bool is_control_flow() const;
@ -99,7 +99,7 @@ struct backend_instruction : public exec_node {
bool can_do_saturate() const;
bool can_do_cmod() const;
bool reads_accumulator_implicitly() const;
bool writes_accumulator_implicitly(const struct gen_device_info *devinfo) const;
bool writes_accumulator_implicitly(const struct intel_device_info *devinfo) const;
/**
* Instructions that use indirect addressing have additional register

12
src/intel/compiler/brw_ir_fs.h
View file

@ -355,7 +355,7 @@ public:
bool is_partial_write() const;
unsigned components_read(unsigned i) const;
unsigned size_read(int arg) const;
bool can_do_source_mods(const struct gen_device_info *devinfo) const;
bool can_do_source_mods(const struct intel_device_info *devinfo) const;
bool can_do_cmod();
bool can_change_types() const;
bool has_source_and_destination_hazard() const;
@ -372,7 +372,7 @@ public:
* Return the subset of flag registers read by the instruction as a bitset
* with byte granularity.
*/
unsigned flags_read(const gen_device_info *devinfo) const;
unsigned flags_read(const intel_device_info *devinfo) const;
/**
* Return the subset of flag registers updated by the instruction (either
@ -552,7 +552,7 @@ is_unordered(const fs_inst *inst)
* scalar source."
*/
static inline bool
has_dst_aligned_region_restriction(const gen_device_info *devinfo,
has_dst_aligned_region_restriction(const intel_device_info *devinfo,
const fs_inst *inst,
brw_reg_type dst_type)
{
@ -570,7 +570,7 @@ has_dst_aligned_region_restriction(const gen_device_info *devinfo,
if (type_sz(dst_type) > 4 || type_sz(exec_type) > 4 ||
(type_sz(exec_type) == 4 && is_dword_multiply))
return devinfo->is_cherryview || gen_device_info_is_9lp(devinfo) ||
return devinfo->is_cherryview || intel_device_info_is_9lp(devinfo) ||
devinfo->verx10 >= 125;
else if (brw_reg_type_is_floating_point(inst->dst.type))
@ -581,7 +581,7 @@ has_dst_aligned_region_restriction(const gen_device_info *devinfo,
}
static inline bool
has_dst_aligned_region_restriction(const gen_device_info *devinfo,
has_dst_aligned_region_restriction(const intel_device_info *devinfo,
const fs_inst *inst)
{
return has_dst_aligned_region_restriction(devinfo, inst, inst->dst.type);
@ -687,6 +687,6 @@ is_coalescing_payload(const brw::simple_allocator &alloc, const fs_inst *inst)
}
bool
has_bank_conflict(const gen_device_info *devinfo, const fs_inst *inst);
has_bank_conflict(const intel_device_info *devinfo, const fs_inst *inst);
#endif

18
src/intel/compiler/brw_ir_performance.cpp
View file

@ -120,7 +120,7 @@ namespace {
* instructions.
*/
struct instruction_info {
instruction_info(const gen_device_info *devinfo, const fs_inst *inst) :
instruction_info(const intel_device_info *devinfo, const fs_inst *inst) :
devinfo(devinfo), op(inst->opcode),
td(inst->dst.type), sd(DIV_ROUND_UP(inst->size_written, REG_SIZE)),
tx(get_exec_type(inst)), sx(0), ss(0),
@ -150,7 +150,7 @@ namespace {
tx = brw_int_type(8, tx == BRW_REGISTER_TYPE_D);
}
instruction_info(const gen_device_info *devinfo,
instruction_info(const intel_device_info *devinfo,
const vec4_instruction *inst) :
devinfo(devinfo), op(inst->opcode),
td(inst->dst.type), sd(DIV_ROUND_UP(inst->size_written, REG_SIZE)),
@ -174,7 +174,7 @@ namespace {
}
/** Device information. */
const struct gen_device_info *devinfo;
const struct intel_device_info *devinfo;
/** Instruction opcode. */
opcode op;
/** Destination type. */
@ -289,7 +289,7 @@ namespace {
const perf_desc
instruction_desc(const instruction_info &info)
{
const struct gen_device_info *devinfo = info.devinfo;
const struct intel_device_info *devinfo = info.devinfo;
switch (info.op) {
case BRW_OPCODE_SYNC:
@ -1176,7 +1176,7 @@ namespace {
* Return the dependency ID of a backend_reg, offset by \p delta GRFs.
*/
dependency_id
reg_dependency_id(const gen_device_info *devinfo, const backend_reg &r,
reg_dependency_id(const intel_device_info *devinfo, const backend_reg &r,
const int delta)
{
if (r.file == VGRF) {
@ -1262,7 +1262,7 @@ namespace {
* instruction.
*/
unsigned
accum_reg_of_channel(const gen_device_info *devinfo,
accum_reg_of_channel(const intel_device_info *devinfo,
const backend_instruction *inst,
brw_reg_type tx, unsigned i)
{
@ -1277,7 +1277,7 @@ namespace {
* Model the performance behavior of an FS back-end instruction.
*/
void
issue_fs_inst(state &st, const gen_device_info *devinfo,
issue_fs_inst(state &st, const intel_device_info *devinfo,
const backend_instruction *be_inst)
{
const fs_inst *inst = static_cast<const fs_inst *>(be_inst);
@ -1397,7 +1397,7 @@ namespace {
* Model the performance behavior of a VEC4 back-end instruction.
*/
void
issue_vec4_instruction(state &st, const gen_device_info *devinfo,
issue_vec4_instruction(state &st, const intel_device_info *devinfo,
const backend_instruction *be_inst)
{
const vec4_instruction *inst =
@ -1508,7 +1508,7 @@ namespace {
void
calculate_performance(performance &p, const backend_shader *s,
void (*issue_instruction)(
state &, const gen_device_info *,
state &, const intel_device_info *,
const backend_instruction *),
unsigned dispatch_width)
{

6
src/intel/compiler/brw_ir_vec4.h
View file

@ -287,12 +287,12 @@ public:
bool is_send_from_grf() const;
unsigned size_read(unsigned arg) const;
bool can_reswizzle(const struct gen_device_info *devinfo, int dst_writemask,
bool can_reswizzle(const struct intel_device_info *devinfo, int dst_writemask,
int swizzle, int swizzle_mask);
void reswizzle(int dst_writemask, int swizzle);
bool can_do_source_mods(const struct gen_device_info *devinfo);
bool can_do_source_mods(const struct intel_device_info *devinfo);
bool can_do_cmod();
bool can_do_writemask(const struct gen_device_info *devinfo);
bool can_do_writemask(const struct intel_device_info *devinfo);
bool can_change_types() const;
bool has_source_and_destination_hazard() const;
unsigned implied_mrf_writes() const;

16
src/intel/compiler/brw_nir.c
View file

@ -404,7 +404,7 @@ lower_barycentric_at_offset(nir_builder *b, nir_instr *instr, void *data)
void
brw_nir_lower_fs_inputs(nir_shader *nir,
const struct gen_device_info *devinfo,
const struct intel_device_info *devinfo,
const struct brw_wm_prog_key *key)
{
nir_foreach_shader_in_variable(var, nir) {
@ -515,7 +515,7 @@ static nir_variable_mode
brw_nir_no_indirect_mask(const struct brw_compiler *compiler,
gl_shader_stage stage)
{
const struct gen_device_info *devinfo = compiler->devinfo;
const struct intel_device_info *devinfo = compiler->devinfo;
const bool is_scalar = compiler->scalar_stage[stage];
nir_variable_mode indirect_mask = 0;
@ -679,7 +679,7 @@ static unsigned
lower_bit_size_callback(const nir_instr *instr, UNUSED void *data)
{
const struct brw_compiler *compiler = (const struct brw_compiler *) data;
const struct gen_device_info *devinfo = compiler->devinfo;
const struct intel_device_info *devinfo = compiler->devinfo;
switch (instr->type) {
case nir_instr_type_alu: {
@ -795,7 +795,7 @@ void
brw_preprocess_nir(const struct brw_compiler *compiler, nir_shader *nir,
const nir_shader *softfp64)
{
const struct gen_device_info *devinfo = compiler->devinfo;
const struct intel_device_info *devinfo = compiler->devinfo;
UNUSED bool progress; /* Written by OPT */
const bool is_scalar = compiler->scalar_stage[nir->info.stage];
@ -1031,7 +1031,7 @@ brw_vectorize_lower_mem_access(nir_shader *nir,
bool is_scalar,
bool robust_buffer_access)
{
const struct gen_device_info *devinfo = compiler->devinfo;
const struct intel_device_info *devinfo = compiler->devinfo;
bool progress = false;
if (is_scalar) {
@ -1087,7 +1087,7 @@ brw_postprocess_nir(nir_shader *nir, const struct brw_compiler *compiler,
bool is_scalar, bool debug_enabled,
bool robust_buffer_access)
{
const struct gen_device_info *devinfo = compiler->devinfo;
const struct intel_device_info *devinfo = compiler->devinfo;
UNUSED bool progress; /* Written by OPT */
@ -1236,7 +1236,7 @@ brw_nir_apply_sampler_key(nir_shader *nir,
const struct brw_compiler *compiler,
const struct brw_sampler_prog_key_data *key_tex)
{
const struct gen_device_info *devinfo = compiler->devinfo;
const struct intel_device_info *devinfo = compiler->devinfo;
nir_lower_tex_options tex_options = {
.lower_txd_clamp_bindless_sampler = true,
.lower_txd_clamp_if_sampler_index_not_lt_16 = true,
@ -1468,7 +1468,7 @@ brw_aop_for_nir_intrinsic(const nir_intrinsic_instr *atomic)
}
enum brw_reg_type
brw_type_for_nir_type(const struct gen_device_info *devinfo, nir_alu_type type)
brw_type_for_nir_type(const struct intel_device_info *devinfo, nir_alu_type type)
{
switch (type) {
case nir_type_uint:

10
src/intel/compiler/brw_nir.h
View file

@ -110,7 +110,7 @@ void brw_nir_lower_vue_inputs(nir_shader *nir,
const struct brw_vue_map *vue_map);
void brw_nir_lower_tes_inputs(nir_shader *nir, const struct brw_vue_map *vue);
void brw_nir_lower_fs_inputs(nir_shader *nir,
const struct gen_device_info *devinfo,
const struct intel_device_info *devinfo,
const struct brw_wm_prog_key *key);
void brw_nir_lower_vue_outputs(nir_shader *nir);
void brw_nir_lower_tcs_outputs(nir_shader *nir, const struct brw_vue_map *vue,
@ -122,7 +122,7 @@ bool brw_nir_lower_conversions(nir_shader *nir);
bool brw_nir_lower_scoped_barriers(nir_shader *nir);
bool brw_nir_lower_image_load_store(nir_shader *nir,
const struct gen_device_info *devinfo,
const struct intel_device_info *devinfo,
bool *uses_atomic_load_store);
void brw_nir_rewrite_image_intrinsic(nir_intrinsic_instr *intrin,
nir_ssa_def *index);
@ -130,7 +130,7 @@ void brw_nir_rewrite_bindless_image_intrinsic(nir_intrinsic_instr *intrin,
nir_ssa_def *handle);
bool brw_nir_lower_mem_access_bit_sizes(nir_shader *shader,
const struct gen_device_info *devinfo);
const struct intel_device_info *devinfo);
void brw_postprocess_nir(nir_shader *nir,
const struct brw_compiler *compiler,
@ -155,7 +155,7 @@ void brw_nir_apply_key(nir_shader *nir,
enum brw_conditional_mod brw_cmod_for_nir_comparison(nir_op op);
uint32_t brw_aop_for_nir_intrinsic(const nir_intrinsic_instr *atomic);
enum brw_reg_type brw_type_for_nir_type(const struct gen_device_info *devinfo,
enum brw_reg_type brw_type_for_nir_type(const struct intel_device_info *devinfo,
nir_alu_type type);
void brw_nir_setup_glsl_uniforms(void *mem_ctx, nir_shader *shader,
@ -195,7 +195,7 @@ nir_shader *brw_nir_create_passthrough_tcs(void *mem_ctx,
bool brw_nir_move_interpolation_to_top(nir_shader *nir);
bool brw_nir_demote_sample_qualifiers(nir_shader *nir);
void brw_nir_populate_wm_prog_data(const nir_shader *shader,
const struct gen_device_info *devinfo,
const struct intel_device_info *devinfo,
const struct brw_wm_prog_key *key,
struct brw_wm_prog_data *prog_data);

2
src/intel/compiler/brw_nir_analyze_ubo_ranges.c
View file

@ -200,7 +200,7 @@ brw_nir_analyze_ubo_ranges(const struct brw_compiler *compiler,
const struct brw_vs_prog_key *vs_key,
struct brw_ubo_range out_ranges[4])
{
const struct gen_device_info *devinfo = compiler->devinfo;
const struct intel_device_info *devinfo = compiler->devinfo;
if ((devinfo->ver <= 7 && !devinfo->is_haswell) ||
!compiler->scalar_stage[nir->info.stage]) {

16
src/intel/compiler/brw_nir_lower_image_load_store.c
View file

@ -89,7 +89,7 @@ image_coord_is_in_bounds(nir_builder *b, nir_deref_instr *deref,
* the hardware tiling format.
*/
static nir_ssa_def *
image_address(nir_builder *b, const struct gen_device_info *devinfo,
image_address(nir_builder *b, const struct intel_device_info *devinfo,
nir_deref_instr *deref, nir_ssa_def *coord)
{
if (glsl_get_sampler_dim(deref->type) == GLSL_SAMPLER_DIM_1D &&
@ -259,7 +259,7 @@ get_format_info(enum isl_format fmt)
}
static nir_ssa_def *
convert_color_for_load(nir_builder *b, const struct gen_device_info *devinfo,
convert_color_for_load(nir_builder *b, const struct intel_device_info *devinfo,
nir_ssa_def *color,
enum isl_format image_fmt, enum isl_format lower_fmt,
unsigned dest_components)
@ -362,7 +362,7 @@ expand_vec:
static bool
lower_image_load_instr(nir_builder *b,
const struct gen_device_info *devinfo,
const struct intel_device_info *devinfo,
nir_intrinsic_instr *intrin)
{
nir_deref_instr *deref = nir_src_as_deref(intrin->src[0]);
@ -446,7 +446,7 @@ lower_image_load_instr(nir_builder *b,
}
static nir_ssa_def *
convert_color_for_store(nir_builder *b, const struct gen_device_info *devinfo,
convert_color_for_store(nir_builder *b, const struct intel_device_info *devinfo,
nir_ssa_def *color,
enum isl_format image_fmt, enum isl_format lower_fmt)
{
@ -514,7 +514,7 @@ convert_color_for_store(nir_builder *b, const struct gen_device_info *devinfo,
static bool
lower_image_store_instr(nir_builder *b,
const struct gen_device_info *devinfo,
const struct intel_device_info *devinfo,
nir_intrinsic_instr *intrin)
{
nir_deref_instr *deref = nir_src_as_deref(intrin->src[0]);
@ -592,7 +592,7 @@ lower_image_store_instr(nir_builder *b,
static bool
lower_image_atomic_instr(nir_builder *b,
const struct gen_device_info *devinfo,
const struct intel_device_info *devinfo,
nir_intrinsic_instr *intrin)
{
if (devinfo->is_haswell || devinfo->ver >= 8)
@ -627,7 +627,7 @@ lower_image_atomic_instr(nir_builder *b,
static bool
lower_image_size_instr(nir_builder *b,
const struct gen_device_info *devinfo,
const struct intel_device_info *devinfo,
nir_intrinsic_instr *intrin)
{
nir_deref_instr *deref = nir_src_as_deref(intrin->src[0]);
@ -676,7 +676,7 @@ lower_image_size_instr(nir_builder *b,
bool
brw_nir_lower_image_load_store(nir_shader *shader,
const struct gen_device_info *devinfo,
const struct intel_device_info *devinfo,
bool *uses_atomic_load_store)
{
bool progress = false;

2
src/intel/compiler/brw_nir_lower_intersection_shader.c
View file

@ -130,7 +130,7 @@ lower_any_hit_for_intersection(nir_shader *any_hit)
void
brw_nir_lower_intersection_shader(nir_shader *intersection,
const nir_shader *any_hit,
const struct gen_device_info *devinfo)
const struct intel_device_info *devinfo)
{
void *dead_ctx = ralloc_context(intersection);

8
src/intel/compiler/brw_nir_lower_mem_access_bit_sizes.c
View file

@ -78,7 +78,7 @@ dup_mem_intrinsic(nir_builder *b, nir_intrinsic_instr *intrin,
static bool
lower_mem_load_bit_size(nir_builder *b, nir_intrinsic_instr *intrin,
const struct gen_device_info *devinfo)
const struct intel_device_info *devinfo)
{
const bool needs_scalar =
intrin->intrinsic == nir_intrinsic_load_scratch;
@ -152,7 +152,7 @@ lower_mem_load_bit_size(nir_builder *b, nir_intrinsic_instr *intrin,
static bool
lower_mem_store_bit_size(nir_builder *b, nir_intrinsic_instr *intrin,
const struct gen_device_info *devinfo)
const struct intel_device_info *devinfo)
{
const bool needs_scalar =
intrin->intrinsic == nir_intrinsic_store_scratch;
@ -239,7 +239,7 @@ lower_mem_store_bit_size(nir_builder *b, nir_intrinsic_instr *intrin,
static bool
lower_mem_access_bit_sizes_impl(nir_function_impl *impl,
const struct gen_device_info *devinfo)
const struct intel_device_info *devinfo)
{
bool progress = false;
@ -312,7 +312,7 @@ lower_mem_access_bit_sizes_impl(nir_function_impl *impl,
*/
bool
brw_nir_lower_mem_access_bit_sizes(nir_shader *shader,
const struct gen_device_info *devinfo)
const struct intel_device_info *devinfo)
{
bool progress = false;

4
src/intel/compiler/brw_nir_lower_rt_intrinsics.c
View file

@ -46,7 +46,7 @@ build_leaf_is_procedural(nir_builder *b, struct brw_nir_rt_mem_hit_defs *hit)
static void
lower_rt_intrinsics_impl(nir_function_impl *impl,
const struct gen_device_info *devinfo)
const struct intel_device_info *devinfo)
{
nir_builder build;
nir_builder_init(&build, impl);
@ -400,7 +400,7 @@ lower_rt_intrinsics_impl(nir_function_impl *impl,
*/
void
brw_nir_lower_rt_intrinsics(nir_shader *nir,
const struct gen_device_info *devinfo)
const struct intel_device_info *devinfo)
{
nir_foreach_function(function, nir) {
if (function->impl)

8
src/intel/compiler/brw_nir_rt.c
View file

@ -266,7 +266,7 @@ build_terminate_ray(nir_builder *b)
*/
static bool
lower_ray_walk_intrinsics(nir_shader *shader,
const struct gen_device_info *devinfo)
const struct intel_device_info *devinfo)
{
assert(shader->info.stage == MESA_SHADER_ANY_HIT ||
shader->info.stage == MESA_SHADER_INTERSECTION);
@ -352,7 +352,7 @@ brw_nir_lower_raygen(nir_shader *nir)
}
void
brw_nir_lower_any_hit(nir_shader *nir, const struct gen_device_info *devinfo)
brw_nir_lower_any_hit(nir_shader *nir, const struct intel_device_info *devinfo)
{
assert(nir->info.stage == MESA_SHADER_ANY_HIT);
NIR_PASS_V(nir, brw_nir_lower_shader_returns);
@ -387,7 +387,7 @@ brw_nir_lower_callable(nir_shader *nir)
void
brw_nir_lower_combined_intersection_any_hit(nir_shader *intersection,
const nir_shader *any_hit,
const struct gen_device_info *devinfo)
const struct intel_device_info *devinfo)
{
assert(intersection->info.stage == MESA_SHADER_INTERSECTION);
assert(any_hit == NULL || any_hit->info.stage == MESA_SHADER_ANY_HIT);
@ -415,7 +415,7 @@ nir_shader *
brw_nir_create_raygen_trampoline(const struct brw_compiler *compiler,
void *mem_ctx)
{
const struct gen_device_info *devinfo = compiler->devinfo;
const struct intel_device_info *devinfo = compiler->devinfo;
const nir_shader_compiler_options *nir_options =
compiler->glsl_compiler_options[MESA_SHADER_COMPUTE].NirOptions;

8
src/intel/compiler/brw_nir_rt.h
View file

@ -33,13 +33,13 @@ extern "C" {
void brw_nir_lower_raygen(nir_shader *nir);
void brw_nir_lower_any_hit(nir_shader *nir,
const struct gen_device_info *devinfo);
const struct intel_device_info *devinfo);
void brw_nir_lower_closest_hit(nir_shader *nir);
void brw_nir_lower_miss(nir_shader *nir);
void brw_nir_lower_callable(nir_shader *nir);
void brw_nir_lower_combined_intersection_any_hit(nir_shader *intersection,
const nir_shader *any_hit,
const struct gen_device_info *devinfo);
const struct intel_device_info *devinfo);
/* We reserve the first 16B of the stack for callee data pointers */
#define BRW_BTD_STACK_RESUME_BSR_ADDR_OFFSET 0
@ -58,10 +58,10 @@ bool brw_nir_lower_shader_calls(nir_shader *shader,
void *mem_ctx);
void brw_nir_lower_rt_intrinsics(nir_shader *shader,
const struct gen_device_info *devinfo);
const struct intel_device_info *devinfo);
void brw_nir_lower_intersection_shader(nir_shader *intersection,
const nir_shader *any_hit,
const struct gen_device_info *devinfo);
const struct intel_device_info *devinfo);
nir_shader *
brw_nir_create_raygen_trampoline(const struct brw_compiler *compiler,

8
src/intel/compiler/brw_nir_rt_builder.h
View file

@ -93,10 +93,10 @@ assert_def_size(nir_ssa_def *def, unsigned num_components, unsigned bit_size)
static inline nir_ssa_def *
brw_nir_num_rt_stacks(nir_builder *b,
const struct gen_device_info *devinfo)
const struct intel_device_info *devinfo)
{
return nir_imul_imm(b, nir_load_ray_num_dss_rt_stacks_intel(b),
gen_device_info_num_dual_subslices(devinfo));
intel_device_info_num_dual_subslices(devinfo));
}
static inline nir_ssa_def *
@ -109,7 +109,7 @@ brw_nir_rt_stack_id(nir_builder *b)
static inline nir_ssa_def *
brw_nir_rt_sw_hotzone_addr(nir_builder *b,
const struct gen_device_info *devinfo)
const struct intel_device_info *devinfo)
{
nir_ssa_def *offset32 =
nir_imul_imm(b, brw_nir_rt_stack_id(b), BRW_RT_SIZEOF_HOTZONE);
@ -175,7 +175,7 @@ brw_nir_rt_mem_ray_addr(nir_builder *b,
static inline nir_ssa_def *
brw_nir_rt_sw_stack_addr(nir_builder *b,
const struct gen_device_info *devinfo)
const struct intel_device_info *devinfo)
{
nir_ssa_def *addr = nir_load_ray_base_mem_addr_intel(b);

2
src/intel/compiler/brw_reg.h
View file

@ -53,7 +53,7 @@
extern "C" {
#endif
struct gen_device_info;
struct intel_device_info;
/** Number of general purpose registers (VS, WM, etc) */
#define BRW_MAX_GRF 128

12
src/intel/compiler/brw_reg_type.c
View file

@ -320,7 +320,7 @@ static const struct hw_3src_type {
* The hardware encoding may depend on whether the value is an immediate.
*/
unsigned
brw_reg_type_to_hw_type(const struct gen_device_info *devinfo,
brw_reg_type_to_hw_type(const struct intel_device_info *devinfo,
enum brw_reg_file file,
enum brw_reg_type type)
{
@ -364,7 +364,7 @@ brw_reg_type_to_hw_type(const struct gen_device_info *devinfo,
* The hardware encoding may depend on whether the value is an immediate.
*/
enum brw_reg_type
brw_hw_type_to_reg_type(const struct gen_device_info *devinfo,
brw_hw_type_to_reg_type(const struct intel_device_info *devinfo,
enum brw_reg_file file, unsigned hw_type)
{
const struct hw_type *table;
@ -406,7 +406,7 @@ brw_hw_type_to_reg_type(const struct gen_device_info *devinfo,
* for a 3-src align16 instruction
*/
unsigned
brw_reg_type_to_a16_hw_3src_type(const struct gen_device_info *devinfo,
brw_reg_type_to_a16_hw_3src_type(const struct intel_device_info *devinfo,
enum brw_reg_type type)
{
const struct hw_3src_type *table;
@ -431,7 +431,7 @@ brw_reg_type_to_a16_hw_3src_type(const struct gen_device_info *devinfo,
* for a 3-src align1 instruction
*/
unsigned
brw_reg_type_to_a1_hw_3src_type(const struct gen_device_info *devinfo,
brw_reg_type_to_a1_hw_3src_type(const struct intel_device_info *devinfo,
enum brw_reg_type type)
{
if (devinfo->verx10 >= 125) {
@ -454,7 +454,7 @@ brw_reg_type_to_a1_hw_3src_type(const struct gen_device_info *devinfo,
* brw_reg_type enumeration value.
*/
enum brw_reg_type
brw_a16_hw_3src_type_to_reg_type(const struct gen_device_info *devinfo,
brw_a16_hw_3src_type_to_reg_type(const struct intel_device_info *devinfo,
unsigned hw_type)
{
const struct hw_3src_type *table = NULL;
@ -480,7 +480,7 @@ brw_a16_hw_3src_type_to_reg_type(const struct gen_device_info *devinfo,
* brw_reg_type enumeration value.
*/
enum brw_reg_type
brw_a1_hw_3src_type_to_reg_type(const struct gen_device_info *devinfo,
brw_a1_hw_3src_type_to_reg_type(const struct intel_device_info *devinfo,
unsigned hw_type, unsigned exec_type)
{
const struct hw_3src_type *table =

14
src/intel/compiler/brw_reg_type.h
View file

@ -37,7 +37,7 @@ extern "C" {
#endif
enum brw_reg_file;
struct gen_device_info;
struct intel_device_info;
/*
* The ordering has been chosen so that no enum value is the same as a
@ -164,27 +164,27 @@ brw_reg_type_from_bit_size(unsigned bit_size,
#define INVALID_HW_REG_TYPE ((unsigned)-1)
unsigned
brw_reg_type_to_hw_type(const struct gen_device_info *devinfo,
brw_reg_type_to_hw_type(const struct intel_device_info *devinfo,
enum brw_reg_file file, enum brw_reg_type type);
enum brw_reg_type ATTRIBUTE_PURE
brw_hw_type_to_reg_type(const struct gen_device_info *devinfo,
brw_hw_type_to_reg_type(const struct intel_device_info *devinfo,
enum brw_reg_file file, unsigned hw_type);
unsigned
brw_reg_type_to_a16_hw_3src_type(const struct gen_device_info *devinfo,
brw_reg_type_to_a16_hw_3src_type(const struct intel_device_info *devinfo,
enum brw_reg_type type);
unsigned
brw_reg_type_to_a1_hw_3src_type(const struct gen_device_info *devinfo,
brw_reg_type_to_a1_hw_3src_type(const struct intel_device_info *devinfo,
enum brw_reg_type type);
enum brw_reg_type
brw_a16_hw_3src_type_to_reg_type(const struct gen_device_info *devinfo,
brw_a16_hw_3src_type_to_reg_type(const struct intel_device_info *devinfo,
unsigned hw_type);
enum brw_reg_type
brw_a1_hw_3src_type_to_reg_type(const struct gen_device_info *devinfo,
brw_a1_hw_3src_type_to_reg_type(const struct intel_device_info *devinfo,
unsigned hw_type, unsigned exec_type);
unsigned

4
src/intel/compiler/brw_rt.h
View file

@ -192,13 +192,13 @@ struct brw_rt_raygen_trampoline_params {
static inline void
brw_rt_compute_scratch_layout(struct brw_rt_scratch_layout *layout,
const struct gen_device_info *devinfo,
const struct intel_device_info *devinfo,
uint32_t stack_ids_per_dss,
uint32_t sw_stack_size)
{
layout->stack_ids_per_dss = stack_ids_per_dss;
const uint32_t dss_count = gen_device_info_num_dual_subslices(devinfo);
const uint32_t dss_count = intel_device_info_num_dual_subslices(devinfo);
const uint32_t num_stack_ids = dss_count * stack_ids_per_dss;
uint64_t size = 0;

4
src/intel/compiler/brw_schedule_instructions.cpp
View file

@ -916,7 +916,7 @@ vec4_instruction_scheduler::get_register_pressure_benefit(backend_instruction *)
schedule_node::schedule_node(backend_instruction *inst,
instruction_scheduler *sched)
{
const struct gen_device_info *devinfo = sched->bs->devinfo;
const struct intel_device_info *devinfo = sched->bs->devinfo;
this->inst = inst;
this->child_array_size = 0;
@ -1706,7 +1706,7 @@ vec4_instruction_scheduler::issue_time(backend_instruction *)
void
instruction_scheduler::schedule_instructions(bblock_t *block)
{
const struct gen_device_info *devinfo = bs->devinfo;
const struct intel_device_info *devinfo = bs->devinfo;
int time = 0;
int instructions_to_schedule = block->end_ip - block->start_ip + 1;

8
src/intel/compiler/brw_shader.cpp
View file

@ -161,7 +161,7 @@ brw_texture_offset(const nir_tex_instr *tex, unsigned src,
}
const char *
brw_instruction_name(const struct gen_device_info *devinfo, enum opcode op)
brw_instruction_name(const struct intel_device_info *devinfo, enum opcode op)
{
switch (op) {
case 0 ... NUM_BRW_OPCODES - 1:
@ -878,7 +878,7 @@ backend_instruction::is_commutative() const
}
bool
backend_instruction::is_3src(const struct gen_device_info *devinfo) const
backend_instruction::is_3src(const struct intel_device_info *devinfo) const
{
return ::is_3src(devinfo, opcode);
}
@ -1079,7 +1079,7 @@ backend_instruction::reads_accumulator_implicitly() const
}
bool
backend_instruction::writes_accumulator_implicitly(const struct gen_device_info *devinfo) const
backend_instruction::writes_accumulator_implicitly(const struct intel_device_info *devinfo) const
{
return writes_accumulator ||
(devinfo->ver < 6 &&
@ -1311,7 +1311,7 @@ brw_compile_tes(const struct brw_compiler *compiler,
struct brw_compile_stats *stats,
char **error_str)
{
const struct gen_device_info *devinfo = compiler->devinfo;
const struct intel_device_info *devinfo = compiler->devinfo;
const bool is_scalar = compiler->scalar_stage[MESA_SHADER_TESS_EVAL];
const bool debug_enabled = INTEL_DEBUG & DEBUG_TES;
const unsigned *assembly;

4
src/intel/compiler/brw_shader.h
View file

@ -56,7 +56,7 @@ public:
const struct brw_compiler *compiler;
void *log_data; /* Passed to compiler->*_log functions */
const struct gen_device_info * const devinfo;
const struct intel_device_info * const devinfo;
const nir_shader *nir;
struct brw_stage_prog_data * const stage_prog_data;
@ -96,7 +96,7 @@ struct backend_shader;
enum brw_reg_type brw_type_for_base_type(const struct glsl_type *type);
enum brw_conditional_mod brw_conditional_for_comparison(unsigned int op);
uint32_t brw_math_function(enum opcode op);
const char *brw_instruction_name(const struct gen_device_info *devinfo,
const char *brw_instruction_name(const struct intel_device_info *devinfo,
enum opcode op);
bool brw_saturate_immediate(enum brw_reg_type type, struct brw_reg *reg);
bool brw_negate_immediate(enum brw_reg_type type, struct brw_reg *reg);

8
src/intel/compiler/brw_vec4.cpp
View file

@ -236,7 +236,7 @@ vec4_instruction::size_read(unsigned arg) const
}
bool
vec4_instruction::can_do_source_mods(const struct gen_device_info *devinfo)
vec4_instruction::can_do_source_mods(const struct intel_device_info *devinfo)
{
if (devinfo->ver == 6 && is_math())
return false;
@ -271,7 +271,7 @@ vec4_instruction::can_do_cmod()
}
bool
vec4_instruction::can_do_writemask(const struct gen_device_info *devinfo)
vec4_instruction::can_do_writemask(const struct intel_device_info *devinfo)
{
switch (opcode) {
case SHADER_OPCODE_GFX4_SCRATCH_READ:
@ -1124,7 +1124,7 @@ vec4_visitor::opt_set_dependency_control()
}
bool
vec4_instruction::can_reswizzle(const struct gen_device_info *devinfo,
vec4_instruction::can_reswizzle(const struct intel_device_info *devinfo,
int dst_writemask,
int swizzle,
int swizzle_mask)
@ -2173,7 +2173,7 @@ stage_uses_interleaved_attributes(unsigned stage,
* instruction's original execution size.
*/
static unsigned
get_lowered_simd_width(const struct gen_device_info *devinfo,
get_lowered_simd_width(const struct intel_device_info *devinfo,
enum shader_dispatch_mode dispatch_mode,
unsigned stage, const vec4_instruction *inst)
{

2
src/intel/compiler/brw_vec4_copy_propagation.cpp
View file

@ -299,7 +299,7 @@ is_align1_opcode(unsigned opcode)
}
static bool
try_copy_propagate(const struct gen_device_info *devinfo,
try_copy_propagate(const struct intel_device_info *devinfo,
vec4_instruction *inst, int arg,
const copy_entry *entry, int attributes_per_reg)
{

22
src/intel/compiler/brw_vec4_generator.cpp
View file

@ -114,7 +114,7 @@ generate_tex(struct brw_codegen *p,
struct brw_reg surface_index,
struct brw_reg sampler_index)
{
const struct gen_device_info *devinfo = p->devinfo;
const struct intel_device_info *devinfo = p->devinfo;
int msg_type = -1;
if (devinfo->ver >= 5) {
@ -737,7 +737,7 @@ generate_gs_set_primitive_id(struct brw_codegen *p, struct brw_reg dst)
static void
generate_tcs_get_instance_id(struct brw_codegen *p, struct brw_reg dst)
{
const struct gen_device_info *devinfo = p->devinfo;
const struct intel_device_info *devinfo = p->devinfo;
const bool ivb = devinfo->is_ivybridge || devinfo->is_baytrail;
/* "Instance Count" comes as part of the payload in r0.2 bits 23:17.
@ -768,7 +768,7 @@ generate_tcs_urb_write(struct brw_codegen *p,
vec4_instruction *inst,
struct brw_reg urb_header)
{
const struct gen_device_info *devinfo = p->devinfo;
const struct intel_device_info *devinfo = p->devinfo;
brw_inst *send = brw_next_insn(p, BRW_OPCODE_SEND);
brw_set_dest(p, send, brw_null_reg());
@ -952,7 +952,7 @@ generate_vec4_urb_read(struct brw_codegen *p,
struct brw_reg dst,
struct brw_reg header)
{
const struct gen_device_info *devinfo = p->devinfo;
const struct intel_device_info *devinfo = p->devinfo;
assert(header.file == BRW_GENERAL_REGISTER_FILE);
assert(header.type == BRW_REGISTER_TYPE_UD);
@ -977,7 +977,7 @@ generate_tcs_release_input(struct brw_codegen *p,
struct brw_reg vertex,
struct brw_reg is_unpaired)
{
const struct gen_device_info *devinfo = p->devinfo;
const struct intel_device_info *devinfo = p->devinfo;
assert(vertex.file == BRW_IMMEDIATE_VALUE);
assert(vertex.type == BRW_REGISTER_TYPE_UD);
@ -1057,7 +1057,7 @@ generate_tcs_create_barrier_header(struct brw_codegen *p,
struct brw_vue_prog_data *prog_data,
struct brw_reg dst)
{
const struct gen_device_info *devinfo = p->devinfo;
const struct intel_device_info *devinfo = p->devinfo;
const bool ivb = devinfo->is_ivybridge || devinfo->is_baytrail;
struct brw_reg m0_2 = get_element_ud(dst, 2);
unsigned instances = ((struct brw_tcs_prog_data *) prog_data)->instances;
@ -1146,7 +1146,7 @@ generate_scratch_read(struct brw_codegen *p,
struct brw_reg dst,
struct brw_reg index)
{
const struct gen_device_info *devinfo = p->devinfo;
const struct intel_device_info *devinfo = p->devinfo;
struct brw_reg header = brw_vec8_grf(0, 0);
gfx6_resolve_implied_move(p, &header, inst->base_mrf);
@ -1192,7 +1192,7 @@ generate_scratch_write(struct brw_codegen *p,
struct brw_reg src,
struct brw_reg index)
{
const struct gen_device_info *devinfo = p->devinfo;
const struct intel_device_info *devinfo = p->devinfo;
const unsigned target_cache =
(devinfo->ver >= 7 ? GFX7_SFID_DATAPORT_DATA_CACHE :
devinfo->ver >= 6 ? GFX6_SFID_DATAPORT_RENDER_CACHE :
@ -1270,7 +1270,7 @@ generate_pull_constant_load(struct brw_codegen *p,
struct brw_reg index,
struct brw_reg offset)
{
const struct gen_device_info *devinfo = p->devinfo;
const struct intel_device_info *devinfo = p->devinfo;
const unsigned target_cache =
(devinfo->ver >= 6 ? GFX6_SFID_DATAPORT_SAMPLER_CACHE :
BRW_SFID_DATAPORT_READ);
@ -1356,7 +1356,7 @@ generate_pull_constant_load_gfx7(struct brw_codegen *p,
struct brw_reg surf_index,
struct brw_reg offset)
{
const struct gen_device_info *devinfo = p->devinfo;
const struct intel_device_info *devinfo = p->devinfo;
assert(surf_index.type == BRW_REGISTER_TYPE_UD);
if (surf_index.file == BRW_IMMEDIATE_VALUE) {
@ -1476,7 +1476,7 @@ generate_code(struct brw_codegen *p,
struct brw_compile_stats *stats,
bool debug_enabled)
{
const struct gen_device_info *devinfo = p->devinfo;
const struct intel_device_info *devinfo = p->devinfo;
const char *stage_abbrev = _mesa_shader_stage_to_abbrev(nir->info.stage);
struct disasm_info *disasm_info = disasm_initialize(devinfo, cfg);

2
src/intel/compiler/brw_vec4_nir.cpp
View file

@ -282,7 +282,7 @@ vec4_visitor::get_indirect_offset(nir_intrinsic_instr *instr)
static src_reg
setup_imm_df(const vec4_builder &bld, double v)
{
const gen_device_info *devinfo = bld.shader->devinfo;
const intel_device_info *devinfo = bld.shader->devinfo;
assert(devinfo->ver == 7);
/* gfx7.5 does not support DF immediates straighforward but the DIM

2
src/intel/compiler/brw_vec4_tcs.cpp
View file

@ -365,7 +365,7 @@ brw_compile_tcs(const struct brw_compiler *compiler,
struct brw_compile_stats *stats,
char **error_str)
{
const struct gen_device_info *devinfo = compiler->devinfo;
const struct intel_device_info *devinfo = compiler->devinfo;
struct brw_vue_prog_data *vue_prog_data = &prog_data->base;
const bool is_scalar = compiler->scalar_stage[MESA_SHADER_TESS_CTRL];
const bool debug_enabled = INTEL_DEBUG & DEBUG_TCS;

2
src/intel/compiler/brw_vec4_visitor.cpp
View file

@ -1245,7 +1245,7 @@ vec4_visitor::emit_urb_slot(dst_reg reg, int varying)
}
static unsigned
align_interleaved_urb_mlen(const struct gen_device_info *devinfo, unsigned mlen)
align_interleaved_urb_mlen(const struct intel_device_info *devinfo, unsigned mlen)
{
if (devinfo->ver >= 6) {
/* URB data written (does not include the message header reg) must

2
src/intel/compiler/brw_vue_map.c
View file

@ -57,7 +57,7 @@ assign_vue_slot(struct brw_vue_map *vue_map, int varying, int slot)
* Compute the VUE map for a shader stage.
*/
void
brw_compute_vue_map(const struct gen_device_info *devinfo,
brw_compute_vue_map(const struct intel_device_info *devinfo,
struct brw_vue_map *vue_map,
uint64_t slots_valid,
bool separate,

8
src/intel/compiler/test_eu_compact.cpp
View file

@ -65,7 +65,7 @@ test_compact_instruction(struct brw_codegen *p, brw_inst src)
* become meaningless once fuzzing twiddles a related bit.
*/
static void
clear_pad_bits(const struct gen_device_info *devinfo, brw_inst *inst)
clear_pad_bits(const struct intel_device_info *devinfo, brw_inst *inst)
{
if (brw_inst_opcode(devinfo, inst) != BRW_OPCODE_SEND &&
brw_inst_opcode(devinfo, inst) != BRW_OPCODE_SENDC &&
@ -83,7 +83,7 @@ clear_pad_bits(const struct gen_device_info *devinfo, brw_inst *inst)
}
static bool
skip_bit(const struct gen_device_info *devinfo, brw_inst *src, int bit)
skip_bit(const struct intel_device_info *devinfo, brw_inst *src, int bit)
{
/* pad bit */
if (bit == 7)
@ -285,7 +285,7 @@ struct {
};
static bool
run_tests(const struct gen_device_info *devinfo)
run_tests(const struct intel_device_info *devinfo)
{
bool fail = false;
@ -330,7 +330,7 @@ run_tests(const struct gen_device_info *devinfo)
int
main(UNUSED int argc, UNUSED char **argv)
{
struct gen_device_info *devinfo = (struct gen_device_info *)calloc(1, sizeof(*devinfo));
struct intel_device_info *devinfo = (struct intel_device_info *)calloc(1, sizeof(*devinfo));
bool fail = false;
for (devinfo->ver = 5; devinfo->ver <= 12; devinfo->ver++) {

14
src/intel/compiler/test_eu_validate.cpp
View file

@ -58,7 +58,7 @@ public:
virtual ~validation_test();
struct brw_codegen *p;
struct gen_device_info devinfo;
struct intel_device_info devinfo;
};
validation_test::validation_test()
@ -75,7 +75,7 @@ validation_test::~validation_test()
void validation_test::SetUp()
{
struct gen_info info = GetParam();
int devid = gen_device_name_to_pci_device_id(info.name);
int devid = intel_device_name_to_pci_device_id(info.name);
gen_get_device_info_from_pci_id(devid, &devinfo);
@ -2312,7 +2312,7 @@ TEST_P(validation_test, qword_low_power_align1_regioning_restrictions)
brw_inst_set_src0_width(&devinfo, last_inst, inst[i].src_width);
brw_inst_set_src0_hstride(&devinfo, last_inst, inst[i].src_hstride);
if (devinfo.is_cherryview || gen_device_info_is_9lp(&devinfo)) {
if (devinfo.is_cherryview || intel_device_info_is_9lp(&devinfo)) {
EXPECT_EQ(inst[i].expected_result, validate(p));
} else {
EXPECT_TRUE(validate(p));
@ -2444,7 +2444,7 @@ TEST_P(validation_test, qword_low_power_no_indirect_addressing)
brw_inst_set_src0_width(&devinfo, last_inst, inst[i].src_width);
brw_inst_set_src0_hstride(&devinfo, last_inst, inst[i].src_hstride);
if (devinfo.is_cherryview || gen_device_info_is_9lp(&devinfo)) {
if (devinfo.is_cherryview || intel_device_info_is_9lp(&devinfo)) {
EXPECT_EQ(inst[i].expected_result, validate(p));
} else {
EXPECT_TRUE(validate(p));
@ -2591,7 +2591,7 @@ TEST_P(validation_test, qword_low_power_no_64bit_arf)
brw_inst_set_src0_width(&devinfo, last_inst, inst[i].src_width);
brw_inst_set_src0_hstride(&devinfo, last_inst, inst[i].src_hstride);
if (devinfo.is_cherryview || gen_device_info_is_9lp(&devinfo)) {
if (devinfo.is_cherryview || intel_device_info_is_9lp(&devinfo)) {
EXPECT_EQ(inst[i].expected_result, validate(p));
} else {
EXPECT_TRUE(validate(p));
@ -2607,7 +2607,7 @@ TEST_P(validation_test, qword_low_power_no_64bit_arf)
brw_MAC(p, retype(g0, BRW_REGISTER_TYPE_DF),
retype(stride(g0, 4, 4, 1), BRW_REGISTER_TYPE_DF),
retype(stride(g0, 4, 4, 1), BRW_REGISTER_TYPE_DF));
if (devinfo.is_cherryview || gen_device_info_is_9lp(&devinfo)) {
if (devinfo.is_cherryview || intel_device_info_is_9lp(&devinfo)) {
EXPECT_FALSE(validate(p));
} else {
EXPECT_TRUE(validate(p));
@ -2809,7 +2809,7 @@ TEST_P(validation_test, qword_low_power_no_depctrl)
brw_inst_set_no_dd_check(&devinfo, last_inst, inst[i].no_dd_check);
brw_inst_set_no_dd_clear(&devinfo, last_inst, inst[i].no_dd_clear);
if (devinfo.is_cherryview || gen_device_info_is_9lp(&devinfo)) {
if (devinfo.is_cherryview || intel_device_info_is_9lp(&devinfo)) {
EXPECT_EQ(inst[i].expected_result, validate(p));
} else {
EXPECT_TRUE(validate(p));

4
src/intel/compiler/test_fs_cmod_propagation.cpp
View file

@ -34,7 +34,7 @@ class cmod_propagation_test : public ::testing::Test {
public:
struct brw_compiler *compiler;
struct gen_device_info *devinfo;
struct intel_device_info *devinfo;
void *ctx;
struct brw_wm_prog_data *prog_data;
struct gl_shader_program *shader_prog;
@ -67,7 +67,7 @@ void cmod_propagation_test::SetUp()
{
ctx = ralloc_context(NULL);
compiler = rzalloc(ctx, struct brw_compiler);
devinfo = rzalloc(ctx, struct gen_device_info);
devinfo = rzalloc(ctx, struct intel_device_info);
compiler->devinfo = devinfo;
prog_data = ralloc(ctx, struct brw_wm_prog_data);

4
src/intel/compiler/test_fs_copy_propagation.cpp
View file

@ -34,7 +34,7 @@ class copy_propagation_test : public ::testing::Test {
public:
struct brw_compiler *compiler;
struct gen_device_info *devinfo;
struct intel_device_info *devinfo;
void *ctx;
struct brw_wm_prog_data *prog_data;
struct gl_shader_program *shader_prog;
@ -57,7 +57,7 @@ void copy_propagation_test::SetUp()
{
ctx = ralloc_context(NULL);
compiler = rzalloc(ctx, struct brw_compiler);
devinfo = rzalloc(ctx, struct gen_device_info);
devinfo = rzalloc(ctx, struct intel_device_info);
compiler->devinfo = devinfo;
prog_data = ralloc(ctx, struct brw_wm_prog_data);

4
src/intel/compiler/test_fs_saturate_propagation.cpp
View file

@ -34,7 +34,7 @@ class saturate_propagation_test : public ::testing::Test {
public:
struct brw_compiler *compiler;
struct gen_device_info *devinfo;
struct intel_device_info *devinfo;
void *ctx;
struct brw_wm_prog_data *prog_data;
struct gl_shader_program *shader_prog;
@ -57,7 +57,7 @@ void saturate_propagation_test::SetUp()
{
ctx = ralloc_context(NULL);
compiler = rzalloc(ctx, struct brw_compiler);
devinfo = rzalloc(ctx, struct gen_device_info);
devinfo = rzalloc(ctx, struct intel_device_info);
compiler->devinfo = devinfo;
prog_data = ralloc(ctx, struct brw_wm_prog_data);

4
src/intel/compiler/test_fs_scoreboard.cpp
View file

@ -34,7 +34,7 @@ class scoreboard_test : public ::testing::Test {
public:
struct brw_compiler *compiler;
struct gen_device_info *devinfo;
struct intel_device_info *devinfo;
void *ctx;
struct brw_wm_prog_data *prog_data;
struct gl_shader_program *shader_prog;
@ -45,7 +45,7 @@ void scoreboard_test::SetUp()
{
ctx = ralloc_context(NULL);
compiler = rzalloc(ctx, struct brw_compiler);
devinfo = rzalloc(ctx, struct gen_device_info);
devinfo = rzalloc(ctx, struct intel_device_info);
compiler->devinfo = devinfo;
prog_data = ralloc(ctx, struct brw_wm_prog_data);

4
src/intel/compiler/test_vec4_cmod_propagation.cpp
View file

@ -37,7 +37,7 @@ class cmod_propagation_test : public ::testing::Test {
public:
struct brw_compiler *compiler;
struct gen_device_info *devinfo;
struct intel_device_info *devinfo;
void *ctx;
struct gl_shader_program *shader_prog;
struct brw_vue_prog_data *prog_data;
@ -100,7 +100,7 @@ void cmod_propagation_test::SetUp()
{
ctx = ralloc_context(NULL);
compiler = rzalloc(ctx, struct brw_compiler);
devinfo = rzalloc(ctx, struct gen_device_info);
devinfo = rzalloc(ctx, struct intel_device_info);
compiler->devinfo = devinfo;
prog_data = ralloc(ctx, struct brw_vue_prog_data);

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