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intel/dev: Implement DG2 restrictions requiring additional DSSes to be disabled.

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Note that this causes a geometry slice to be disabled if any DSS is
fused off within that slice, which may seem stricter than the BSpec
quotation implies, but testing shows that pixel pipes with any faulted
DSS don't work at all, and that using a slice with any faulted pixel
pipe leads to serious graphics corruption.

It would be better to query this geometry topology information from
the hardware instead of trying to reconstruct it here, but the kernel
interface for that is not available yet.

Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14436>
This commit is contained in:
Francisco Jerez 2021-12-09 16:29:06 -08:00 • committed by Marge Bot
parent e48c29acca
commit 054eb9f346
1 changed files with 19 additions and 0 deletions
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19
src/intel/dev/intel_device_info.c
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@ -1110,6 +1110,25 @@ update_from_topology(struct intel_device_info *devinfo,
else
devinfo->ppipe_subslices[p] = 0;
}
/* From the "Fusing information" BSpec page regarding DG2
* configurations where at least a slice has a single pixel pipe
* fused off:
*
* "Fault disable any 2 DSS in a Gslice and disable that Gslice
* (incl. geom/color/Z)"
*
* XXX - Query geometry topology from hardware once kernel
* interface is available instead of trying to do
* guesswork here.
*/
if (intel_device_info_is_dg2(devinfo)) {
for (unsigned p = 0; p < INTEL_DEVICE_MAX_PIXEL_PIPES; p++) {
if (devinfo->ppipe_subslices[p] < 2 ||
devinfo->ppipe_subslices[p ^ 1] < 2)
devinfo->ppipe_subslices[p] = 0;
}
}
}
if (devinfo->ver == 12 && devinfo->num_slices == 1) {