Commit graph

29173 commits

Author SHA1 Message Date
Tim Rowley
aaeb07989e swr: [rasterizer jitter] fixes for icc in vs2015 compat mode
- Move most jitter functionality into SwrJit namespace
- Avoid global "using namespace llvm" in headers

Signed-off-by: Tim Rowley <timothy.o.rowley@intel.com>
2016-10-03 09:57:19 -05:00
Tim Rowley
b8a6f06c85 swr: [rasterizer core] generalize compute dispatch mechanism
Generalize compute dispatch mechanism to support other types of dispatches.

Signed-off-by: Tim Rowley <timothy.o.rowley@intel.com>
2016-10-03 09:57:13 -05:00
Tim Rowley
33a1a09eb0 swr: [rasterizer common] os.h portability header changes
- Fix conflict between windows MemoryFence and llvm::sys::MemoryFence
- Declare gettid()

Signed-off-by: Tim Rowley <timothy.o.rowley@intel.com>
2016-10-03 09:56:47 -05:00
Steven Toth
e99b9395be gallium/hud: Add support for CPU frequency monitoring
Detect all of the CPUs in the system. Expose metrics
for min, max and current frequency in Hz.

Signed-off-by: Steven Toth <stoth@kernellabs.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
2016-09-30 15:18:46 -06:00
Marek Olšák
7b87190d2b Revert "gallium/hud: automatically print % if max_value == 100"
This reverts commit dbfeb0ec12.

With max_value being rounded to 100, it's often wrong.

Reviewed-by: Brian Paul <brianp@vmware.com>
2016-09-30 22:07:12 +02:00
Nicolai Hähnle
7bac5bf032 gallium/radeon: fix crash/regression in performance counters
Regression introduced by "gallium/radeon: zero all query buffers".

Cc: Michel Dänzer <michel@daenzer.net>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2016-09-30 12:41:45 +02:00
Nicolai Hähnle
cfd870de70 gallium/radeon: update documentation of buffer_get_virtual_address
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2016-09-30 12:41:41 +02:00
Nicolai Hähnle
fd9f54223d gallium/radeon: emit relocations for query fences
This is only needed for r600 which doesn't have ARB_query_buffer_object and
therefore wouldn't really need the fences, but let's be optimistic about
filling in this feature gap eventually.

Cc: Dieter Nützel <Dieter@nuetzel-hh.de>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2016-09-30 12:38:57 +02:00
Nicolai Hähnle
3e7cced4b9 radeon/uvd: adjust the buffer offset when relocation is used
We don't plan to use sub-allocated buffers with UVD, but just in case one
slips through, this increases the chances of things working out anyway.

Reviewed-by: Christian König <christian.koenig@amd.com>
2016-09-30 12:38:52 +02:00
Nicolai Hähnle
a48bf02d05 radeon/vce: adjust the buffer offset when relocation is used
We don't plan to use sub-allocated buffers with VCE, but just in case one
slips through, this increases the chances of things working out anyway.

Reviewed-by: Christian König <christian.koenig@amd.com>
2016-09-30 12:38:48 +02:00
Nicolai Hähnle
13cb41f666 radeon/video: don't use sub-allocated buffers
Cc: Christian König <christian.koenig@amd.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=97976
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=97969
Reviewed-by: Christian König <christian.koenig@amd.com>
2016-09-30 12:38:29 +02:00
Steven Toth
1d466b9b04 gallium/hud: Add power sensor support
Implement support for power based sensors, reporting units in
milli-watts and watts.

Also, minor cleanup - change the related if block to a switch.

Tested with two different power sensors, including the nouveau
'power1' sensors on a GTX950 card.

Signed-off-by: Steven Toth <stoth@kernellabs.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
2016-09-29 17:51:15 -06:00
Samuel Pitoiset
3abe68b828 nv50/ir: teach insnCanLoad() about SHLADD
Commutativity is not allowed with SHLADD, but src2 can accept
loads. To allow the load propagation pass to do its job, add a
special case like for SUCLAMP because src1 is always an immediate.

This IMAD to SHLADD optimization helps a bunch of shaders from Tomb
Raider, Victor Vran, UE4 demos (+15% perf with Elemental) and Shadow
Warrior.

GF100/GK104:

total instructions in shared programs :2838045 -> 2834712 (-0.12%)
total gprs used in shared programs    :396684 -> 396386 (-0.08%)
total local used in shared programs   :34416 -> 34416 (0.00%)

                local        gpr       inst      bytes
    helped           0         326        1105        1105
      hurt           0          55           3           3

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
2016-09-29 21:20:50 +02:00
Samuel Pitoiset
115c79be10 nv50/ir: optimize SHLADD(a, b, c) to MOV((a << b) + c)
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
2016-09-29 21:20:47 +02:00
Samuel Pitoiset
2e008be9a9 nv50/ir: optimize SHLADD(a, b, 0x0) to SHL(a, b)
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
2016-09-29 21:20:44 +02:00
Samuel Pitoiset
e4eb0fca02 nv50/ir: optimize IMAD to SHLADD in presence of power of 2
Only and only if src1 is a power of 2 we can replace IMAD by SHLADD.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
2016-09-29 21:20:41 +02:00
Samuel Pitoiset
31545b64b8 nvc0/ir: add emission for SHLADD
Unfortunately, we can't use the emit helpers for GF100/GK110
because src1 and src2 are swapped.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
2016-09-29 21:20:36 +02:00
Samuel Pitoiset
85132c7453 nv50/ir: add preliminary support for SHLADD
This instruction is available since SM20 (Fermi) and allow to do
(a << b) + c in one shot. In some situations, IMAD should be
replaced by SHLADD when b is a power of 2, and ADD+SHL should be
replaced by SHLADD as well.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
2016-09-29 21:20:30 +02:00
Samuel Pitoiset
652874754a nvc0: update GM107 sched control codes format
envyas now uses a much better representation for those control
codes and it displays the different flags instead of an
unreadable hex number.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
2016-09-29 20:13:05 +02:00
Nicolai Hähnle
e4b585f009 gallium/radeon: use smaller buffers for query results
Most of the time, even the 512 bytes that we now get is more than sufficient
(pipeline stats queries are the largest at 184 bytes per shot).

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2016-09-29 11:24:56 +02:00
Nicolai Hähnle
de84e99e45 gallium/radeon/winsyses: add radeon_winsys::min_alloc_size
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2016-09-29 11:24:52 +02:00
Nicolai Hähnle
7a0e543836 radeonsi: enable ARB_query_buffer_object (v2)
v2: enable only when compute is available

Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2016-09-29 11:15:00 +02:00
Nicolai Hähnle
15e2661137 gallium/radeon: implement get_query_result_resource (v2)
v2: fix a comment (Gustaw Smolarczyk)

Acked-by: Edward O'Callaghan <funfunctor@folklore1984.net>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2016-09-29 11:14:54 +02:00
Nicolai Hähnle
2c9d546402 gallium/radeon: zero all query buffers
To ensure that fences are properly initialized.

Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2016-09-29 11:14:51 +02:00
Nicolai Hähnle
daeab0171d gallium/radeon: cleanup getting PIPE_QUERY_TIMESTAMP result
Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2016-09-29 11:14:45 +02:00
Nicolai Hähnle
631c47384c gallium/radeon: add query fences and r600_get_hw_query_params
We will support the waiting option in ARB_query_buffer_object using
WAIT_REG_MEM on an appropriate fence-like dword. Some queries conveniently
write their results with the highest bit set, and we can just use that;
for others, we have to write a fence explicitly.

ZPASS_DONE for occlusion queries writes its results with the high bit
set, but it writes up to 8 pairs of results (one for each DB). We have
to wait for all of these results, so let's just add an explicit fence.

The new function provides summary information to be used by subsequent
patches.

Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2016-09-29 11:14:41 +02:00
Nicolai Hähnle
51b57a9b5a radeonsi: add save_qbo_state
Save compute shader state that will be used for the ARB_query_buffer_object
implementation.

Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2016-09-29 11:14:37 +02:00
Nicolai Hähnle
70f9ca2468 radeonsi: add si_get_shader_buffers/get_pipe_constant_buffers (v2)
These functions extract the pipe state structure from the current
descriptors, for state saving.

v2: correctly dereference *buf (Bas)

Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2016-09-29 11:14:33 +02:00
Nicolai Hähnle
8d45243e40 gallium/radeon: add r600_gfx_{write,wait}_fence
For bottom-of-pipe fences inside the gfx command stream.

Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2016-09-29 11:14:29 +02:00
Nicolai Hähnle
8e4de00930 gallium/radeon: add barrier_flags to r600_common_screen
There are driver-specific context flags for barriers that are not covered
by the Gallium barrier interfaces.

The R600 settings of these flags may not be optimal, but we're not going
to use them yet anyway.

Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2016-09-29 11:14:11 +02:00
Steven Toth
8c60bcb4c3 gallium/hud: Add support for block I/O, network I/O and lmsensor stats
V8: Feedback based on peer review
    convert if block into a switch
    Constify some func args

V7: Increase precision when measuring lmsensors volts
    Flatten patch series.

V6: Feedback based on peer review
    Simplify sensor initialization (arg passing).
    Constify some func args

V5: Feedback based on peer review
    Convert sprintf to snprintf
    Convert char * to const char *
    int arg converted to bool
    Func changes to take a filename vs a larger struct.
    Omit the space between '*' and the param name.

V4: Merged with master as of 2016/9/27 6pm

V3: Flatten the entire patchset ready for the ML

V2: Additional seperate patches based on feedback
a) configure.ac: Add a comment related to libsensors

b) HUD: Disable Block/NIC I/O stats by default.
Implement configuration option --enable-gallium-extra-hud=yes
and enable both statistics when this option is enabled.

c) Configure.ac: Minor cleanup to user visible configuration settings

d) Configure.ac: HUD stats - build system improvements
Move the -lsensors out of a deeper Makefile, bring it into the configure.ac.
Also, rename a compiler directive to more closely follow the standard.

V1: Initial release to the ML
Three new features:
1. Disk/block I/O device read/write stats MB/ps.
2. Network Interface RX/TX transfer statistics as a percentage
   of the overall NIC speed.
3. lmsensor power, voltage and temperature sensors.

The lmsensor changes makes a dependency on libsensors so support
for the change is opt out by default.

Signed-off-by: Steven Toth <stoth@kernellabs.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
2016-09-28 16:18:05 -06:00
Eric Anholt
2a721b1b79 vc4: Emit perf debug when we fall back to quad clears. 2016-09-28 08:31:14 -07:00
Michel Dänzer
8d8c440ebf gallium/radeon: Initialize pipe_resource::next to NULL
Fixes lots of piglit tests crashing due to using uninitialized memory.

Fixes: ecd6fce261 ("mesa/st: support lowering multi-planar YUV")
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2016-09-28 10:39:22 +09:00
Tim Rowley
50842e8a93 swr: replace gallium->swr format enum conversion
Replace old string comparison with a mapping table.

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
2016-09-27 12:55:26 -05:00
Nicolai Hähnle
4421c0fb0d gallium/radeon/winsyses: reduce the number of pb_cache buckets
Small buffers are now handled via the slabs code, so separate buckets in
pb_cache have become redundant.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2016-09-27 16:45:41 +02:00
Nicolai Hähnle
fb827c055c winsys/radeon: enable buffer allocation from slabs
Only enable for chips with GPUVM, because older driver paths do not take the
required offset into account.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2016-09-27 16:45:37 +02:00
Nicolai Hähnle
a1e391e39d winsys/radeon: add fine-grained fences for slab buffers
Note the logic for adding fences is somewhat different than for amdgpu,
because radeon has no scheduler and we therefore have no guarantee about
the order in which submissions from multiple threads are processed.

(Ironically, this is only an issue when "multi-threaded submission" is
disabled, because "multi-threaded submission" actually means that all
submissions happen from a single thread that happens to be separate from
the application's threads. If we only supported "multi-threaded
submission", the fence handling could be simplified by adding the fences
in that thread where everything is serialized.)

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2016-09-27 16:45:34 +02:00
Nicolai Hähnle
0edebde9a4 winsys/radeon: add slab buffer list
Introducing radeon_bo::hash will reduce collisions between "real" buffers
and buffers from slabs.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2016-09-27 16:45:32 +02:00
Nicolai Hähnle
cbb9c2f170 winsys/radeon: separate adding a buffer from updating its reloc data
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2016-09-27 16:45:29 +02:00
Nicolai Hähnle
a9e8672585 winsys/radeon: add slab entry structures to radeon_bo
Already adjust the map/unmap logic accordingly.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2016-09-27 16:45:25 +02:00
Nicolai Hähnle
ffa1c669dd winsys/amdgpu: enable buffer allocation from slabs
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2016-09-27 16:45:23 +02:00
Nicolai Hähnle
a3832590c6 winsys/amdgpu: add fence and buffer list logic for slab allocated buffers
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2016-09-27 16:45:20 +02:00
Nicolai Hähnle
a987e4377a winsys/amdgpu: add slab entry structures to amdgpu_winsys_bo
Already adjust amdgpu_bo_map/unmap accordingly.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2016-09-27 16:45:15 +02:00
Nicolai Hähnle
5af9eef719 winsys/amdgpu: do not synchronize unsynchronized buffers
When a buffer is added to a CS without the SYNCHRONIZED usage flag, we now
no longer add a dependency on the buffer's fence(s).

However, we still need to add a fence to the buffer during flush, so that
cache reclaim works correctly (and in the hypothetical case that the buffer
is later added to a CS _with_ the SYNCHRONIZED flag).

It is now possible that the submissions refererring to a buffer are no longer
linearly ordered, and so we may have to keep multiple fences around. We keep
the fences in a FIFO. It should usually stay quite short (# of contexts * 2,
for gfx + dma rings).

While we're at it, extract amdgpu_add_fence_dependency for a single buffer,
which will make adding the distinction between real buffer and slab cases
easier.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2016-09-27 16:45:11 +02:00
Nicolai Hähnle
6d89a40676 gallium/radeon: add RADEON_FLAG_HANDLE
When passed to winsys->buffer_create, this flag will indicate that we require
a buffer that maps 1:1 with a kernel buffer handle.

This is currently set for all textures, since textures can potentially be
exported to other processes. This is not a huge loss, since the main purpose
of this patch series is to deal with applications that allocate many small
buffers.

A hypothetical application with tons of tiny textures might still benefit
from not setting this flag, but that's not a use case I'm worried about
just now.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2016-09-27 16:45:05 +02:00
Nicolai Hähnle
e703f71ebd gallium/radeon: add RADEON_USAGE_SYNCHRONIZED
This is really the behavior we want most of the time, but having a
SYNCHRONIZED flag instead of an UNSYNCHRONIZED one has the advantage that
OR'ing different flags together always results in stronger guarantees.

The parent BOs of sub-allocated buffers will be added unsynchronized.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2016-09-27 16:45:02 +02:00
Nicolai Hähnle
84f156c0cb gallium/pipebuffer: add pb_slab utility
This is a simple framework for slab allocation from buffers that fits into
the buffer management scheme of the radeon and amdgpu winsyses where bufmgrs
aren't used.

The utility knows about different sized allocations and explicitly manages
reclaim of allocations that have pending fences. It manages all the free lists
but does not actually touch buffer objects directly, relying on callbacks for
that.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2016-09-27 16:44:42 +02:00
Nicolai Hähnle
b3ebc229dc gallium/u_math: add util_logbase2_ceil
For finding the exponent of the next power of two.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2016-09-27 16:44:38 +02:00
Nicholas Bishop
c060f291c2 i915g: add dma-buf support to i915_drm_buffer_get_handle
The implementation of i915_drm_buffer_get_handle now handles
DRM_API_HANDLE_TYPE_FD in the same way that intel_winsys_import_handle
does, by calling drm_intel_bo_gem_create_from_prime.

Tested by successfully running Chrome's ozone_demo [1] with the
ozone-gbm backend on an Intel Pineview M machine. Without this change
it fails while trying to create a DMA-BUF.

[1] https://chromium.googlesource.com/chromium/src.git/+/master/ui/ozone/demo/ozone_demo.cc

Signed-off-by: Nicholas Bishop <nbishop@neverware.com>
[Emil Velikov: Fix coding style]
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
2016-09-27 13:37:21 +01:00
Nicholas Bishop
aa560e8e63 st/dri: check pipe_screen->resource_get_handle() return value
Change dri2_query_image to check the return value of resource_get_handle
and return GL_FALSE if an error occurs.

For reference this is an example callstack that should propagate the
error back to the user:

    i915_drm_buffer_get_handle
    i915_texture_get_handle
    u_resource_get_handle_vtbl
    dri2_query_image
    gbm_dri_bo_get_fd
    gbm_bo_get_fd

Cc: mesa-stable@lists.freedesktop.org
Signed-off-by: Nicholas Bishop <nbishop@neverware.com>
Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com> (v1)
[Emil Velikov: Split from larger patch, polish coding style, cc stable]
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
2016-09-27 13:37:21 +01:00