We're about to start using YCRCB_NORMAL and YCRCB_SWAPUV for 8-bit
interleaved YCbCr and, while ISL claims CCS_E support, it's not well
tested and we don't think it's working yet for all of ANV's use-cases.
Disable it for now in ANV and only for YUV formats.
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24619>
BLORP uses the get_ccs_compatible_copy_format() based on whether or not
ISL claims the format supports CCS_E, not whether or not CCS_E is used
on the image. This is probably a good thing as it improves consistency.
However, it means that we need CCS-compatible formats for YCRCB_*
formats even if we never use them with CCS_E enabled. In practice,
these do actually seem to work according to the Vulkan CTS but coverage
is likely far less than perfect.
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24619>
Instead, we replace every use of it with nir_def. Most of this commit
was generated by sed:
sed -i -e 's/dest.ssa/def/g' src/**/*.h src/**/*.c src/**/*.cpp
A few manual fixups were required in lima and the nir_legacy code.
Acked-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24674>
Instead, we replace it directly with nir_def. We could replace it with
nir_dest but the next commit gets rid of that so this avoids unnecessary
churn. Most of this commit was generated by sed:
sed -i -e 's/dest.dest.ssa/def/g' src/**/*.h src/**/*.c src/**/*.cpp
There were a few manual fixups required in the nir_legacy.c and
nir_from_ssa.c as nir_legacy_reg and nir_parallel_copy_entry both have a
similar pattern.
Acked-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24674>
We could add a nir_def_num_components() helper but we use
ssa.num_components about 3x as often as nir_dest_num_components() today
so that's a major Coccinelle refactor anyway and this doesn't make it
much worse. Most of this commit was generated byt the following
semantic patch:
@@
expression D;
@@
<...
-nir_dest_num_components(D)
+D.ssa.num_components
...
Some manual fixup was needed, especially in cpp files where Coccinelle
tends to give up the moment it sees any interesting C++.
Acked-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24674>
We could add a nir_def_bit_size() helper but we use ->bit_size about 3x
as often as nir_dest_bit_size() today so that's a major Coccinelle
refactor anyway and this doesn't make it much worse. Most of this
commit was generated byt the following semantic patch:
@@
expression D;
@@
<...
-nir_dest_bit_size(D)
+D.ssa.bit_size
...
Some manual fixup was needed, especially in cpp files where Coccinelle
tends to give up the moment it sees any interesting C++.
Acked-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24674>
Even with direct descriptors, our current implementation works by
doing A64 messages to read/write dynamic buffers. This is so that we
can apply the sliding range view of the descriptor while having
robustness support.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: 06dfd216d3 ("anv: add direct descriptor support to apply_layout")
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24256>
Catching the cases that Coccinelle missed. Mostly in C++ files using
gtest which causes Coccinelle to just give up and walk away.
Acked-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24658>
The initialization can be simplified and the real programming moved
over to genX_pipeline.c
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24632>
Following 71ebd9b9d7, 3DSTATE_GS can be emitted as part of the
pipeline batch and as a dynamic state. Just do the latter.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: 71ebd9b9d7 ("anv,hasvk: respect provoking vertex setting on geometry shaders")
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24632>
We can disable the MESH/TASK stages by just using the CONTROL
instruction and keep the rest of the HW programmed as before.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24632>
According to WA description, we need to track DS write state
and emit a PSS_STALL_SYNC whenever that state changes.
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18411>
This is required for Wa_18019816803 when blorp emit DS state.
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18411>
It can be useful to compare 2 runs with different compiler changes.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24552>
One particular nice thing to have is the first generated backend IR
before validation. Especially if you made a mistake in the NIR
translation, you can at least look at it before validation tells you
off.
Then the last 2 steps of the optimize() function can be interesting to
look at.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24552>
And split them into UBO and SSBO
v2 (Lionel):
- Get rid of robustness fields in anv_shader_bin
v3 (Lionel):
- Do not pass unused parameters around
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17545>
We cannot find anything in the Vulkan spec requiring this. D3D12 [1]
says it's undefined as long as it doesn't crash the OS :
"Out of bounds indexing of any descriptor table from the shader
results in a largely undefined memory access, including the
possibility of reading arbitrary in-process memory as if it is a
hardware state descriptor and living with the consequence of what
the hardware does with that. This could produce a device reset, but
will not crash Windows."
[1] : https://learn.microsoft.com/en-us/windows/win32/direct3d12/advanced-use-of-descriptor-tables#out-of-bounds-indexing
Found 2 titles affected by this change
Some pretty good results on Cyberpunk 2077 :
Totals from 10285 (100.00% of 10285) affected shaders:
Instrs: 7638709 -> 7517360 (-1.59%); split: -1.64%, +0.05%
Cycles: 148047414 -> 148470916 (+0.29%); split: -0.83%, +1.12%
Subgroup size: 112544 -> 112576 (+0.03%); split: +0.04%, -0.01%
Spill count: 98 -> 90 (-8.16%)
Fill count: 90 -> 82 (-8.89%)
Max live registers: 495274 -> 479502 (-3.18%); split: -3.21%, +0.03%
Max dispatch width: 87824 -> 91168 (+3.81%); split: +4.10%, -0.29%
Gaining 297 shaders in SIMD16/32, loosing 16 SIMD32 shaders
Some not so good results on Strange Brigade :
Totals from 4027 (100.00% of 4027) affected shaders:
Instrs: 2080355 -> 2013880 (-3.20%); split: -3.20%, +0.01%
Cycles: 25405149 -> 25170579 (-0.92%); split: -1.37%, +0.45%
Max live registers: 167303 -> 168958 (+0.99%)
Max dispatch width: 33264 -> 32496 (-2.31%)
Loosing 96 SIMD16 shaders.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17545>
This replicates the same fix we did for Anv and null descriptors with
A64 messages from commit efcda1c530 ("anv: fix null descriptor
handling with A64 messages").
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: mesa-stable
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17545>
This change allow us to insert the MI_SEMAPHORE_WAIT before/after
specific draw call. With GTX tool, we can always update the memory
address to unblock spinning wait.
v2:
- Make sure draw_call_count is thread-safe (Lionel)
- Add static inline helper (Lionel)
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24308>
Some older gens used '_' (underscore) while newer gens used a ' '
(space).
$ sed -i 's/Texture_Coordinate_Mode/Texture\ Coordinate\ Mode/' \
src/intel/genxml/*.xml
The naming needs to be aligned for importing enums later on.
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24547>
Vulkan defines the scaling lists according to the H264 ITU spec, which
only defines ScalingList8x8[0] and ScalingList8x8[1] for
non-444 formats.
Reviewed-by: Lynne <dev@lynne.ee>
Reviewed-by: Hyunjun Ko <zzoon@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24474>
Sync with commit f16c04291100 ("drm/xe: Rename engine to exec_queue").
With that Iris and ANV had some major renames that were done manually
as there is to many "engine" in non-related code.
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24476>
Brown paper bag fix for my untested review feedback comments.
Cube array images use a coordinate of the form <X, Y, 6*Slice+Face>,
while cube array textures use a <X, Y, Slice, Face> style coordinate.
This code tried to convert one to the other, but instead of writing
Z / 6 and Z % 6, we tried to reuse our original division result. What
we wanted was Z - (Z/6) * 6, but instead we botched it and wrote Z-Z*6
which produced...totally invalid cube faces.
Fixes: fe81d40bff ("intel/nir: add lower for sparse images & textures")
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Tested-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24481>
