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nir: Drop most instances of nir_ssa_dest_init()

Browse source 
Generated using the following two semantic patches:

    @@
    expression I, J, NC, BS;
    @@

    -nir_ssa_dest_init(I, &J->dest, NC, BS);
    +nir_def_init(I, &J->dest.ssa, NC, BS);

    @@
    expression I, J, NC, BS;
    @@

    -nir_ssa_dest_init(I, &J->dest.dest, NC, BS);
    +nir_def_init(I, &J->dest.dest.ssa, NC, BS);

Acked-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24658>
This commit is contained in:
Faith Ekstrand 2023-08-12 18:31:52 -05:00 • committed by Marge Bot
parent 7bcbfae87c
commit ed9affa02f
107 changed files with 333 additions and 360 deletions
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5
src/amd/common/ac_nir_lower_global_access.c
View file

@ -98,9 +98,8 @@ process_instr(nir_builder *b, nir_instr *instr, void *_)
new_intrin->num_components = intrin->num_components;
if (op != nir_intrinsic_store_global_amd)
nir_ssa_dest_init(&new_intrin->instr, &new_intrin->dest,
intrin->dest.ssa.num_components,
intrin->dest.ssa.bit_size);
nir_def_init(&new_intrin->instr, &new_intrin->dest.ssa,
intrin->dest.ssa.num_components, intrin->dest.ssa.bit_size);
unsigned num_src = nir_intrinsic_infos[intrin->intrinsic].num_srcs;
for (unsigned i = 0; i < num_src; i++)

8
src/amd/common/ac_nir_lower_image_opcodes_cdna.c
View file

@ -400,8 +400,8 @@ static bool lower_image_opcodes(nir_builder *b, nir_instr *instr, void *data)
new_tex->dest_type = nir_type_int32;
nir_src_copy(&new_tex->src[0].src, &tex->src[i].src, &new_tex->instr);
new_tex->src[0].src_type = tex->src[i].src_type;
nir_ssa_dest_init(&new_tex->instr, &new_tex->dest,
nir_tex_instr_dest_size(new_tex), 32);
nir_def_init(&new_tex->instr, &new_tex->dest.ssa,
nir_tex_instr_dest_size(new_tex), 32);
nir_builder_instr_insert(b, &new_tex->instr);
desc = &new_tex->dest.ssa;
break;
@ -419,8 +419,8 @@ static bool lower_image_opcodes(nir_builder *b, nir_instr *instr, void *data)
new_tex->dest_type = nir_type_int32;
nir_src_copy(&new_tex->src[0].src, &tex->src[i].src, &new_tex->instr);
new_tex->src[0].src_type = tex->src[i].src_type;
nir_ssa_dest_init(&new_tex->instr, &new_tex->dest,
nir_tex_instr_dest_size(new_tex), 32);
nir_def_init(&new_tex->instr, &new_tex->dest.ssa,
nir_tex_instr_dest_size(new_tex), 32);
nir_builder_instr_insert(b, &new_tex->instr);
sampler_desc = &new_tex->dest.ssa;
break;

4
src/amd/common/ac_nir_lower_resinfo.c
View file

@ -288,8 +288,8 @@ static bool lower_resinfo(nir_builder *b, nir_instr *instr, void *data)
new_tex->dest_type = nir_type_int32;
nir_src_copy(&new_tex->src[0].src, &tex->src[i].src, &new_tex->instr);
new_tex->src[0].src_type = tex->src[i].src_type;
nir_ssa_dest_init(&new_tex->instr, &new_tex->dest,
nir_tex_instr_dest_size(new_tex), 32);
nir_def_init(&new_tex->instr, &new_tex->dest.ssa,
nir_tex_instr_dest_size(new_tex), 32);
nir_builder_instr_insert(b, &new_tex->instr);
desc = &new_tex->dest.ssa;
break;

4
src/asahi/compiler/agx_nir_lower_texture.c
View file

@ -419,7 +419,7 @@ bias_for_tex(nir_builder *b, nir_tex_instr *tex)
query->op = nir_texop_lod_bias_agx;
query->dest_type = nir_type_float16;
nir_ssa_dest_init(instr, &query->dest, 1, 16);
nir_def_init(instr, &query->dest.ssa, 1, 16);
return &query->dest.ssa;
}
@ -548,7 +548,7 @@ txs_for_image(nir_builder *b, nir_intrinsic_instr *intr,
nir_tex_src_for_ssa(nir_tex_src_texture_offset, intr->src[0].ssa);
}
nir_ssa_dest_init(&tex->instr, &tex->dest, num_components, bit_size);
nir_def_init(&tex->instr, &tex->dest.ssa, num_components, bit_size);
nir_builder_instr_insert(b, &tex->instr);
return &tex->dest.ssa;
}

2
src/asahi/lib/agx_meta.c
View file

@ -57,7 +57,7 @@ build_background_op(nir_builder *b, enum agx_meta_op op, unsigned rt,
tex->coord_components = 2;
tex->texture_index = rt;
nir_ssa_dest_init(&tex->instr, &tex->dest, 4, 32);
nir_def_init(&tex->instr, &tex->dest.ssa, 4, 32);
nir_builder_instr_insert(b, &tex->instr);
return nir_trim_vector(b, &tex->dest.ssa, nr);

4
src/broadcom/compiler/v3d_nir_lower_load_store_bitsize.c
View file

@ -153,8 +153,8 @@ lower_load_bitsize(nir_builder *b,
}
}
nir_ssa_dest_init(&new_intr->instr, &new_intr->dest, 1,
bit_size);
nir_def_init(&new_intr->instr, &new_intr->dest.ssa, 1,
bit_size);
dest_components[component] = &new_intr->dest.ssa;
nir_builder_instr_insert(b, &new_intr->instr);

4
src/broadcom/compiler/v3d_nir_lower_scratch.c
View file

@ -65,8 +65,8 @@ v3d_nir_lower_load_scratch(nir_builder *b, nir_intrinsic_instr *instr)
nir_intrinsic_instr *chan_instr =
nir_intrinsic_instr_create(b->shader, instr->intrinsic);
chan_instr->num_components = 1;
nir_ssa_dest_init(&chan_instr->instr, &chan_instr->dest, 1,
instr->dest.ssa.bit_size);
nir_def_init(&chan_instr->instr, &chan_instr->dest.ssa, 1,
instr->dest.ssa.bit_size);
chan_instr->src[0] = nir_src_for_ssa(chan_offset);

6
src/broadcom/vulkan/v3dv_meta_copy.c
View file

@ -2332,7 +2332,7 @@ get_texel_buffer_copy_fs(struct v3dv_device *device, VkFormat format,
tex->dest_type = nir_type_uint32;
tex->is_array = false;
tex->coord_components = 1;
nir_ssa_dest_init(&tex->instr, &tex->dest, 4, 32);
nir_def_init(&tex->instr, &tex->dest.ssa, 4, 32);
nir_builder_instr_insert(&b, &tex->instr);
uint32_t swiz[4];
@ -3608,7 +3608,7 @@ build_nir_tex_op_read(struct nir_builder *b,
tex->is_array = glsl_sampler_type_is_array(sampler_type);
tex->coord_components = tex_pos->num_components;
nir_ssa_dest_init(&tex->instr, &tex->dest, 4, 32);
nir_def_init(&tex->instr, &tex->dest.ssa, 4, 32);
nir_builder_instr_insert(b, &tex->instr);
return &tex->dest.ssa;
}
@ -3631,7 +3631,7 @@ build_nir_tex_op_ms_fetch_sample(struct nir_builder *b,
tex->is_array = false;
tex->coord_components = tex_pos->num_components;
nir_ssa_dest_init(&tex->instr, &tex->dest, 4, 32);
nir_def_init(&tex->instr, &tex->dest.ssa, 4, 32);
nir_builder_instr_insert(b, &tex->instr);
return &tex->dest.ssa;
}

36
src/compiler/glsl/glsl_to_nir.cpp
View file

@ -1226,11 +1226,11 @@ nir_visitor::visit(ir_call *ir)
/* Atomic result */
assert(ir->return_deref);
if (ir->return_deref->type->is_integer_64()) {
nir_ssa_dest_init(&instr->instr, &instr->dest,
ir->return_deref->type->vector_elements, 64);
nir_def_init(&instr->instr, &instr->dest.ssa,
ir->return_deref->type->vector_elements, 64);
} else {
nir_ssa_dest_init(&instr->instr, &instr->dest,
ir->return_deref->type->vector_elements, 32);
nir_def_init(&instr->instr, &instr->dest.ssa,
ir->return_deref->type->vector_elements, 32);
}
nir_builder_instr_insert(&b, &instr->instr);
break;
@ -1255,7 +1255,7 @@ nir_visitor::visit(ir_call *ir)
/* Set the intrinsic destination. */
if (ir->return_deref) {
nir_ssa_dest_init(&instr->instr, &instr->dest, 1, 32);
nir_def_init(&instr->instr, &instr->dest.ssa, 1, 32);
}
/* Set the intrinsic parameters. */
@ -1311,7 +1311,7 @@ nir_visitor::visit(ir_call *ir)
} else
num_components = ir->return_deref->type->vector_elements;
nir_ssa_dest_init(&instr->instr, &instr->dest, num_components, 32);
nir_def_init(&instr->instr, &instr->dest.ssa, num_components, 32);
}
if (op == nir_intrinsic_image_deref_size) {
@ -1444,7 +1444,7 @@ nir_visitor::visit(ir_call *ir)
break;
}
case nir_intrinsic_shader_clock:
nir_ssa_dest_init(&instr->instr, &instr->dest, 2, 32);
nir_def_init(&instr->instr, &instr->dest.ssa, 2, 32);
nir_intrinsic_set_memory_scope(instr, SCOPE_SUBGROUP);
nir_builder_instr_insert(&b, &instr->instr);
break;
@ -1495,8 +1495,8 @@ nir_visitor::visit(ir_call *ir)
/* Setup destination register */
unsigned bit_size = type->is_boolean() ? 32 : glsl_get_bit_size(type);
nir_ssa_dest_init(&instr->instr, &instr->dest, type->vector_elements,
bit_size);
nir_def_init(&instr->instr, &instr->dest.ssa, type->vector_elements,
bit_size);
nir_builder_instr_insert(&b, &instr->instr);
@ -1538,7 +1538,7 @@ nir_visitor::visit(ir_call *ir)
FALLTHROUGH;
case nir_intrinsic_vote_any:
case nir_intrinsic_vote_all: {
nir_ssa_dest_init(&instr->instr, &instr->dest, 1, 1);
nir_def_init(&instr->instr, &instr->dest.ssa, 1, 1);
ir_rvalue *value = (ir_rvalue *) ir->actual_parameters.get_head();
instr->src[0] = nir_src_for_ssa(evaluate_rvalue(value));
@ -1548,8 +1548,8 @@ nir_visitor::visit(ir_call *ir)
}
case nir_intrinsic_ballot: {
nir_ssa_dest_init(&instr->instr, &instr->dest,
ir->return_deref->type->vector_elements, 64);
nir_def_init(&instr->instr, &instr->dest.ssa,
ir->return_deref->type->vector_elements, 64);
instr->num_components = ir->return_deref->type->vector_elements;
ir_rvalue *value = (ir_rvalue *) ir->actual_parameters.get_head();
@ -1559,8 +1559,8 @@ nir_visitor::visit(ir_call *ir)
break;
}
case nir_intrinsic_read_invocation: {
nir_ssa_dest_init(&instr->instr, &instr->dest,
ir->return_deref->type->vector_elements, 32);
nir_def_init(&instr->instr, &instr->dest.ssa,
ir->return_deref->type->vector_elements, 32);
instr->num_components = ir->return_deref->type->vector_elements;
ir_rvalue *value = (ir_rvalue *) ir->actual_parameters.get_head();
@ -1573,8 +1573,8 @@ nir_visitor::visit(ir_call *ir)
break;
}
case nir_intrinsic_read_first_invocation: {
nir_ssa_dest_init(&instr->instr, &instr->dest,
ir->return_deref->type->vector_elements, 32);
nir_def_init(&instr->instr, &instr->dest.ssa,
ir->return_deref->type->vector_elements, 32);
instr->num_components = ir->return_deref->type->vector_elements;
ir_rvalue *value = (ir_rvalue *) ir->actual_parameters.get_head();
@ -1584,12 +1584,12 @@ nir_visitor::visit(ir_call *ir)
break;
}
case nir_intrinsic_is_helper_invocation: {
nir_ssa_dest_init(&instr->instr, &instr->dest, 1, 1);
nir_def_init(&instr->instr, &instr->dest.ssa, 1, 1);
nir_builder_instr_insert(&b, &instr->instr);
break;
}
case nir_intrinsic_is_sparse_texels_resident: {
nir_ssa_dest_init(&instr->instr, &instr->dest, 1, 1);
nir_def_init(&instr->instr, &instr->dest.ssa, 1, 1);
ir_rvalue *value = (ir_rvalue *) ir->actual_parameters.get_head();
instr->src[0] = nir_src_for_ssa(evaluate_rvalue(value));

18
src/compiler/nir/nir_builder.c
View file

@ -113,8 +113,8 @@ nir_builder_alu_instr_finish_and_insert(nir_builder *build, nir_alu_instr *instr
}
}
nir_ssa_dest_init(&instr->instr, &instr->dest.dest, num_components,
bit_size);
nir_def_init(&instr->instr, &instr->dest.dest.ssa, num_components,
bit_size);
nir_builder_instr_insert(build, &instr->instr);
@ -304,8 +304,8 @@ nir_build_tex_deref_instr(nir_builder *build, nir_texop op,
}
assert(src_idx == num_srcs);
nir_ssa_dest_init(&tex->instr, &tex->dest, nir_tex_instr_dest_size(tex),
nir_alu_type_get_type_size(tex->dest_type));
nir_def_init(&tex->instr, &tex->dest.ssa, nir_tex_instr_dest_size(tex),
nir_alu_type_get_type_size(tex->dest_type));
nir_builder_instr_insert(build, &tex->instr);
return &tex->dest.ssa;
@ -328,8 +328,8 @@ nir_vec_scalars(nir_builder *build, nir_scalar *comp, unsigned num_components)
/* Note: not reusing nir_builder_alu_instr_finish_and_insert() because it
* can't re-guess the num_components when num_components == 1 (nir_op_mov).
*/
nir_ssa_dest_init(&instr->instr, &instr->dest.dest, num_components,
comp[0].def->bit_size);
nir_def_init(&instr->instr, &instr->dest.dest.ssa, num_components,
comp[0].def->bit_size);
nir_builder_instr_insert(build, &instr->instr);
@ -385,7 +385,7 @@ nir_load_system_value(nir_builder *build, nir_intrinsic_op op, int index,
load->num_components = num_components;
load->const_index[0] = index;
nir_ssa_dest_init(&load->instr, &load->dest, num_components, bit_size);
nir_def_init(&load->instr, &load->dest.ssa, num_components, bit_size);
nir_builder_instr_insert(build, &load->instr);
return &load->dest.ssa;
}
@ -472,8 +472,8 @@ nir_if_phi(nir_builder *build, nir_def *then_def, nir_def *else_def)
assert(then_def->num_components == else_def->num_components);
assert(then_def->bit_size == else_def->bit_size);
nir_ssa_dest_init(&phi->instr, &phi->dest, then_def->num_components,
then_def->bit_size);
nir_def_init(&phi->instr, &phi->dest.ssa, then_def->num_components,
then_def->bit_size);
nir_builder_instr_insert(build, &phi->instr);

41
src/compiler/nir/nir_builder.h
View file

@ -1298,8 +1298,8 @@ nir_build_deref_var(nir_builder *build, nir_variable *var)
deref->type = var->type;
deref->var = var;
nir_ssa_dest_init(&deref->instr, &deref->dest, 1,
nir_get_ptr_bitsize(build->shader));
nir_def_init(&deref->instr, &deref->dest.ssa, 1,
nir_get_ptr_bitsize(build->shader));
nir_builder_instr_insert(build, &deref->instr);
@ -1324,9 +1324,8 @@ nir_build_deref_array(nir_builder *build, nir_deref_instr *parent,
deref->parent = nir_src_for_ssa(&parent->dest.ssa);
deref->arr.index = nir_src_for_ssa(index);
nir_ssa_dest_init(&deref->instr, &deref->dest,
parent->dest.ssa.num_components,
parent->dest.ssa.bit_size);
nir_def_init(&deref->instr, &deref->dest.ssa,
parent->dest.ssa.num_components, parent->dest.ssa.bit_size);
nir_builder_instr_insert(build, &deref->instr);
@ -1361,9 +1360,8 @@ nir_build_deref_ptr_as_array(nir_builder *build, nir_deref_instr *parent,
deref->parent = nir_src_for_ssa(&parent->dest.ssa);
deref->arr.index = nir_src_for_ssa(index);
nir_ssa_dest_init(&deref->instr, &deref->dest,
parent->dest.ssa.num_components,
parent->dest.ssa.bit_size);
nir_def_init(&deref->instr, &deref->dest.ssa,
parent->dest.ssa.num_components, parent->dest.ssa.bit_size);
nir_builder_instr_insert(build, &deref->instr);
@ -1383,9 +1381,8 @@ nir_build_deref_array_wildcard(nir_builder *build, nir_deref_instr *parent)
deref->type = glsl_get_array_element(parent->type);
deref->parent = nir_src_for_ssa(&parent->dest.ssa);
nir_ssa_dest_init(&deref->instr, &deref->dest,
parent->dest.ssa.num_components,
parent->dest.ssa.bit_size);
nir_def_init(&deref->instr, &deref->dest.ssa,
parent->dest.ssa.num_components, parent->dest.ssa.bit_size);
nir_builder_instr_insert(build, &deref->instr);
@ -1406,9 +1403,8 @@ nir_build_deref_struct(nir_builder *build, nir_deref_instr *parent,
deref->parent = nir_src_for_ssa(&parent->dest.ssa);
deref->strct.index = index;
nir_ssa_dest_init(&deref->instr, &deref->dest,
parent->dest.ssa.num_components,
parent->dest.ssa.bit_size);
nir_def_init(&deref->instr, &deref->dest.ssa,
parent->dest.ssa.num_components, parent->dest.ssa.bit_size);
nir_builder_instr_insert(build, &deref->instr);
@ -1428,8 +1424,8 @@ nir_build_deref_cast(nir_builder *build, nir_def *parent,
deref->parent = nir_src_for_ssa(parent);
deref->cast.ptr_stride = ptr_stride;
nir_ssa_dest_init(&deref->instr, &deref->dest, parent->num_components,
parent->bit_size);
nir_def_init(&deref->instr, &deref->dest.ssa, parent->num_components,
parent->bit_size);
nir_builder_instr_insert(build, &deref->instr);
@ -1450,9 +1446,8 @@ nir_alignment_deref_cast(nir_builder *build, nir_deref_instr *parent,
deref->cast.align_mul = align_mul;
deref->cast.align_offset = align_offset;
nir_ssa_dest_init(&deref->instr, &deref->dest,
parent->dest.ssa.num_components,
parent->dest.ssa.bit_size);
nir_def_init(&deref->instr, &deref->dest.ssa,
parent->dest.ssa.num_components, parent->dest.ssa.bit_size);
nir_builder_instr_insert(build, &deref->instr);
@ -1645,7 +1640,7 @@ nir_load_global(nir_builder *build, nir_def *addr, unsigned align,
load->num_components = num_components;
load->src[0] = nir_src_for_ssa(addr);
nir_intrinsic_set_align(load, align, 0);
nir_ssa_dest_init(&load->instr, &load->dest, num_components, bit_size);
nir_def_init(&load->instr, &load->dest.ssa, num_components, bit_size);
nir_builder_instr_insert(build, &load->instr);
return &load->dest.ssa;
}
@ -1676,7 +1671,7 @@ nir_load_global_constant(nir_builder *build, nir_def *addr, unsigned align,
load->num_components = num_components;
load->src[0] = nir_src_for_ssa(addr);
nir_intrinsic_set_align(load, align, 0);
nir_ssa_dest_init(&load->instr, &load->dest, num_components, bit_size);
nir_def_init(&load->instr, &load->dest.ssa, num_components, bit_size);
nir_builder_instr_insert(build, &load->instr);
return &load->dest.ssa;
}
@ -1701,7 +1696,7 @@ nir_decl_reg(nir_builder *b, unsigned num_components, unsigned bit_size,
nir_intrinsic_set_bit_size(decl, bit_size);
nir_intrinsic_set_num_array_elems(decl, num_array_elems);
nir_intrinsic_set_divergent(decl, true);
nir_ssa_dest_init(&decl->instr, &decl->dest, 1, 32);
nir_def_init(&decl->instr, &decl->dest.ssa, 1, 32);
nir_instr_insert(nir_before_cf_list(&b->impl->body), &decl->instr);
@ -1878,7 +1873,7 @@ nir_load_barycentric(nir_builder *build, nir_intrinsic_op op,
{
unsigned num_components = op == nir_intrinsic_load_barycentric_model ? 3 : 2;
nir_intrinsic_instr *bary = nir_intrinsic_instr_create(build->shader, op);
nir_ssa_dest_init(&bary->instr, &bary->dest, num_components, 32);
nir_def_init(&bary->instr, &bary->dest.ssa, num_components, 32);
nir_intrinsic_set_interp_mode(bary, interp_mode);
nir_builder_instr_insert(build, &bary->instr);
return &bary->dest.ssa;

5
src/compiler/nir/nir_builtin_builder.c
View file

@ -373,8 +373,7 @@ nir_get_texture_size(nir_builder *b, nir_tex_instr *tex)
/* Add in an LOD because some back-ends require it */
txs->src[idx] = nir_tex_src_for_ssa(nir_tex_src_lod, nir_imm_int(b, 0));
nir_ssa_dest_init(&txs->instr, &txs->dest, nir_tex_instr_dest_size(txs),
32);
nir_def_init(&txs->instr, &txs->dest.ssa, nir_tex_instr_dest_size(txs), 32);
nir_builder_instr_insert(b, &txs->instr);
return &txs->dest.ssa;
@ -425,7 +424,7 @@ nir_get_texture_lod(nir_builder *b, nir_tex_instr *tex)
}
}
nir_ssa_dest_init(&tql->instr, &tql->dest, 2, 32);
nir_def_init(&tql->instr, &tql->dest.ssa, 2, 32);
nir_builder_instr_insert(b, &tql->instr);
/* The LOD is the y component of the result */

4
src/compiler/nir/nir_deref.c
View file

@ -806,8 +806,8 @@ rematerialize_deref_in_block(nir_deref_instr *deref,
unreachable("Invalid deref instruction type");
}
nir_ssa_dest_init(&new_deref->instr, &new_deref->dest,
deref->dest.ssa.num_components, deref->dest.ssa.bit_size);
nir_def_init(&new_deref->instr, &new_deref->dest.ssa,
deref->dest.ssa.num_components, deref->dest.ssa.bit_size);
nir_builder_instr_insert(b, &new_deref->instr);
return new_deref;

9
src/compiler/nir/nir_from_ssa.c
View file

@ -401,9 +401,8 @@ isolate_phi_nodes_block(nir_shader *shader, nir_block *block, void *dead_ctx)
nir_parallel_copy_entry);
entry->src_is_reg = false;
entry->dest_is_reg = false;
nir_ssa_dest_init(&pcopy->instr, &entry->dest.dest,
phi->dest.ssa.num_components,
phi->dest.ssa.bit_size);
nir_def_init(&pcopy->instr, &entry->dest.dest.ssa,
phi->dest.ssa.num_components, phi->dest.ssa.bit_size);
entry->dest.dest.ssa.divergent = nir_src_is_divergent(src->src);
exec_list_push_tail(&pcopy->entries, &entry->node);
@ -417,8 +416,8 @@ isolate_phi_nodes_block(nir_shader *shader, nir_block *block, void *dead_ctx)
nir_parallel_copy_entry);
entry->src_is_reg = false;
entry->dest_is_reg = false;
nir_ssa_dest_init(&block_pcopy->instr, &entry->dest.dest,
phi->dest.ssa.num_components, phi->dest.ssa.bit_size);
nir_def_init(&block_pcopy->instr, &entry->dest.dest.ssa,
phi->dest.ssa.num_components, phi->dest.ssa.bit_size);
entry->dest.dest.ssa.divergent = phi->dest.ssa.divergent;
exec_list_push_tail(&block_pcopy->entries, &entry->node);

2
src/compiler/nir/nir_lower_alu_width.c
View file

@ -89,7 +89,7 @@ static void
nir_alu_ssa_dest_init(nir_alu_instr *alu, unsigned num_components,
unsigned bit_size)
{
nir_ssa_dest_init(&alu->instr, &alu->dest.dest, num_components, bit_size);
nir_def_init(&alu->instr, &alu->dest.dest.ssa, num_components, bit_size);
}
static nir_def *

4
src/compiler/nir/nir_lower_atomics_to_ssbo.c
View file

@ -156,8 +156,8 @@ lower_instr(nir_intrinsic_instr *instr, unsigned ssbo_offset, nir_builder *b, un
new_instr->num_components = instr->dest.ssa.num_components;
}
nir_ssa_dest_init(&new_instr->instr, &new_instr->dest,
instr->dest.ssa.num_components, instr->dest.ssa.bit_size);
nir_def_init(&new_instr->instr, &new_instr->dest.ssa,
instr->dest.ssa.num_components, instr->dest.ssa.bit_size);
nir_instr_insert_before(&instr->instr, &new_instr->instr);
nir_instr_remove(&instr->instr);

6
src/compiler/nir/nir_lower_bit_size.c
View file

@ -322,10 +322,8 @@ split_phi(nir_builder *b, nir_phi_instr *phi)
nir_phi_instr_add_src(lowered[1], src->pred, nir_src_for_ssa(y));
}
nir_ssa_dest_init(&lowered[0]->instr, &lowered[0]->dest, num_components,
32);
nir_ssa_dest_init(&lowered[1]->instr, &lowered[1]->dest, num_components,
32);
nir_def_init(&lowered[0]->instr, &lowered[0]->dest.ssa, num_components, 32);
nir_def_init(&lowered[1]->instr, &lowered[1]->dest.ssa, num_components, 32);
b->cursor = nir_before_instr(&phi->instr);
nir_builder_instr_insert(b, &lowered[0]->instr);

2
src/compiler/nir/nir_lower_bitmap.c
View file

@ -86,7 +86,7 @@ lower_bitmap(nir_shader *shader, nir_builder *b,
tex->src[2] = nir_tex_src_for_ssa(nir_tex_src_coord,
nir_trim_vector(b, texcoord, tex->coord_components));
nir_ssa_dest_init(&tex->instr, &tex->dest, 4, 32);
nir_def_init(&tex->instr, &tex->dest.ssa, 4, 32);
nir_builder_instr_insert(b, &tex->instr);
/* kill if tex != 0.0.. take .x or .w channel according to format: */

6
src/compiler/nir/nir_lower_drawpixels.c
View file

@ -118,7 +118,7 @@ lower_color(nir_builder *b, lower_drawpixels_state *state, nir_intrinsic_instr *
nir_tex_src_for_ssa(nir_tex_src_coord,
nir_trim_vector(b, texcoord, tex->coord_components));
nir_ssa_dest_init(&tex->instr, &tex->dest, 4, 32);
nir_def_init(&tex->instr, &tex->dest.ssa, 4, 32);
nir_builder_instr_insert(b, &tex->instr);
def = &tex->dest.ssa;
@ -158,7 +158,7 @@ lower_color(nir_builder *b, lower_drawpixels_state *state, nir_intrinsic_instr *
tex->src[2] = nir_tex_src_for_ssa(nir_tex_src_coord,
nir_trim_vector(b, def, 2));
nir_ssa_dest_init(&tex->instr, &tex->dest, 4, 32);
nir_def_init(&tex->instr, &tex->dest.ssa, 4, 32);
nir_builder_instr_insert(b, &tex->instr);
def_xy = &tex->dest.ssa;
@ -172,7 +172,7 @@ lower_color(nir_builder *b, lower_drawpixels_state *state, nir_intrinsic_instr *
tex->src[0] = nir_tex_src_for_ssa(nir_tex_src_coord,
nir_channels(b, def, 0xc));
nir_ssa_dest_init(&tex->instr, &tex->dest, 4, 32);
nir_def_init(&tex->instr, &tex->dest.ssa, 4, 32);
nir_builder_instr_insert(b, &tex->instr);
def_zw = &tex->dest.ssa;

2
src/compiler/nir/nir_lower_fb_read.c
View file

@ -76,7 +76,7 @@ nir_lower_fb_read_instr(nir_builder *b, nir_instr *instr, UNUSED void *cb_data)
tex->src[2] = nir_tex_src_for_ssa(nir_tex_src_texture_handle,
nir_imm_intN_t(b, io.location - FRAG_RESULT_DATA0, 32));
nir_ssa_dest_init(&tex->instr, &tex->dest, 4, 32);
nir_def_init(&tex->instr, &tex->dest.ssa, 4, 32);
nir_builder_instr_insert(b, &tex->instr);
nir_def_rewrite_uses(&intr->dest.ssa, &tex->dest.ssa);

2
src/compiler/nir/nir_lower_image.c
View file

@ -149,7 +149,7 @@ lower_image_samples_identical_to_fragment_mask_load(nir_builder *b, nir_intrinsi
break;
}
nir_ssa_dest_init(&fmask_load->instr, &fmask_load->dest, 1, 32);
nir_def_init(&fmask_load->instr, &fmask_load->dest.ssa, 1, 32);
nir_builder_instr_insert(b, &fmask_load->instr);
nir_def *samples_identical = nir_ieq_imm(b, &fmask_load->dest.ssa, 0);

6
src/compiler/nir/nir_lower_indirect_derefs.c
View file

@ -100,9 +100,9 @@ emit_load_store_deref(nir_builder *b, nir_intrinsic_instr *orig_instr,
i < nir_intrinsic_infos[orig_instr->intrinsic].num_srcs; i++)
nir_src_copy(&load->src[i], &orig_instr->src[i], &load->instr);
nir_ssa_dest_init(&load->instr, &load->dest,
orig_instr->dest.ssa.num_components,
orig_instr->dest.ssa.bit_size);
nir_def_init(&load->instr, &load->dest.ssa,
orig_instr->dest.ssa.num_components,
orig_instr->dest.ssa.bit_size);
nir_builder_instr_insert(b, &load->instr);
*dest = &load->dest.ssa;
} else {

3
src/compiler/nir/nir_lower_input_attachments.c
View file

@ -135,8 +135,7 @@ try_lower_input_load(nir_builder *b, nir_intrinsic_instr *load,
tex->texture_non_uniform = nir_intrinsic_access(load) & ACCESS_NON_UNIFORM;
nir_ssa_dest_init(&tex->instr, &tex->dest, nir_tex_instr_dest_size(tex),
32);
nir_def_init(&tex->instr, &tex->dest.ssa, nir_tex_instr_dest_size(tex), 32);
nir_builder_instr_insert(b, &tex->instr);
if (tex->is_sparse) {

10
src/compiler/nir/nir_lower_int64.c
View file

@ -1171,8 +1171,8 @@ split_64bit_subgroup_op(nir_builder *b, const nir_intrinsic_instr *intrin)
memcpy(split->const_index, intrin->const_index,
sizeof(intrin->const_index));
nir_ssa_dest_init(&split->instr, &split->dest,
intrin->dest.ssa.num_components, 32);
nir_def_init(&split->instr, &split->dest.ssa,
intrin->dest.ssa.num_components, 32);
nir_builder_instr_insert(b, &split->instr);
res[i] = &split->dest.ssa;
@ -1188,7 +1188,7 @@ build_vote_ieq(nir_builder *b, nir_def *x)
nir_intrinsic_instr_create(b->shader, nir_intrinsic_vote_ieq);
vote->src[0] = nir_src_for_ssa(x);
vote->num_components = x->num_components;
nir_ssa_dest_init(&vote->instr, &vote->dest, 1, 1);
nir_def_init(&vote->instr, &vote->dest.ssa, 1, 1);
nir_builder_instr_insert(b, &vote->instr);
return &vote->dest.ssa;
}
@ -1212,8 +1212,8 @@ build_scan_intrinsic(nir_builder *b, nir_intrinsic_op scan_op,
nir_intrinsic_set_reduction_op(scan, reduction_op);
if (scan_op == nir_intrinsic_reduce)
nir_intrinsic_set_cluster_size(scan, cluster_size);
nir_ssa_dest_init(&scan->instr, &scan->dest, val->num_components,
val->bit_size);
nir_def_init(&scan->instr, &scan->dest.ssa, val->num_components,
val->bit_size);
nir_builder_instr_insert(b, &scan->instr);
return &scan->dest.ssa;
}

10
src/compiler/nir/nir_lower_io.c
View file

@ -337,7 +337,7 @@ emit_load(struct lower_io_state *state,
load->src[0] = nir_src_for_ssa(offset);
}
nir_ssa_dest_init(&load->instr, &load->dest, num_components, bit_size);
nir_def_init(&load->instr, &load->dest.ssa, num_components, bit_size);
nir_builder_instr_insert(b, &load->instr);
return &load->dest.ssa;
@ -557,7 +557,7 @@ lower_interpolate_at(nir_intrinsic_instr *intrin, struct lower_io_state *state,
nir_intrinsic_instr *bary_setup =
nir_intrinsic_instr_create(state->builder.shader, bary_op);
nir_ssa_dest_init(&bary_setup->instr, &bary_setup->dest, 2, 32);
nir_def_init(&bary_setup->instr, &bary_setup->dest.ssa, 2, 32);
nir_intrinsic_set_interp_mode(bary_setup, var->data.interpolation);
if (intrin->intrinsic == nir_intrinsic_interp_deref_at_sample ||
@ -1505,7 +1505,7 @@ build_explicit_io_load(nir_builder *b, nir_intrinsic_instr *intrin,
}
load->num_components = num_components;
nir_ssa_dest_init(&load->instr, &load->dest, num_components, bit_size);
nir_def_init(&load->instr, &load->dest.ssa, num_components, bit_size);
assert(bit_size % 8 == 0);
@ -1812,8 +1812,8 @@ build_explicit_io_atomic(nir_builder *b, nir_intrinsic_instr *intrin,
nir_intrinsic_set_access(atomic, nir_intrinsic_access(intrin));
assert(intrin->dest.ssa.num_components == 1);
nir_ssa_dest_init(&atomic->instr, &atomic->dest, 1,
intrin->dest.ssa.bit_size);
nir_def_init(&atomic->instr, &atomic->dest.ssa, 1,
intrin->dest.ssa.bit_size);
assert(atomic->dest.ssa.bit_size % 8 == 0);

4
src/compiler/nir/nir_lower_io_arrays_to_elements.c
View file

@ -171,8 +171,8 @@ lower_array(nir_builder *b, nir_intrinsic_instr *intr, nir_variable *var,
element_intr->src[0] = nir_src_for_ssa(&element_deref->dest.ssa);
if (intr->intrinsic != nir_intrinsic_store_deref) {
nir_ssa_dest_init(&element_intr->instr, &element_intr->dest,
intr->num_components, intr->dest.ssa.bit_size);
nir_def_init(&element_intr->instr, &element_intr->dest.ssa,
intr->num_components, intr->dest.ssa.bit_size);
if (intr->intrinsic == nir_intrinsic_interp_deref_at_offset ||
intr->intrinsic == nir_intrinsic_interp_deref_at_sample ||

12
src/compiler/nir/nir_lower_io_to_scalar.c
View file

@ -53,8 +53,8 @@ lower_load_input_to_scalar(nir_builder *b, nir_intrinsic_instr *intr)
unsigned newc = nir_intrinsic_component(intr);
nir_intrinsic_instr *chan_intr =
nir_intrinsic_instr_create(b->shader, intr->intrinsic);
nir_ssa_dest_init(&chan_intr->instr, &chan_intr->dest, 1,
intr->dest.ssa.bit_size);
nir_def_init(&chan_intr->instr, &chan_intr->dest.ssa, 1,
intr->dest.ssa.bit_size);
chan_intr->num_components = 1;
nir_intrinsic_set_base(chan_intr, nir_intrinsic_base(intr));
@ -92,8 +92,8 @@ lower_load_to_scalar(nir_builder *b, nir_intrinsic_instr *intr)
for (unsigned i = 0; i < intr->num_components; i++) {
nir_intrinsic_instr *chan_intr =
nir_intrinsic_instr_create(b->shader, intr->intrinsic);
nir_ssa_dest_init(&chan_intr->instr, &chan_intr->dest, 1,
intr->dest.ssa.bit_size);
nir_def_init(&chan_intr->instr, &chan_intr->dest.ssa, 1,
intr->dest.ssa.bit_size);
chan_intr->num_components = 1;
nir_intrinsic_set_align_offset(chan_intr,
@ -380,8 +380,8 @@ lower_load_to_scalar_early(nir_builder *b, nir_intrinsic_instr *intr,
nir_intrinsic_instr *chan_intr =
nir_intrinsic_instr_create(b->shader, intr->intrinsic);
nir_ssa_dest_init(&chan_intr->instr, &chan_intr->dest, 1,
intr->dest.ssa.bit_size);
nir_def_init(&chan_intr->instr, &chan_intr->dest.ssa, 1,
intr->dest.ssa.bit_size);
chan_intr->num_components = 1;
nir_deref_instr *deref = nir_build_deref_var(b, chan_var);

5
src/compiler/nir/nir_lower_io_to_temporaries.c
View file

@ -206,9 +206,8 @@ emit_interp(nir_builder *b, nir_deref_instr **old_interp_deref,
}
new_interp->num_components = interp->num_components;
nir_ssa_dest_init(&new_interp->instr, &new_interp->dest,
interp->dest.ssa.num_components,
interp->dest.ssa.bit_size);
nir_def_init(&new_interp->instr, &new_interp->dest.ssa,
interp->dest.ssa.num_components, interp->dest.ssa.bit_size);
nir_builder_instr_insert(b, &new_interp->instr);
nir_store_deref(b, temp_deref, &new_interp->dest.ssa,

2
src/compiler/nir/nir_lower_mem_access_bit_sizes.c
View file

@ -58,7 +58,7 @@ dup_mem_intrinsic(nir_builder *b, nir_intrinsic_instr *intrin,
nir_intrinsic_set_align(dup, align_mul, align_offset);
if (info->has_dest) {
nir_ssa_dest_init(&dup->instr, &dup->dest, num_components, bit_size);
nir_def_init(&dup->instr, &dup->dest.ssa, num_components, bit_size);
} else {
nir_intrinsic_set_write_mask(dup, (1 << num_components) - 1);
}

10
src/compiler/nir/nir_lower_phis_to_scalar.c
View file

@ -201,13 +201,13 @@ lower_phis_to_scalar_block(nir_block *block,
nir_op vec_op = nir_op_vec(phi->dest.ssa.num_components);
nir_alu_instr *vec = nir_alu_instr_create(state->shader, vec_op);
nir_ssa_dest_init(&vec->instr, &vec->dest.dest,
phi->dest.ssa.num_components, bit_size);
nir_def_init(&vec->instr, &vec->dest.dest.ssa,
phi->dest.ssa.num_components, bit_size);
for (unsigned i = 0; i < phi->dest.ssa.num_components; i++) {
nir_phi_instr *new_phi = nir_phi_instr_create(state->shader);
nir_ssa_dest_init(&new_phi->instr, &new_phi->dest, 1,
phi->dest.ssa.bit_size);
nir_def_init(&new_phi->instr, &new_phi->dest.ssa, 1,
phi->dest.ssa.bit_size);
vec->src[i].src = nir_src_for_ssa(&new_phi->dest.ssa);
@ -215,7 +215,7 @@ lower_phis_to_scalar_block(nir_block *block,
/* We need to insert a mov to grab the i'th component of src */
nir_alu_instr *mov = nir_alu_instr_create(state->shader,
nir_op_mov);
nir_ssa_dest_init(&mov->instr, &mov->dest.dest, 1, bit_size);
nir_def_init(&mov->instr, &mov->dest.dest.ssa, 1, bit_size);
nir_src_copy(&mov->src[0].src, &src->src, &mov->instr);
mov->src[0].swizzle[0] = i;

4
src/compiler/nir/nir_lower_readonly_images_to_tex.c
View file

@ -148,7 +148,7 @@ lower_readonly_image_instr_intrinsic(nir_builder *b, nir_intrinsic_instr *intrin
assert(num_srcs == 3);
tex->dest_type = nir_intrinsic_dest_type(intrin);
nir_ssa_dest_init(&tex->instr, &tex->dest, 4, 32);
nir_def_init(&tex->instr, &tex->dest.ssa, 4, 32);
break;
}
@ -159,7 +159,7 @@ lower_readonly_image_instr_intrinsic(nir_builder *b, nir_intrinsic_instr *intrin
assert(num_srcs == 2);
tex->dest_type = nir_type_uint32;
nir_ssa_dest_init(&tex->instr, &tex->dest, coord_components, 32);
nir_def_init(&tex->instr, &tex->dest.ssa, coord_components, 32);
break;
}

7
src/compiler/nir/nir_lower_ssbo.c
View file

@ -66,7 +66,7 @@ nir_load_ssbo_prop(nir_builder *b, nir_intrinsic_op op,
nir_intrinsic_instr *load = nir_intrinsic_instr_create(b->shader, op);
load->num_components = 1;
nir_src_copy(&load->src[0], idx, &load->instr);
nir_ssa_dest_init(&load->instr, &load->dest, 1, bitsize);
nir_def_init(&load->instr, &load->dest.ssa, 1, bitsize);
nir_builder_instr_insert(b, &load->instr);
return &load->dest.ssa;
}
@ -115,9 +115,8 @@ lower_ssbo_instr(nir_builder *b, nir_intrinsic_instr *intr)
nir_src_copy(&global->src[0], &intr->src[0], &global->instr);
nir_intrinsic_set_write_mask(global, nir_intrinsic_write_mask(intr));
} else {
nir_ssa_dest_init(&global->instr, &global->dest,
intr->dest.ssa.num_components,
intr->dest.ssa.bit_size);
nir_def_init(&global->instr, &global->dest.ssa,
intr->dest.ssa.num_components, intr->dest.ssa.bit_size);
if (is_atomic) {
nir_src_copy(&global->src[1], &intr->src[2], &global->instr);

25
src/compiler/nir/nir_lower_subgroups.c
View file

@ -40,7 +40,7 @@ lower_subgroups_64bit_split_intrinsic(nir_builder *b, nir_intrinsic_instr *intri
comp = nir_unpack_64_2x32_split_y(b, intrin->src[0].ssa);
nir_intrinsic_instr *intr = nir_intrinsic_instr_create(b->shader, intrin->intrinsic);
nir_ssa_dest_init(&intr->instr, &intr->dest, 1, 32);
nir_def_init(&intr->instr, &intr->dest.ssa, 1, 32);
intr->const_index[0] = intrin->const_index[0];
intr->const_index[1] = intrin->const_index[1];
intr->src[0] = nir_src_for_ssa(comp);
@ -117,8 +117,8 @@ lower_subgroup_op_to_scalar(nir_builder *b, nir_intrinsic_instr *intrin,
for (unsigned i = 0; i < intrin->num_components; i++) {
nir_intrinsic_instr *chan_intrin =
nir_intrinsic_instr_create(b->shader, intrin->intrinsic);
nir_ssa_dest_init(&chan_intrin->instr, &chan_intrin->dest, 1,
intrin->dest.ssa.bit_size);
nir_def_init(&chan_intrin->instr, &chan_intrin->dest.ssa, 1,
intrin->dest.ssa.bit_size);
chan_intrin->num_components = 1;
/* value */
@ -152,8 +152,8 @@ lower_vote_eq_to_scalar(nir_builder *b, nir_intrinsic_instr *intrin)
for (unsigned i = 0; i < intrin->num_components; i++) {
nir_intrinsic_instr *chan_intrin =
nir_intrinsic_instr_create(b->shader, intrin->intrinsic);
nir_ssa_dest_init(&chan_intrin->instr, &chan_intrin->dest, 1,
intrin->dest.ssa.bit_size);
nir_def_init(&chan_intrin->instr, &chan_intrin->dest.ssa, 1,
intrin->dest.ssa.bit_size);
chan_intrin->num_components = 1;
chan_intrin->src[0] = nir_src_for_ssa(nir_channel(b, value, i));
nir_builder_instr_insert(b, &chan_intrin->instr);
@ -209,9 +209,8 @@ lower_shuffle_to_swizzle(nir_builder *b, nir_intrinsic_instr *intrin,
swizzle->num_components = intrin->num_components;
nir_src_copy(&swizzle->src[0], &intrin->src[0], &swizzle->instr);
nir_intrinsic_set_swizzle_mask(swizzle, (mask << 10) | 0x1f);
nir_ssa_dest_init(&swizzle->instr, &swizzle->dest,
intrin->dest.ssa.num_components,
intrin->dest.ssa.bit_size);
nir_def_init(&swizzle->instr, &swizzle->dest.ssa,
intrin->dest.ssa.num_components, intrin->dest.ssa.bit_size);
if (options->lower_to_scalar && swizzle->num_components > 1) {
return lower_subgroup_op_to_scalar(b, swizzle, options->lower_shuffle_to_32bit);
@ -300,9 +299,8 @@ lower_to_shuffle(nir_builder *b, nir_intrinsic_instr *intrin,
shuffle->num_components = intrin->num_components;
nir_src_copy(&shuffle->src[0], &intrin->src[0], &shuffle->instr);
shuffle->src[1] = nir_src_for_ssa(index);
nir_ssa_dest_init(&shuffle->instr, &shuffle->dest,
intrin->dest.ssa.num_components,
intrin->dest.ssa.bit_size);
nir_def_init(&shuffle->instr, &shuffle->dest.ssa,
intrin->dest.ssa.num_components, intrin->dest.ssa.bit_size);
bool lower_to_32bit = options->lower_shuffle_to_32bit && is_shuffle;
if (options->lower_to_scalar && shuffle->num_components > 1) {
@ -584,9 +582,8 @@ lower_dynamic_quad_broadcast(nir_builder *b, nir_intrinsic_instr *intrin,
qbcst->num_components = intrin->num_components;
qbcst->src[1] = nir_src_for_ssa(nir_imm_int(b, i));
nir_src_copy(&qbcst->src[0], &intrin->src[0], &qbcst->instr);
nir_ssa_dest_init(&qbcst->instr, &qbcst->dest,
intrin->dest.ssa.num_components,
intrin->dest.ssa.bit_size);
nir_def_init(&qbcst->instr, &qbcst->dest.ssa,
intrin->dest.ssa.num_components, intrin->dest.ssa.bit_size);
nir_def *qbcst_dst = NULL;

24
src/compiler/nir/nir_lower_tex.c
View file

@ -321,8 +321,8 @@ sample_plane(nir_builder *b, nir_tex_instr *tex, int plane,
plane_tex->texture_index = tex->texture_index;
plane_tex->sampler_index = tex->sampler_index;
nir_ssa_dest_init(&plane_tex->instr, &plane_tex->dest, 4,
nir_dest_bit_size(tex->dest));
nir_def_init(&plane_tex->instr, &plane_tex->dest.ssa, 4,
nir_dest_bit_size(tex->dest));
nir_builder_instr_insert(b, &plane_tex->instr);
@ -886,9 +886,9 @@ lower_tex_to_txd(nir_builder *b, nir_tex_instr *tex)
txd->src[tex->num_srcs] = nir_tex_src_for_ssa(nir_tex_src_ddx, dfdx);
txd->src[tex->num_srcs + 1] = nir_tex_src_for_ssa(nir_tex_src_ddy, dfdy);
nir_ssa_dest_init(&txd->instr, &txd->dest,
nir_dest_num_components(tex->dest),
nir_dest_bit_size(tex->dest));
nir_def_init(&txd->instr, &txd->dest.ssa,
nir_dest_num_components(tex->dest),
nir_dest_bit_size(tex->dest));
nir_builder_instr_insert(b, &txd->instr);
nir_def_rewrite_uses(&tex->dest.ssa, &txd->dest.ssa);
nir_instr_remove(&tex->instr);
@ -926,9 +926,9 @@ lower_txb_to_txl(nir_builder *b, nir_tex_instr *tex)
lod = nir_fadd(b, nir_channel(b, lod, 1), nir_ssa_for_src(b, tex->src[bias_idx].src, 1));
txl->src[tex->num_srcs - 1] = nir_tex_src_for_ssa(nir_tex_src_lod, lod);
nir_ssa_dest_init(&txl->instr, &txl->dest,
nir_dest_num_components(tex->dest),
nir_dest_bit_size(tex->dest));
nir_def_init(&txl->instr, &txl->dest.ssa,
nir_dest_num_components(tex->dest),
nir_dest_bit_size(tex->dest));
nir_builder_instr_insert(b, &txl->instr);
nir_def_rewrite_uses(&tex->dest.ssa, &txl->dest.ssa);
nir_instr_remove(&tex->instr);
@ -1219,8 +1219,8 @@ lower_tg4_offsets(nir_builder *b, nir_tex_instr *tex)
nir_tex_src src = nir_tex_src_for_ssa(nir_tex_src_offset, offset);
tex_copy->src[tex_copy->num_srcs - 1] = src;
nir_ssa_dest_init(&tex_copy->instr, &tex_copy->dest,
nir_tex_instr_dest_size(tex), 32);
nir_def_init(&tex_copy->instr, &tex_copy->dest.ssa,
nir_tex_instr_dest_size(tex), 32);
nir_builder_instr_insert(b, &tex_copy->instr);
@ -1341,7 +1341,7 @@ nir_lower_ms_txf_to_fragment_fetch(nir_builder *b, nir_tex_instr *tex)
fmask_fetch->is_array = tex->is_array;
fmask_fetch->texture_non_uniform = tex->texture_non_uniform;
fmask_fetch->dest_type = nir_type_uint32;
nir_ssa_dest_init(&fmask_fetch->instr, &fmask_fetch->dest, 1, 32);
nir_def_init(&fmask_fetch->instr, &fmask_fetch->dest.ssa, 1, 32);
fmask_fetch->num_srcs = 0;
for (unsigned i = 0; i < tex->num_srcs; i++) {
@ -1374,7 +1374,7 @@ nir_lower_samples_identical_to_fragment_fetch(nir_builder *b, nir_tex_instr *tex
nir_tex_instr *fmask_fetch = nir_instr_as_tex(nir_instr_clone(b->shader, &tex->instr));
fmask_fetch->op = nir_texop_fragment_mask_fetch_amd;
fmask_fetch->dest_type = nir_type_uint32;
nir_ssa_dest_init(&fmask_fetch->instr, &fmask_fetch->dest, 1, 32);
nir_def_init(&fmask_fetch->instr, &fmask_fetch->dest.ssa, 1, 32);
nir_builder_instr_insert(b, &fmask_fetch->instr);
nir_def_rewrite_uses(&tex->dest.ssa, nir_ieq_imm(b, &fmask_fetch->dest.ssa, 0));

2
src/compiler/nir/nir_lower_tex_shadow.c
View file

@ -97,7 +97,7 @@ nir_lower_tex_shadow_impl(nir_builder *b, nir_instr *instr, void *options)
}
/* NIR expects a vec4 result from the above texture instructions */
nir_ssa_dest_init(&tex->instr, &tex->dest, 4, 32);
nir_def_init(&tex->instr, &tex->dest.ssa, 4, 32);
nir_def *tex_r = nir_channel(b, &tex->dest.ssa, 0);
nir_def *cmp = tex->src[comp_index].src.ssa;

5
src/compiler/nir/nir_lower_vars_to_ssa.c
View file

@ -602,9 +602,8 @@ rename_variables(struct lower_variables_state *state)
for (unsigned i = intrin->num_components; i < NIR_MAX_VEC_COMPONENTS; i++)
mov->src[0].swizzle[i] = 0;
nir_ssa_dest_init(&mov->instr, &mov->dest.dest,
intrin->num_components,
intrin->dest.ssa.bit_size);
nir_def_init(&mov->instr, &mov->dest.dest.ssa,
intrin->num_components, intrin->dest.ssa.bit_size);
nir_instr_insert_before(&intrin->instr, &mov->instr);
nir_instr_remove(&intrin->instr);

4
src/compiler/nir/nir_lower_vec_to_regs.c
View file

@ -176,8 +176,8 @@ try_coalesce(nir_builder *b, nir_def *reg, nir_alu_instr *vec,
*/
unsigned bit_size = nir_dest_bit_size(vec->dest.dest);
assert(bit_size == src_alu->dest.dest.ssa.bit_size);
nir_ssa_dest_init(&src_alu->instr, &src_alu->dest.dest,
dest_components, bit_size);
nir_def_init(&src_alu->instr, &src_alu->dest.dest.ssa, dest_components,
bit_size);
/* Then we can store that ALU result directly into the register */
b->cursor = nir_after_instr(&src_alu->instr);

12
src/compiler/nir/nir_opt_comparison_pre.c
View file

@ -199,17 +199,17 @@ rewrite_compare_instruction(nir_builder *bld, nir_alu_instr *orig_cmp,
* nir_search.c).
*/
nir_alu_instr *mov_add = nir_alu_instr_create(bld->shader, nir_op_mov);
nir_ssa_dest_init(&mov_add->instr, &mov_add->dest.dest,
orig_add->dest.dest.ssa.num_components,
orig_add->dest.dest.ssa.bit_size);
nir_def_init(&mov_add->instr, &mov_add->dest.dest.ssa,
orig_add->dest.dest.ssa.num_components,
orig_add->dest.dest.ssa.bit_size);
mov_add->src[0].src = nir_src_for_ssa(fadd);
nir_builder_instr_insert(bld, &mov_add->instr);
nir_alu_instr *mov_cmp = nir_alu_instr_create(bld->shader, nir_op_mov);
nir_ssa_dest_init(&mov_cmp->instr, &mov_cmp->dest.dest,
orig_cmp->dest.dest.ssa.num_components,
orig_cmp->dest.dest.ssa.bit_size);
nir_def_init(&mov_cmp->instr, &mov_cmp->dest.dest.ssa,
orig_cmp->dest.dest.ssa.num_components,
orig_cmp->dest.dest.ssa.bit_size);
mov_cmp->src[0].src = nir_src_for_ssa(cmp);
nir_builder_instr_insert(bld, &mov_cmp->instr);

16
src/compiler/nir/nir_opt_if.c
View file

@ -499,8 +499,8 @@ opt_split_alu_of_phi(nir_builder *b, nir_loop *loop)
nir_phi_instr_add_src(phi, prev_block, nir_src_for_ssa(prev_value));
nir_phi_instr_add_src(phi, continue_block, nir_src_for_ssa(alu_copy));
nir_ssa_dest_init(&phi->instr, &phi->dest, alu_copy->num_components,
alu_copy->bit_size);
nir_def_init(&phi->instr, &phi->dest.ssa, alu_copy->num_components,
alu_copy->bit_size);
b->cursor = nir_after_phis(header_block);
nir_builder_instr_insert(b, &phi->instr);
@ -663,9 +663,9 @@ opt_simplify_bcsel_of_phi(nir_builder *b, nir_loop *loop)
continue_block)
->src);
nir_ssa_dest_init(&phi->instr, &phi->dest,
nir_dest_num_components(bcsel->dest.dest),
nir_dest_bit_size(bcsel->dest.dest));
nir_def_init(&phi->instr, &phi->dest.ssa,
nir_dest_num_components(bcsel->dest.dest),
nir_dest_bit_size(bcsel->dest.dest));
b->cursor = nir_after_phis(header_block);
nir_builder_instr_insert(b, &phi->instr);
@ -1184,9 +1184,9 @@ clone_alu_and_replace_src_defs(nir_builder *b, const nir_alu_instr *alu,
nir_alu_instr *nalu = nir_alu_instr_create(b->shader, alu->op);
nalu->exact = alu->exact;
nir_ssa_dest_init(&nalu->instr, &nalu->dest.dest,
alu->dest.dest.ssa.num_components,
alu->dest.dest.ssa.bit_size);
nir_def_init(&nalu->instr, &nalu->dest.dest.ssa,
alu->dest.dest.ssa.num_components,
alu->dest.dest.ssa.bit_size);
for (unsigned i = 0; i < nir_op_infos[alu->op].num_inputs; i++) {
nalu->src[i].src = nir_src_for_ssa(src_defs[i]);

4
src/compiler/nir/nir_opt_peephole_select.c
View file

@ -457,8 +457,8 @@ nir_opt_peephole_select_block(nir_block *block, nir_shader *shader,
nir_src_copy(&sel->src[idx].src, &src->src, &sel->instr);
}
nir_ssa_dest_init(&sel->instr, &sel->dest.dest,
phi->dest.ssa.num_components, phi->dest.ssa.bit_size);
nir_def_init(&sel->instr, &sel->dest.dest.ssa,
phi->dest.ssa.num_components, phi->dest.ssa.bit_size);
nir_def_rewrite_uses(&phi->dest.ssa,
&sel->dest.dest.ssa);

10
src/compiler/nir/nir_opt_phi_precision.c
View file

@ -230,9 +230,9 @@ try_move_narrowing_dst(nir_builder *b, nir_phi_instr *phi)
/* construct replacement phi instruction: */
nir_phi_instr *new_phi = nir_phi_instr_create(b->shader);
nir_ssa_dest_init(&new_phi->instr, &new_phi->dest,
phi->dest.ssa.num_components,
nir_alu_type_get_type_size(nir_op_infos[op].output_type));
nir_def_init(&new_phi->instr, &new_phi->dest.ssa,
phi->dest.ssa.num_components,
nir_alu_type_get_type_size(nir_op_infos[op].output_type));
/* Push the conversion into the new phi sources: */
nir_foreach_phi_src(src, phi) {
@ -374,8 +374,8 @@ try_move_widening_src(nir_builder *b, nir_phi_instr *phi)
/* construct replacement phi instruction: */
nir_phi_instr *new_phi = nir_phi_instr_create(b->shader);
nir_ssa_dest_init(&new_phi->instr, &new_phi->dest,
phi->dest.ssa.num_components, bit_size);
nir_def_init(&new_phi->instr, &new_phi->dest.ssa,
phi->dest.ssa.num_components, bit_size);
/* Remove the widening conversions from the phi sources: */
nir_foreach_phi_src(src, phi) {

4
src/compiler/nir/nir_opt_uniform_atomics.c
View file

@ -287,8 +287,8 @@ optimize_and_rewrite_atomic(nir_builder *b, nir_intrinsic_instr *intrin)
nir_def old_result = intrin->dest.ssa;
list_replace(&intrin->dest.ssa.uses, &old_result.uses);
nir_ssa_dest_init(&intrin->instr, &intrin->dest, 1,
intrin->dest.ssa.bit_size);
nir_def_init(&intrin->instr, &intrin->dest.ssa, 1,
intrin->dest.ssa.bit_size);
nir_def *result = optimize_atomic(b, intrin, return_prev);

4
src/compiler/nir/nir_opt_vectorize.c
View file

@ -194,8 +194,8 @@ instr_try_combine(struct set *instr_set, nir_instr *instr1, nir_instr *instr2)
nir_builder b = nir_builder_at(nir_after_instr(instr1));
nir_alu_instr *new_alu = nir_alu_instr_create(b.shader, alu1->op);
nir_ssa_dest_init(&new_alu->instr, &new_alu->dest.dest, total_components,
alu1->dest.dest.ssa.bit_size);
nir_def_init(&new_alu->instr, &new_alu->dest.dest.ssa, total_components,
alu1->dest.dest.ssa.bit_size);
new_alu->instr.pass_flags = alu1->instr.pass_flags;
/* If either channel is exact, we have to preserve it even if it's

4
src/compiler/nir/nir_phi_builder.c
View file

@ -232,8 +232,8 @@ nir_phi_builder_value_get_block_def(struct nir_phi_builder_value *val,
* be used.
*/
nir_phi_instr *phi = nir_phi_instr_create(val->builder->shader);
nir_ssa_dest_init(&phi->instr, &phi->dest, val->num_components,
val->bit_size);
nir_def_init(&phi->instr, &phi->dest.ssa, val->num_components,
val->bit_size);
phi->instr.block = dom;
exec_list_push_tail(&val->phis, &phi->instr.node);
def = &phi->dest.ssa;

4
src/compiler/nir/nir_repair_ssa.c
View file

@ -126,8 +126,8 @@ repair_ssa_def(nir_def *def, void *void_state)
cast->parent = nir_src_for_ssa(block_def);
cast->cast.ptr_stride = nir_deref_instr_array_stride(deref);
nir_ssa_dest_init(&cast->instr, &cast->dest, def->num_components,
def->bit_size);
nir_def_init(&cast->instr, &cast->dest.ssa, def->num_components,
def->bit_size);
nir_instr_insert(nir_before_instr(src->parent_instr),
&cast->instr);
block_def = &cast->dest.ssa;

4
src/compiler/nir/nir_search.c
View file

@ -451,8 +451,8 @@ construct_value(nir_builder *build,
num_components = nir_op_infos[op].output_size;
nir_alu_instr *alu = nir_alu_instr_create(build->shader, op);
nir_ssa_dest_init(&alu->instr, &alu->dest.dest, num_components,
dst_bit_size);
nir_def_init(&alu->instr, &alu->dest.dest.ssa, num_components,
dst_bit_size);
/* We have no way of knowing what values in a given search expression
* map to a particular replacement value. Therefore, if the

8
src/compiler/nir/nir_split_64bit_vec3_and_vec4.c
View file

@ -225,8 +225,8 @@ split_phi(nir_builder *b, nir_phi_instr *phi)
nir_op vec_op = nir_op_vec(phi->dest.ssa.num_components);
nir_alu_instr *vec = nir_alu_instr_create(b->shader, vec_op);
nir_ssa_dest_init(&vec->instr, &vec->dest.dest,
phi->dest.ssa.num_components, 64);
nir_def_init(&vec->instr, &vec->dest.dest.ssa,
phi->dest.ssa.num_components, 64);
int num_comp[2] = { 2, phi->dest.ssa.num_components - 2 };
@ -234,8 +234,8 @@ split_phi(nir_builder *b, nir_phi_instr *phi)
for (unsigned i = 0; i < 2; i++) {
new_phi[i] = nir_phi_instr_create(b->shader);
nir_ssa_dest_init(&new_phi[i]->instr, &new_phi[i]->dest, num_comp[i],
phi->dest.ssa.bit_size);
nir_def_init(&new_phi[i]->instr, &new_phi[i]->dest.ssa, num_comp[i],
phi->dest.ssa.bit_size);
nir_foreach_phi_src(src, phi) {
/* Insert at the end of the predecessor but before the jump

8
src/compiler/nir/nir_to_lcssa.c
View file

@ -225,8 +225,8 @@ convert_loop_exit_for_ssa(nir_def *def, void *void_state)
/* Initialize a phi-instruction */
nir_phi_instr *phi = nir_phi_instr_create(state->shader);
nir_ssa_dest_init(&phi->instr, &phi->dest, def->num_components,
def->bit_size);
nir_def_init(&phi->instr, &phi->dest.ssa, def->num_components,
def->bit_size);
/* Create a phi node with as many sources pointing to the same ssa_def as
* the block has predecessors.
@ -250,8 +250,8 @@ convert_loop_exit_for_ssa(nir_def *def, void *void_state)
cast->parent = nir_src_for_ssa(&phi->dest.ssa);
cast->cast.ptr_stride = nir_deref_instr_array_stride(instr);
nir_ssa_dest_init(&cast->instr, &cast->dest,
phi->dest.ssa.num_components, phi->dest.ssa.bit_size);
nir_def_init(&cast->instr, &cast->dest.ssa,
phi->dest.ssa.num_components, phi->dest.ssa.bit_size);
nir_instr_insert(nir_after_phis(state->block_after_loop), &cast->instr);
dest = &cast->dest.ssa;
}

4
src/compiler/nir/tests/dce_tests.cpp
View file

@ -44,8 +44,8 @@ nir_phi_instr *create_one_source_phi(nir_shader *shader, nir_block *pred,
{
nir_phi_instr *phi = nir_phi_instr_create(shader);
nir_phi_instr_add_src(phi, pred, nir_src_for_ssa(def));
nir_ssa_dest_init(&phi->instr, &phi->dest, def->num_components,
def->bit_size);
nir_def_init(&phi->instr, &phi->dest.ssa, def->num_components,
def->bit_size);
return phi;
}

6
src/compiler/nir/tests/load_store_vectorizer_tests.cpp
View file

@ -162,7 +162,7 @@ nir_load_store_vectorize_test::get_resource(uint32_t binding, bool ssbo)
nir_intrinsic_instr *res = nir_intrinsic_instr_create(
b->shader, nir_intrinsic_vulkan_resource_index);
nir_ssa_dest_init(&res->instr, &res->dest, 1, 32);
nir_def_init(&res->instr, &res->dest.ssa, 1, 32);
res->num_components = 1;
res->src[0] = nir_src_for_ssa(nir_imm_zero(b, 1, 32));
nir_intrinsic_set_desc_type(
@ -197,7 +197,7 @@ nir_load_store_vectorize_test::create_indirect_load(
return NULL;
}
nir_intrinsic_instr *load = nir_intrinsic_instr_create(b->shader, intrinsic);
nir_ssa_dest_init(&load->instr, &load->dest, components, bit_size);
nir_def_init(&load->instr, &load->dest.ssa, components, bit_size);
load->num_components = components;
if (res) {
load->src[0] = nir_src_for_ssa(res);
@ -258,7 +258,7 @@ nir_load_store_vectorize_test::create_indirect_store(
return;
}
nir_intrinsic_instr *store = nir_intrinsic_instr_create(b->shader, intrinsic);
nir_ssa_dest_init(&store->instr, &store->dest, components, bit_size);
nir_def_init(&store->instr, &store->dest.ssa, components, bit_size);
store->num_components = components;
if (res) {
store->src[0] = nir_src_for_ssa(value);

8
src/compiler/nir/tests/loop_analyze_tests.cpp
View file

@ -83,8 +83,8 @@ loop_builder(nir_builder *b, loop_builder_param p)
nir_loop *loop = nir_push_loop(b);
{
nir_ssa_dest_init(&phi->instr, &phi->dest, ssa_0->num_components,
ssa_0->bit_size);
nir_def_init(&phi->instr, &phi->dest.ssa, ssa_0->num_components,
ssa_0->bit_size);
nir_phi_instr_add_src(phi, ssa_0->parent_instr->block,
nir_src_for_ssa(ssa_0));
@ -153,8 +153,8 @@ loop_builder_invert(nir_builder *b, loop_builder_invert_param p)
nir_loop *loop = nir_push_loop(b);
{
nir_ssa_dest_init(&phi->instr, &phi->dest, ssa_0->num_components,
ssa_0->bit_size);
nir_def_init(&phi->instr, &phi->dest.ssa, ssa_0->num_components,
ssa_0->bit_size);
nir_phi_instr_add_src(phi, ssa_0->parent_instr->block,
nir_src_for_ssa(ssa_0));

2
src/compiler/nir/tests/loop_unroll_tests.cpp
View file

@ -116,7 +116,7 @@ loop_unroll_test_helper(nir_builder *bld, nir_def *init,
nir_block *head_block = nir_loop_first_block(loop);
nir_phi_instr *phi = nir_phi_instr_create(bld->shader);
nir_ssa_dest_init(&phi->instr, &phi->dest, 1, 32);
nir_def_init(&phi->instr, &phi->dest.ssa, 1, 32);
nir_phi_instr_add_src(phi, top_block, nir_src_for_ssa(init));

2
src/compiler/nir/tests/mod_analysis_tests.cpp
View file

@ -58,7 +58,7 @@ nir_mod_analysis_test::nir_imul_vec2y(nir_builder *b, nir_def *src0, nir_def *sr
instr->src[1].src = nir_src_for_ssa(src1);
instr->src[1].swizzle[0] = 1;
nir_ssa_dest_init(&instr->instr, &instr->dest.dest, 1, 32);
nir_def_init(&instr->instr, &instr->dest.dest.ssa, 1, 32);
nir_builder_instr_insert(b, &instr->instr);
return &instr->dest.dest.ssa;

20
src/compiler/spirv/spirv_to_nir.c
View file

@ -3295,8 +3295,8 @@ vtn_handle_texture(struct vtn_builder *b, SpvOp opcode,
instr->dest_type = dest_type;
nir_ssa_dest_init(&instr->instr, &instr->dest,
nir_tex_instr_dest_size(instr), 32);
nir_def_init(&instr->instr, &instr->dest.ssa,
nir_tex_instr_dest_size(instr), 32);
vtn_assert(glsl_get_vector_elements(ret_type->type) ==
nir_tex_instr_result_size(instr));
@ -3776,8 +3776,8 @@ vtn_handle_image(struct vtn_builder *b, SpvOp opcode,
opcode == SpvOpImageQuerySizeLod)
bit_size = MIN2(bit_size, 32);
nir_ssa_dest_init(&intrin->instr, &intrin->dest,
nir_intrinsic_dest_components(intrin), bit_size);
nir_def_init(&intrin->instr, &intrin->dest.ssa,
nir_intrinsic_dest_components(intrin), bit_size);
nir_builder_instr_insert(&b->nb, &intrin->instr);
@ -4042,11 +4042,11 @@ vtn_handle_atomics(struct vtn_builder *b, SpvOp opcode,
if (opcode == SpvOpAtomicFlagTestAndSet) {
/* map atomic flag to a 32-bit atomic integer. */
nir_ssa_dest_init(&atomic->instr, &atomic->dest, 1, 32);
nir_def_init(&atomic->instr, &atomic->dest.ssa, 1, 32);
} else {
nir_ssa_dest_init(&atomic->instr, &atomic->dest,
glsl_get_vector_elements(type->type),
glsl_get_bit_size(type->type));
nir_def_init(&atomic->instr, &atomic->dest.ssa,
glsl_get_vector_elements(type->type),
glsl_get_bit_size(type->type));
vtn_push_nir_ssa(b, w[2], &atomic->dest.ssa);
}
@ -4066,7 +4066,7 @@ create_vec(struct vtn_builder *b, unsigned num_components, unsigned bit_size)
{
nir_op op = nir_op_vec(num_components);
nir_alu_instr *vec = nir_alu_instr_create(b->shader, op);
nir_ssa_dest_init(&vec->instr, &vec->dest.dest, num_components, bit_size);
nir_def_init(&vec->instr, &vec->dest.dest.ssa, num_components, bit_size);
return vec;
}
@ -5790,7 +5790,7 @@ vtn_handle_ray_intrinsic(struct vtn_builder *b, SpvOp opcode,
nir_intrinsic_report_ray_intersection);
intrin->src[0] = nir_src_for_ssa(vtn_ssa_value(b, w[3])->def);
intrin->src[1] = nir_src_for_ssa(vtn_ssa_value(b, w[4])->def);
nir_ssa_dest_init(&intrin->instr, &intrin->dest, 1, 1);
nir_def_init(&intrin->instr, &intrin->dest.ssa, 1, 1);
nir_builder_instr_insert(&b->nb, &intrin->instr);
vtn_push_nir_ssa(b, w[2], &intrin->dest.ssa);
break;

6
src/compiler/spirv/vtn_amd.c
View file

@ -216,9 +216,9 @@ vtn_handle_amd_shader_explicit_vertex_parameter_instruction(struct vtn_builder *
intrin->src[1] = nir_src_for_ssa(vtn_get_nir_ssa(b, w[6]));
intrin->num_components = glsl_get_vector_elements(deref->type);
nir_ssa_dest_init(&intrin->instr, &intrin->dest,
glsl_get_vector_elements(deref->type),
glsl_get_bit_size(deref->type));
nir_def_init(&intrin->instr, &intrin->dest.ssa,
glsl_get_vector_elements(deref->type),
glsl_get_bit_size(deref->type));
nir_builder_instr_insert(&b->nb, &intrin->instr);

6
src/compiler/spirv/vtn_glsl450.c
View file

@ -680,9 +680,9 @@ handle_glsl450_interpolation(struct vtn_builder *b, enum GLSLstd450 opcode,
}
intrin->num_components = glsl_get_vector_elements(deref->type);
nir_ssa_dest_init(&intrin->instr, &intrin->dest,
glsl_get_vector_elements(deref->type),
glsl_get_bit_size(deref->type));
nir_def_init(&intrin->instr, &intrin->dest.ssa,
glsl_get_vector_elements(deref->type),
glsl_get_bit_size(deref->type));
nir_builder_instr_insert(&b->nb, &intrin->instr);

2
src/compiler/spirv/vtn_subgroup.c
View file

@ -95,7 +95,7 @@ vtn_handle_subgroup(struct vtn_builder *b, SpvOp opcode,
nir_intrinsic_instr *ballot =
nir_intrinsic_instr_create(b->nb.shader, nir_intrinsic_ballot);
ballot->src[0] = nir_src_for_ssa(vtn_get_nir_ssa(b, w[3 + has_scope]));
nir_ssa_dest_init(&ballot->instr, &ballot->dest, 4, 32);
nir_def_init(&ballot->instr, &ballot->dest.ssa, 4, 32);
ballot->num_components = 4;
nir_builder_instr_insert(&b->nb, &ballot->instr);
vtn_push_nir_ssa(b, w[2], &ballot->dest.ssa);

18
src/compiler/spirv/vtn_variables.c
View file

@ -249,9 +249,9 @@ vtn_variable_resource_index(struct vtn_builder *b, struct vtn_variable *var,
nir_intrinsic_set_desc_type(instr, vk_desc_type_for_mode(b, var->mode));
nir_address_format addr_format = vtn_mode_to_address_format(b, var->mode);
nir_ssa_dest_init(&instr->instr, &instr->dest,
nir_address_format_num_components(addr_format),
nir_address_format_bit_size(addr_format));
nir_def_init(&instr->instr, &instr->dest.ssa,
nir_address_format_num_components(addr_format),
nir_address_format_bit_size(addr_format));
instr->num_components = instr->dest.ssa.num_components;
nir_builder_instr_insert(&b->nb, &instr->instr);
@ -272,9 +272,9 @@ vtn_resource_reindex(struct vtn_builder *b, enum vtn_variable_mode mode,
nir_intrinsic_set_desc_type(instr, vk_desc_type_for_mode(b, mode));
nir_address_format addr_format = vtn_mode_to_address_format(b, mode);
nir_ssa_dest_init(&instr->instr, &instr->dest,
nir_address_format_num_components(addr_format),
nir_address_format_bit_size(addr_format));
nir_def_init(&instr->instr, &instr->dest.ssa,
nir_address_format_num_components(addr_format),
nir_address_format_bit_size(addr_format));
instr->num_components = instr->dest.ssa.num_components;
nir_builder_instr_insert(&b->nb, &instr->instr);
@ -294,9 +294,9 @@ vtn_descriptor_load(struct vtn_builder *b, enum vtn_variable_mode mode,
nir_intrinsic_set_desc_type(desc_load, vk_desc_type_for_mode(b, mode));
nir_address_format addr_format = vtn_mode_to_address_format(b, mode);
nir_ssa_dest_init(&desc_load->instr, &desc_load->dest,
nir_address_format_num_components(addr_format),
nir_address_format_bit_size(addr_format));
nir_def_init(&desc_load->instr, &desc_load->dest.ssa,
nir_address_format_num_components(addr_format),
nir_address_format_bit_size(addr_format));
desc_load->num_components = desc_load->dest.ssa.num_components;
nir_builder_instr_insert(&b->nb, &desc_load->instr);

2
src/freedreno/ir3/ir3_nir_lower_64b.c
View file

@ -144,7 +144,7 @@ lower_64b_intrinsics(nir_builder *b, nir_instr *instr, void *unused)
load->num_components = 2;
load->src[offset_src_idx] = nir_src_for_ssa(off);
nir_ssa_dest_init(&load->instr, &load->dest, 2, 32);
nir_def_init(&load->instr, &load->dest.ssa, 2, 32);
nir_builder_instr_insert(b, &load->instr);
components[i] = nir_pack_64_2x32(b, &load->dest.ssa);

4
src/freedreno/ir3/ir3_nir_lower_io_offsets.c
View file

@ -220,8 +220,8 @@ lower_offset_for_ssbo(nir_intrinsic_instr *intrinsic, nir_builder *b,
if (has_dest) {
nir_def *dest = &intrinsic->dest.ssa;
nir_ssa_dest_init(&new_intrinsic->instr, &new_intrinsic->dest,
dest->num_components, dest->bit_size);
nir_def_init(&new_intrinsic->instr, &new_intrinsic->dest.ssa,
dest->num_components, dest->bit_size);
new_dest = &new_intrinsic->dest.ssa;
}

2
src/freedreno/ir3/ir3_nir_lower_layer_id.c
View file

@ -36,7 +36,7 @@ nir_lower_layer_id(nir_builder *b, nir_instr *instr, UNUSED void *cb_data)
.num_slots = 1,
};
nir_intrinsic_set_io_semantics(load_input, semantics);
nir_ssa_dest_init(&load_input->instr, &load_input->dest, 1, 32);
nir_def_init(&load_input->instr, &load_input->dest.ssa, 1, 32);
nir_builder_instr_insert(b, &load_input->instr);
nir_def_rewrite_uses(&intr->dest.ssa, &load_input->dest.ssa);
return true;

4
src/freedreno/ir3/ir3_nir_lower_tess.c
View file

@ -175,8 +175,8 @@ replace_intrinsic(nir_builder *b, nir_intrinsic_instr *intr,
new_intr->num_components = intr->num_components;
if (nir_intrinsic_infos[op].has_dest)
nir_ssa_dest_init(&new_intr->instr, &new_intr->dest,
intr->num_components, intr->dest.ssa.bit_size);
nir_def_init(&new_intr->instr, &new_intr->dest.ssa,
intr->num_components, intr->dest.ssa.bit_size);
nir_builder_instr_insert(b, &new_intr->instr);

2
src/freedreno/ir3/ir3_nir_lower_wide_load_store.c
View file

@ -93,7 +93,7 @@ lower_wide_load_store(nir_builder *b, nir_instr *instr, void *unused)
load->num_components = c;
load->src[0] = nir_src_for_ssa(addr);
nir_intrinsic_set_align(load, nir_intrinsic_align(intr), 0);
nir_ssa_dest_init(&load->instr, &load->dest, c, bit_size);
nir_def_init(&load->instr, &load->dest.ssa, c, bit_size);
nir_builder_instr_insert(b, &load->instr);
addr = nir_iadd(b,

4
src/freedreno/vulkan/tu_clear_blit.cc
View file

@ -623,7 +623,7 @@ build_blit_fs_shader(bool zscale)
nir_load_var(b, in_coords));
tex->coord_components = coord_components;
nir_ssa_dest_init(&tex->instr, &tex->dest, 4, 32);
nir_def_init(&tex->instr, &tex->dest.ssa, 4, 32);
nir_builder_instr_insert(b, &tex->instr);
nir_store_var(b, out_color, &tex->dest.ssa, 0xf);
@ -681,7 +681,7 @@ build_ms_copy_fs_shader(void)
tex->src[1] = nir_tex_src_for_ssa(nir_tex_src_ms_index,
nir_load_sample_id(b));
nir_ssa_dest_init(&tex->instr, &tex->dest, 4, 32);
nir_def_init(&tex->instr, &tex->dest.ssa, 4, 32);
nir_builder_instr_insert(b, &tex->instr);
nir_store_var(b, out_color, &tex->dest.ssa, 0xf);

6
src/freedreno/vulkan/tu_shader.cc
View file

@ -320,9 +320,9 @@ lower_ssbo_ubo_intrinsic(struct tu_device *dev,
}
if (info->has_dest) {
nir_ssa_dest_init(&copy->instr, &copy->dest,
intrin->dest.ssa.num_components,
intrin->dest.ssa.bit_size);
nir_def_init(&copy->instr, &copy->dest.ssa,
intrin->dest.ssa.num_components,
intrin->dest.ssa.bit_size);
results[i] = &copy->dest.ssa;
}

2
src/gallium/auxiliary/nir/nir_draw_helpers.c
View file

@ -78,7 +78,7 @@ nir_lower_pstipple_block(nir_block *block,
tex->texture_index = state->stip_tex->data.binding;
tex->sampler_index = state->stip_tex->data.binding;
tex->src[0] = nir_tex_src_for_ssa(nir_tex_src_coord, texcoord);
nir_ssa_dest_init(&tex->instr, &tex->dest, 4, 32);
nir_def_init(&tex->instr, &tex->dest.ssa, 4, 32);
nir_builder_instr_insert(b, &tex->instr);

14
src/gallium/auxiliary/nir/tgsi_to_nir.c
View file

@ -742,7 +742,7 @@ ttn_src_for_file_and_index(struct ttn_compile *c, unsigned file, unsigned index,
}
load->src[srcn++] = nir_src_for_ssa(offset);
nir_ssa_dest_init(&load->instr, &load->dest, 4, 32);
nir_def_init(&load->instr, &load->dest.ssa, 4, 32);
nir_builder_instr_insert(b, &load->instr);
src = nir_src_for_ssa(&load->dest.ssa);
@ -1401,8 +1401,8 @@ ttn_tex(struct ttn_compile *c, nir_def **src)
assert(src_number == num_srcs);
assert(src_number == instr->num_srcs);
nir_ssa_dest_init(&instr->instr, &instr->dest,
nir_tex_instr_dest_size(instr), 32);
nir_def_init(&instr->instr, &instr->dest.ssa,
nir_tex_instr_dest_size(instr), 32);
nir_builder_instr_insert(b, &instr->instr);
return nir_pad_vector_imm_int(b, &instr->dest.ssa, 0, 4);
}
@ -1460,11 +1460,10 @@ ttn_txq(struct ttn_compile *c, nir_def **src)
txs->src[1] = nir_tex_src_for_ssa(nir_tex_src_lod,
ttn_channel(b, src[0], X));
nir_ssa_dest_init(&txs->instr, &txs->dest, nir_tex_instr_dest_size(txs),
32);
nir_def_init(&txs->instr, &txs->dest.ssa, nir_tex_instr_dest_size(txs), 32);
nir_builder_instr_insert(b, &txs->instr);
nir_ssa_dest_init(&qlv->instr, &qlv->dest, 1, 32);
nir_def_init(&qlv->instr, &qlv->dest.ssa, 1, 32);
nir_builder_instr_insert(b, &qlv->instr);
return nir_vector_insert_imm(b,
@ -1622,8 +1621,7 @@ ttn_mem(struct ttn_compile *c, nir_def **src)
if (tgsi_inst->Instruction.Opcode == TGSI_OPCODE_LOAD) {
nir_ssa_dest_init(&instr->instr, &instr->dest, instr->num_components,
32);
nir_def_init(&instr->instr, &instr->dest.ssa, instr->num_components, 32);
nir_builder_instr_insert(b, &instr->instr);
return nir_pad_vector_imm_int(b, &instr->dest.ssa, 0, 4);
} else {

8
src/gallium/drivers/crocus/crocus_program.c
View file

@ -491,9 +491,9 @@ crocus_setup_uniforms(ASSERTED const struct intel_device_info *devinfo,
nir_intrinsic_set_align(load_ubo, 4, 0);
nir_intrinsic_set_range_base(load_ubo, 0);
nir_intrinsic_set_range(load_ubo, ~0);
nir_ssa_dest_init(&load_ubo->instr, &load_ubo->dest,
intrin->dest.ssa.num_components,
intrin->dest.ssa.bit_size);
nir_def_init(&load_ubo->instr, &load_ubo->dest.ssa,
intrin->dest.ssa.num_components,
intrin->dest.ssa.bit_size);
nir_builder_instr_insert(&b, &load_ubo->instr);
nir_def_rewrite_uses(&intrin->dest.ssa,
@ -631,7 +631,7 @@ crocus_setup_uniforms(ASSERTED const struct intel_device_info *devinfo,
nir_intrinsic_set_align(load, 4, 0);
nir_intrinsic_set_range_base(load, 0);
nir_intrinsic_set_range(load, ~0);
nir_ssa_dest_init(&load->instr, &load->dest, comps, 32);
nir_def_init(&load->instr, &load->dest.ssa, comps, 32);
nir_builder_instr_insert(&b, &load->instr);
nir_def_rewrite_uses(&intrin->dest.ssa,
&load->dest.ssa);

4
src/gallium/drivers/d3d12/d3d12_blit.cpp
View file

@ -680,7 +680,7 @@ get_stencil_resolve_fs(struct d3d12_context *ctx, bool no_flip)
txs->is_array = false;
txs->dest_type = nir_type_int;
nir_ssa_dest_init(&txs->instr, &txs->dest, 2, 32);
nir_def_init(&txs->instr, &txs->dest.ssa, 2, 32);
nir_builder_instr_insert(&b, &txs->instr);
pos_src = nir_vec4(&b,
@ -706,7 +706,7 @@ get_stencil_resolve_fs(struct d3d12_context *ctx, bool no_flip)
tex->is_array = false;
tex->coord_components = 2;
nir_ssa_dest_init(&tex->instr, &tex->dest, 4, 32);
nir_def_init(&tex->instr, &tex->dest.ssa, 4, 32);
nir_builder_instr_insert(&b, &tex->instr);
nir_store_var(&b, stencil_out, nir_channel(&b, &tex->dest.ssa, 1), 0x1);

2
src/gallium/drivers/etnaviv/etnaviv_compiler_nir.c
View file

@ -728,7 +728,7 @@ insert_vec_mov(nir_alu_instr *vec, unsigned start_idx, nir_shader *shader)
}
}
nir_ssa_dest_init(&mov->instr, &mov->dest.dest, num_components, 32);
nir_def_init(&mov->instr, &mov->dest.dest.ssa, num_components, 32);
/* replace vec srcs with inserted mov */
for (unsigned i = 0, j = 0; i < 4; i++) {

4
src/gallium/drivers/etnaviv/etnaviv_nir.c
View file

@ -132,7 +132,7 @@ etna_lower_io(nir_shader *shader, struct etna_shader_variant *v)
for (unsigned i = tex->coord_components; i < 4; i++)
vec->src[i].src = nir_src_for_ssa(src1->ssa);
nir_ssa_dest_init(&vec->instr, &vec->dest.dest, 4, 32);
nir_def_init(&vec->instr, &vec->dest.dest.ssa, 4, 32);
nir_tex_instr_remove_src(tex, src1_idx);
nir_instr_rewrite_src(&tex->instr, coord, nir_src_for_ssa(&vec->dest.dest.ssa));
@ -186,7 +186,7 @@ etna_lower_alu_impl(nir_function_impl *impl, bool has_new_transcendentals)
mul->src[0].src = mul->src[1].src = nir_src_for_ssa(ssa);
mul->src[1].swizzle[0] = 1;
nir_ssa_dest_init(&mul->instr, &mul->dest.dest, 1, 32);
nir_def_init(&mul->instr, &mul->dest.dest.ssa, 1, 32);
alu->src[0].swizzle[1] = 0;
ssa->num_components = 2;

8
src/gallium/drivers/lima/ir/lima_nir_duplicate_intrinsic.c
View file

@ -43,8 +43,8 @@ lima_nir_duplicate_intrinsic(nir_builder *b, nir_intrinsic_instr *itr,
memcpy(dupl->const_index, itr->const_index, sizeof(itr->const_index));
dupl->src[0].ssa = itr->src[0].ssa;
nir_ssa_dest_init(&dupl->instr, &dupl->dest, dupl->num_components,
itr->dest.ssa.bit_size);
nir_def_init(&dupl->instr, &dupl->dest.ssa, dupl->num_components,
itr->dest.ssa.bit_size);
dupl->instr.pass_flags = 1;
nir_builder_instr_insert(b, &dupl->instr);
@ -72,8 +72,8 @@ lima_nir_duplicate_intrinsic(nir_builder *b, nir_intrinsic_instr *itr,
memcpy(dupl->const_index, itr->const_index, sizeof(itr->const_index));
dupl->src[0].ssa = itr->src[0].ssa;
nir_ssa_dest_init(&dupl->instr, &dupl->dest, dupl->num_components,
itr->dest.ssa.bit_size);
nir_def_init(&dupl->instr, &dupl->dest.ssa, dupl->num_components,
itr->dest.ssa.bit_size);
dupl->instr.pass_flags = 1;
nir_builder_instr_insert(b, &dupl->instr);

4
src/gallium/drivers/lima/ir/lima_nir_lower_uniform_to_scalar.c
View file

@ -35,8 +35,8 @@ lower_load_uniform_to_scalar(nir_builder *b, nir_intrinsic_instr *intr)
for (unsigned i = 0; i < intr->num_components; i++) {
nir_intrinsic_instr *chan_intr =
nir_intrinsic_instr_create(b->shader, intr->intrinsic);
nir_ssa_dest_init(&chan_intr->instr, &chan_intr->dest, 1,
intr->dest.ssa.bit_size);
nir_def_init(&chan_intr->instr, &chan_intr->dest.ssa, 1,
intr->dest.ssa.bit_size);
chan_intr->num_components = 1;
nir_intrinsic_set_base(chan_intr, nir_intrinsic_base(intr) * 4 + i);

4
src/gallium/drivers/lima/ir/lima_nir_split_load_input.c
View file

@ -69,8 +69,8 @@ lima_nir_split_load_input_instr(nir_builder *b,
nir_intrinsic_instr *new_intrin = nir_intrinsic_instr_create(
b->shader,
intrin->intrinsic);
nir_ssa_dest_init(&new_intrin->instr, &new_intrin->dest,
nir_dest_num_components(alu->dest.dest), ssa->bit_size);
nir_def_init(&new_intrin->instr, &new_intrin->dest.ssa,
nir_dest_num_components(alu->dest.dest), ssa->bit_size);
new_intrin->num_components = nir_dest_num_components(alu->dest.dest);
nir_intrinsic_set_base(new_intrin, nir_intrinsic_base(intrin));
nir_intrinsic_set_component(new_intrin, nir_intrinsic_component(intrin) + swizzle);

9
src/gallium/drivers/r600/sfn/sfn_nir.cpp
View file

@ -543,8 +543,8 @@ r600_lower_shared_io_impl(nir_function_impl *impl)
nir_intrinsic_instr_create(b.shader, nir_intrinsic_load_local_shared_r600);
load->num_components = nir_dest_num_components(op->dest);
load->src[0] = nir_src_for_ssa(addr);
nir_ssa_dest_init(&load->instr, &load->dest, load->num_components,
32);
nir_def_init(&load->instr, &load->dest.ssa, load->num_components,
32);
nir_def_rewrite_uses(&op->dest.ssa, &load->dest.ssa);
nir_builder_instr_insert(&b, &load->instr);
} else {
@ -595,9 +595,8 @@ r600_lower_fs_pos_input_impl(nir_builder *b, nir_instr *instr, void *_options)
(void)_options;
auto old_ir = nir_instr_as_intrinsic(instr);
auto load = nir_intrinsic_instr_create(b->shader, nir_intrinsic_load_input);
nir_ssa_dest_init(&load->instr, &load->dest,
old_ir->dest.ssa.num_components,
old_ir->dest.ssa.bit_size);
nir_def_init(&load->instr, &load->dest.ssa,
old_ir->dest.ssa.num_components, old_ir->dest.ssa.bit_size);
nir_intrinsic_set_io_semantics(load, nir_intrinsic_io_semantics(old_ir));
nir_intrinsic_set_base(load, nir_intrinsic_base(old_ir));

6
src/gallium/drivers/r600/sfn/sfn_nir_lower_64bit.cpp
View file

@ -589,7 +589,7 @@ LowerSplit64BitVar::split_double_load_uniform(nir_intrinsic_instr *intr)
nir_intrinsic_set_range(load2, nir_intrinsic_range(intr));
load2->num_components = second_components;
nir_ssa_dest_init(&load2->instr, &load2->dest, second_components, 64);
nir_def_init(&load2->instr, &load2->dest.ssa, second_components, 64);
nir_builder_instr_insert(b, &load2->instr);
intr->dest.ssa.num_components = intr->num_components = 2;
@ -617,7 +617,7 @@ LowerSplit64BitVar::split_double_load_ssbo(nir_intrinsic_instr *intr)
auto new_src0 = nir_src_for_ssa(nir_iadd_imm(b, intr->src[0].ssa, 1));
nir_instr_rewrite_src(&load2->instr, &load2->src[0], new_src0);
load2->num_components = second_components;
nir_ssa_dest_init(&load2->instr, &load2->dest, second_components, 64);
nir_def_init(&load2->instr, &load2->dest.ssa, second_components, 64);
nir_intrinsic_set_dest_type(load2, nir_intrinsic_dest_type(intr));
nir_builder_instr_insert(b, &load2->instr);
@ -643,7 +643,7 @@ LowerSplit64BitVar::split_double_load_ubo(nir_intrinsic_instr *intr)
load2->num_components = second_components;
nir_ssa_dest_init(&load2->instr, &load2->dest, second_components, 64);
nir_def_init(&load2->instr, &load2->dest.ssa, second_components, 64);
nir_builder_instr_insert(b, &load2->instr);
intr->dest.ssa.num_components = intr->num_components = 2;

2
src/gallium/drivers/r600/sfn/sfn_nir_lower_fs_out_to_vector.cpp
View file

@ -486,7 +486,7 @@ NirLowerFSOutToVector::create_combined_vector(nir_builder *b,
k += s->num_components;
}
nir_ssa_dest_init(&instr->instr, &instr->dest.dest, num_comp, 32);
nir_def_init(&instr->instr, &instr->dest.dest.ssa, num_comp, 32);
nir_builder_instr_insert(b, &instr->instr);
return &instr->dest.dest.ssa;
}

6
src/gallium/drivers/r600/sfn/sfn_nir_lower_tess_io.cpp
View file

@ -55,7 +55,7 @@ static nir_def *
emit_load_param_base(nir_builder *b, nir_intrinsic_op op)
{
nir_intrinsic_instr *result = nir_intrinsic_instr_create(b->shader, op);
nir_ssa_dest_init(&result->instr, &result->dest, 4, 32);
nir_def_init(&result->instr, &result->dest.ssa, 4, 32);
nir_builder_instr_insert(b, &result->instr);
return &result->dest.ssa;
}
@ -284,7 +284,7 @@ r600_load_rel_patch_id(nir_builder *b)
{
auto patch_id =
nir_intrinsic_instr_create(b->shader, nir_intrinsic_load_tcs_rel_patch_id_r600);
nir_ssa_dest_init(&patch_id->instr, &patch_id->dest, 1, 32);
nir_def_init(&patch_id->instr, &patch_id->dest.ssa, 1, 32);
nir_builder_instr_insert(b, &patch_id->instr);
return &patch_id->dest.ssa;
}
@ -452,7 +452,7 @@ r600_lower_tess_io_impl(nir_builder *b, nir_instr *instr, enum mesa_prim prim_ty
nir_intrinsic_instr_create(b->shader, nir_intrinsic_load_local_shared_r600);
tf->num_components = ncomps;
tf->src[0] = nir_src_for_ssa(addr_outer);
nir_ssa_dest_init(&tf->instr, &tf->dest, tf->num_components, 32);
nir_def_init(&tf->instr, &tf->dest.ssa, tf->num_components, 32);
nir_builder_instr_insert(b, &tf->instr);
if (ncomps < 4 && b->shader->info.stage != MESA_SHADER_TESS_EVAL) {
auto undef = nir_undef(b, 1, 32);

4
src/gallium/drivers/r600/sfn/sfn_nir_vectorize_vs_inputs.c
View file

@ -147,8 +147,8 @@ r600_create_new_load(nir_builder *b,
b->cursor = nir_before_instr(&intr->instr);
nir_intrinsic_instr *new_intr = nir_intrinsic_instr_create(b->shader, intr->intrinsic);
nir_ssa_dest_init(&new_intr->instr, &new_intr->dest, num_comps,
intr->dest.ssa.bit_size);
nir_def_init(&new_intr->instr, &new_intr->dest.ssa, num_comps,
intr->dest.ssa.bit_size);
new_intr->num_components = num_comps;
nir_deref_instr *deref = nir_build_deref_var(b, var);

4
src/gallium/drivers/vc4/vc4_nir_lower_io.c
View file

@ -299,8 +299,8 @@ vc4_nir_lower_uniform(struct vc4_compile *c, nir_builder *b,
nir_intrinsic_instr *intr_comp =
nir_intrinsic_instr_create(c->s, intr->intrinsic);
intr_comp->num_components = 1;
nir_ssa_dest_init(&intr_comp->instr, &intr_comp->dest, 1,
intr->dest.ssa.bit_size);
nir_def_init(&intr_comp->instr, &intr_comp->dest.ssa, 1,
intr->dest.ssa.bit_size);
/* Convert the uniform offset to bytes. If it happens
* to be a constant, constant-folding will clean up

2
src/gallium/drivers/vc4/vc4_nir_lower_txf_ms.c
View file

@ -109,7 +109,7 @@ vc4_nir_lower_txf_ms_instr(nir_builder *b, nir_instr *instr, void *data)
txf->src[0] = nir_tex_src_for_ssa(nir_tex_src_coord,
nir_vec2(b, addr, nir_imm_int(b, 0)));
nir_ssa_dest_init(&txf->instr, &txf->dest, 4, 32);
nir_def_init(&txf->instr, &txf->dest.ssa, 4, 32);
nir_builder_instr_insert(b, &txf->instr);
return &txf->dest.ssa;

12
src/gallium/drivers/zink/zink_compiler.c
View file

@ -235,7 +235,7 @@ lower_basevertex_instr(nir_builder *b, nir_instr *in, void *data)
nir_intrinsic_instr *load = nir_intrinsic_instr_create(b->shader, nir_intrinsic_load_push_constant_zink);
load->src[0] = nir_src_for_ssa(nir_imm_int(b, ZINK_GFX_PUSHCONST_DRAW_MODE_IS_INDEXED));
load->num_components = 1;
nir_ssa_dest_init(&load->instr, &load->dest, 1, 32);
nir_def_init(&load->instr, &load->dest.ssa, 1, 32);
nir_builder_instr_insert(b, &load->instr);
nir_def *composite = nir_build_alu(b, nir_op_bcsel,
@ -275,7 +275,7 @@ lower_drawid_instr(nir_builder *b, nir_instr *in, void *data)
nir_intrinsic_instr *load = nir_intrinsic_instr_create(b->shader, nir_intrinsic_load_push_constant_zink);
load->src[0] = nir_src_for_ssa(nir_imm_int(b, ZINK_GFX_PUSHCONST_DRAW_ID));
load->num_components = 1;
nir_ssa_dest_init(&load->instr, &load->dest, 1, 32);
nir_def_init(&load->instr, &load->dest.ssa, 1, 32);
nir_builder_instr_insert(b, &load->instr);
nir_def_rewrite_uses(&instr->dest.ssa, &load->dest.ssa);
@ -1718,8 +1718,8 @@ lower_txf_lod_robustness_instr(nir_builder *b, nir_instr *in, void *data)
levels->src[!!(offset_idx >= 0)].src_type = nir_tex_src_texture_handle;
nir_src_copy(&levels->src[!!(offset_idx >= 0)].src, &txf->src[handle_idx].src, &levels->instr);
}
nir_ssa_dest_init(&levels->instr, &levels->dest,
nir_tex_instr_dest_size(levels), 32);
nir_def_init(&levels->instr, &levels->dest.ssa,
nir_tex_instr_dest_size(levels), 32);
nir_builder_instr_insert(b, &levels->instr);
nir_if *lod_oob_if = nir_push_if(b, nir_ilt(b, lod, &levels->dest.ssa));
@ -2323,8 +2323,8 @@ rewrite_atomic_ssbo_instr(nir_builder *b, nir_instr *instr, struct bo_vars *bo)
for (unsigned i = 0; i < num_components; i++) {
nir_deref_instr *deref_arr = nir_build_deref_array(b, deref_struct, offset);
nir_intrinsic_instr *new_instr = nir_intrinsic_instr_create(b->shader, op);
nir_ssa_dest_init(&new_instr->instr, &new_instr->dest, 1,
nir_dest_bit_size(intr->dest));
nir_def_init(&new_instr->instr, &new_instr->dest.ssa, 1,
nir_dest_bit_size(intr->dest));
nir_intrinsic_set_atomic_op(new_instr, nir_intrinsic_atomic_op(intr));
new_instr->src[0] = nir_src_for_ssa(&deref_arr->dest.ssa);
/* deref ops have no offset src, so copy the srcs after it */

12
src/gallium/drivers/zink/zink_lower_cubemap_to_array.c
View file

@ -176,9 +176,9 @@ create_array_tex_from_cube_tex(nir_builder *b, nir_tex_instr *tex, nir_def *coor
s++;
}
nir_ssa_dest_init(&array_tex->instr, &array_tex->dest,
nir_tex_instr_dest_size(array_tex),
nir_dest_bit_size(tex->dest));
nir_def_init(&array_tex->instr, &array_tex->dest.ssa,
nir_tex_instr_dest_size(array_tex),
nir_dest_bit_size(tex->dest));
nir_builder_instr_insert(b, &array_tex->instr);
return &array_tex->dest.ssa;
}
@ -446,9 +446,9 @@ lower_tex_to_txl(nir_builder *b, nir_tex_instr *tex)
txl->src[s] = nir_tex_src_for_ssa(nir_tex_src_lod, lod);
b->cursor = nir_before_instr(&tex->instr);
nir_ssa_dest_init(&txl->instr, &txl->dest,
nir_dest_num_components(tex->dest),
nir_dest_bit_size(tex->dest));
nir_def_init(&txl->instr, &txl->dest.ssa,
nir_dest_num_components(tex->dest),
nir_dest_bit_size(tex->dest));
nir_builder_instr_insert(b, &txl->instr);
nir_def_rewrite_uses(&tex->dest.ssa, &txl->dest.ssa);
return txl;

6
src/imagination/rogue/nir/rogue_nir_lower_io.c
View file

@ -66,10 +66,8 @@ static void lower_load_global_constant_to_scalar(nir_builder *b,
for (uint8_t i = 0; i < intr->num_components; i++) {
nir_intrinsic_instr *chan_intr =
nir_intrinsic_instr_create(b->shader, intr->intrinsic);
nir_ssa_dest_init(&chan_intr->instr,
&chan_intr->dest,
1,
intr->dest.ssa.bit_size);
nir_def_init(&chan_intr->instr, &chan_intr->dest.ssa, 1,
intr->dest.ssa.bit_size);
chan_intr->num_components = 1;
nir_intrinsic_set_access(chan_intr, nir_intrinsic_access(intr));

2
src/intel/blorp/blorp_blit.c
View file

@ -163,7 +163,7 @@ blorp_create_nir_tex_instr(nir_builder *b, struct brw_blorp_blit_vars *v,
tex->src[0] = nir_tex_src_for_ssa(nir_tex_src_coord, pos);
tex->coord_components = 3;
nir_ssa_dest_init(&tex->instr, &tex->dest, 4, 32);
nir_def_init(&tex->instr, &tex->dest.ssa, 4, 32);
return tex;
}

10
src/intel/compiler/brw_kernel.c
View file

@ -110,7 +110,7 @@ implement_sub_group_ballot_builtin(nir_function *func)
nir_intrinsic_instr_create(b.shader, nir_intrinsic_ballot);
ballot->src[0] = nir_src_for_ssa(cond);
ballot->num_components = 1;
nir_ssa_dest_init(&ballot->instr, &ballot->dest, 1, 32);
nir_def_init(&ballot->instr, &ballot->dest.ssa, 1, 32);
nir_builder_instr_insert(&b, &ballot->instr);
nir_store_deref(&b, ret, &ballot->dest.ssa, ~0);
@ -182,9 +182,9 @@ lower_kernel_intrinsics(nir_shader *nir)
load->src[0] = nir_src_for_ssa(nir_u2u32(&b, intrin->src[0].ssa));
nir_intrinsic_set_base(load, kernel_arg_start);
nir_intrinsic_set_range(load, nir->num_uniforms);
nir_ssa_dest_init(&load->instr, &load->dest,
intrin->dest.ssa.num_components,
intrin->dest.ssa.bit_size);
nir_def_init(&load->instr, &load->dest.ssa,
intrin->dest.ssa.num_components,
intrin->dest.ssa.bit_size);
nir_builder_instr_insert(&b, &load->instr);
nir_def_rewrite_uses(&intrin->dest.ssa, &load->dest.ssa);
@ -212,7 +212,7 @@ lower_kernel_intrinsics(nir_shader *nir)
nir_intrinsic_set_base(load, kernel_sysvals_start +
offsetof(struct brw_kernel_sysvals, num_work_groups));
nir_intrinsic_set_range(load, 3 * 4);
nir_ssa_dest_init(&load->instr, &load->dest, 3, 32);
nir_def_init(&load->instr, &load->dest.ssa, 3, 32);
nir_builder_instr_insert(&b, &load->instr);
/* We may need to do a bit-size cast here */

2
src/intel/compiler/brw_nir.c
View file

@ -328,7 +328,7 @@ brw_nir_lower_vs_inputs(nir_shader *nir,
}
load->num_components = 1;
nir_ssa_dest_init(&load->instr, &load->dest, 1, 32);
nir_def_init(&load->instr, &load->dest.ssa, 1, 32);
nir_builder_instr_insert(&b, &load->instr);
nir_def_rewrite_uses(&intrin->dest.ssa,

8
src/intel/compiler/brw_nir_lower_sparse.c
View file

@ -156,8 +156,8 @@ lower_sparse_image_load(nir_builder *b, nir_intrinsic_instr *intrin)
tex->src[2].src_type = nir_tex_src_lod;
tex->src[2].src = nir_src_for_ssa(nir_imm_int(b, 0));
nir_ssa_dest_init(&tex->instr, &tex->dest, 5,
nir_dest_bit_size(intrin->dest));
nir_def_init(&tex->instr, &tex->dest.ssa, 5,
nir_dest_bit_size(intrin->dest));
nir_builder_instr_insert(b, &tex->instr);
@ -175,8 +175,8 @@ lower_tex_compare(nir_builder *b, nir_tex_instr *tex, int compare_idx)
/* Clone the original instruction */
nir_tex_instr *sparse_tex = nir_instr_as_tex(nir_instr_clone(b->shader, &tex->instr));
nir_ssa_dest_init(&sparse_tex->instr, &sparse_tex->dest,
tex->dest.ssa.num_components, tex->dest.ssa.bit_size);
nir_def_init(&sparse_tex->instr, &sparse_tex->dest.ssa,
tex->dest.ssa.num_components, tex->dest.ssa.bit_size);
nir_builder_instr_insert(b, &sparse_tex->instr);
/* Drop the compare source on the cloned instruction */

2
src/intel/compiler/brw_nir_lower_storage_image.c
View file

@ -51,7 +51,7 @@ _load_image_param(nir_builder *b, nir_deref_instr *deref, unsigned offset)
default:
unreachable("Invalid param offset");
}
nir_ssa_dest_init(&load->instr, &load->dest, load->num_components, 32);
nir_def_init(&load->instr, &load->dest.ssa, load->num_components, 32);
nir_builder_instr_insert(b, &load->instr);
return &load->dest.ssa;

4
src/intel/compiler/brw_nir_opt_peephole_ffma.c
View file

@ -232,8 +232,8 @@ brw_nir_opt_peephole_ffma_instr(nir_builder *b,
}
nir_alu_src_copy(&ffma->src[2], &add->src[1 - add_mul_src], ffma);
nir_ssa_dest_init(&ffma->instr, &ffma->dest.dest,
add->dest.dest.ssa.num_components, bit_size);
nir_def_init(&ffma->instr, &ffma->dest.dest.ssa,
add->dest.dest.ssa.num_components, bit_size);
nir_def_rewrite_uses(&add->dest.dest.ssa, &ffma->dest.dest.ssa);
nir_builder_instr_insert(b, &ffma->instr);

4
src/intel/compiler/brw_nir_opt_peephole_imul32x16.c
View file

@ -45,8 +45,8 @@ replace_imul_instr(nir_builder *b, nir_alu_instr *imul, unsigned small_val,
nir_alu_src_copy(&imul_32x16->src[0], &imul->src[1 - small_val], imul_32x16);
nir_alu_src_copy(&imul_32x16->src[1], &imul->src[small_val], imul_32x16);
nir_ssa_dest_init(&imul_32x16->instr, &imul_32x16->dest.dest,
imul->dest.dest.ssa.num_components, 32);
nir_def_init(&imul_32x16->instr, &imul_32x16->dest.dest.ssa,
imul->dest.dest.ssa.num_components, 32);
nir_def_rewrite_uses(&imul->dest.dest.ssa,
&imul_32x16->dest.dest.ssa);

8
src/intel/vulkan_hasvk/anv_nir_lower_ycbcr_textures.c
View file

@ -55,8 +55,7 @@ get_texture_size(struct ycbcr_state *state, nir_deref_instr *texture)
tex->src[0] = nir_tex_src_for_ssa(nir_tex_src_texture_deref,
&texture->dest.ssa);
nir_ssa_dest_init(&tex->instr, &tex->dest, nir_tex_instr_dest_size(tex),
32);
nir_def_init(&tex->instr, &tex->dest.ssa, nir_tex_instr_dest_size(tex), 32);
nir_builder_instr_insert(b, &tex->instr);
state->image_size = nir_i2f32(b, &tex->dest.ssa);
@ -152,9 +151,8 @@ create_plane_tex_instr_implicit(struct ycbcr_state *state,
tex->sampler_index = old_tex->sampler_index;
tex->is_array = old_tex->is_array;
nir_ssa_dest_init(&tex->instr, &tex->dest,
old_tex->dest.ssa.num_components,
nir_dest_bit_size(old_tex->dest));
nir_def_init(&tex->instr, &tex->dest.ssa, old_tex->dest.ssa.num_components,
nir_dest_bit_size(old_tex->dest));
nir_builder_instr_insert(b, &tex->instr);
return &tex->dest.ssa;

2
src/mesa/main/ff_fragment_shader.c
View file

@ -819,7 +819,7 @@ load_texture(struct texenv_fragment_program *p, GLuint unit)
tex->src[4] = nir_tex_src_for_ssa(nir_tex_src_comparator, src4);
}
nir_ssa_dest_init(&tex->instr, &tex->dest, 4, 32);
nir_def_init(&tex->instr, &tex->dest.ssa, 4, 32);
p->src_texture[unit] = &tex->dest.ssa;
nir_builder_instr_insert(p->b, &tex->instr);

4
src/mesa/program/prog_to_nir.c
View file

@ -178,7 +178,7 @@ ptn_get_src(struct ptn_compile *c, const struct prog_src_register *prog_src)
} else {
assert(swizzle != SWIZZLE_NIL);
nir_alu_instr *mov = nir_alu_instr_create(b->shader, nir_op_mov);
nir_ssa_dest_init(&mov->instr, &mov->dest.dest, 1, 32);
nir_def_init(&mov->instr, &mov->dest.dest.ssa, 1, 32);
mov->src[0] = src;
mov->src[0].swizzle[0] = swizzle;
nir_builder_instr_insert(b, &mov->instr);
@ -463,7 +463,7 @@ ptn_tex(struct ptn_compile *c, nir_def **src,
assert(src_number == num_srcs);
nir_ssa_dest_init(&instr->instr, &instr->dest, 4, 32);
nir_def_init(&instr->instr, &instr->dest.ssa, 4, 32);
nir_builder_instr_insert(b, &instr->instr);
return &instr->dest.ssa;

2
src/mesa/state_tracker/st_atifs_to_nir.c
View file

@ -366,7 +366,7 @@ compile_setupinst(struct st_translate *t,
tex->src[2] = nir_tex_src_for_ssa(nir_tex_src_coord,
nir_trim_vector(t->b, coord, tex->coord_components));
nir_ssa_dest_init(&tex->instr, &tex->dest, 4, 32);
nir_def_init(&tex->instr, &tex->dest.ssa, 4, 32);
nir_builder_instr_insert(t->b, &tex->instr);
t->temps[r] = &tex->dest.ssa;

2
src/mesa/state_tracker/st_cb_drawpixels.c
View file

@ -134,7 +134,7 @@ sample_via_nir(nir_builder *b, nir_variable *texcoord,
nir_trim_vector(b, nir_load_var(b, texcoord),
tex->coord_components));
nir_ssa_dest_init(&tex->instr, &tex->dest, 4, 32);
nir_def_init(&tex->instr, &tex->dest.ssa, 4, 32);
nir_builder_instr_insert(b, &tex->instr);
return nir_channel(b, &tex->dest.ssa, 0);
}

2
src/mesa/state_tracker/st_pbo.c
View file

@ -527,7 +527,7 @@ create_fs(struct st_context *st, bool download,
tex->src[1].src = nir_src_for_ssa(&tex_deref->dest.ssa);
tex->src[2].src_type = nir_tex_src_coord;
tex->src[2].src = nir_src_for_ssa(texcoord);
nir_ssa_dest_init(&tex->instr, &tex->dest, 4, 32);
nir_def_init(&tex->instr, &tex->dest.ssa, 4, 32);
nir_builder_instr_insert(&b, &tex->instr);
nir_def *result = &tex->dest.ssa;

2
src/mesa/state_tracker/st_pbo_compute.c
View file

@ -687,7 +687,7 @@ create_conversion_shader(struct st_context *st, enum pipe_texture_target target,
nir_deref_instr *sampler_deref = nir_build_deref_var(&b, sampler);
txf->src[2].src = nir_src_for_ssa(&sampler_deref->dest.ssa);
nir_ssa_dest_init(&txf->instr, &txf->dest, 4, 32);
nir_def_init(&txf->instr, &txf->dest.ssa, 4, 32);
nir_builder_instr_insert(&b, &txf->instr);
/* pass the grid offset as the coord to get the zero-indexed buffer offset */

4
src/microsoft/compiler/dxil_nir.c
View file

@ -835,8 +835,8 @@ cast_phi(nir_builder *b, nir_phi_instr *phi, unsigned new_bit_size)
nir_phi_instr_add_src(lowered, src->pred, nir_src_for_ssa(cast));
}
nir_ssa_dest_init(&lowered->instr, &lowered->dest, num_components,
new_bit_size);
nir_def_init(&lowered->instr, &lowered->dest.ssa, num_components,
new_bit_size);
b->cursor = nir_before_instr(&phi->instr);
nir_builder_instr_insert(b, &lowered->instr);

4
src/microsoft/compiler/dxil_nir_lower_int_cubemaps.c
View file

@ -188,8 +188,8 @@ create_array_tex_from_cube_tex(nir_builder *b, nir_tex_instr *tex, nir_def *coor
array_tex->src[i].src_type = tex->src[i].src_type;
}
nir_ssa_dest_init(&array_tex->instr, &array_tex->dest,
nir_tex_instr_dest_size(array_tex), 32);
nir_def_init(&array_tex->instr, &array_tex->dest.ssa,
nir_tex_instr_dest_size(array_tex), 32);
nir_builder_instr_insert(b, &array_tex->instr);
return &array_tex->dest.ssa;
}

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