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intel: Sync xe_drm.h and rename engine to exec_queue

Browse source 
Sync with commit f16c04291100 ("drm/xe: Rename engine to exec_queue").
With that Iris and ANV had some major renames that were done manually
as there is to many "engine" in non-related code.

Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24476>
This commit is contained in:
José Roberto de Souza 2023-08-03 07:19:48 -07:00 • committed by Marge Bot
parent 6db246c960
commit d686cadfbf
9 changed files with 106 additions and 97 deletions
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97
include/drm-uapi/xe_drm.h
View file

@ -16,6 +16,16 @@ extern "C" {
* subject to backwards-compatibility constraints.
*/
/**
* DOC: uevent generated by xe on it's pci node.
*
* XE_RESET_FAILED_UEVENT - Event is generated when attempt to reset gt
* fails. The value supplied with the event is always "NEEDS_RESET".
* Additional information supplied is tile id and gt id of the gt unit for
* which reset has failed.
*/
#define XE_RESET_FAILED_UEVENT "DEVICE_STATUS"
/**
* struct xe_user_extension - Base class for defining a chain of extensions
*
@ -93,14 +103,14 @@ struct xe_user_extension {
#define DRM_XE_VM_CREATE 0x03
#define DRM_XE_VM_DESTROY 0x04
#define DRM_XE_VM_BIND 0x05
#define DRM_XE_ENGINE_CREATE 0x06
#define DRM_XE_ENGINE_DESTROY 0x07
#define DRM_XE_EXEC_QUEUE_CREATE 0x06
#define DRM_XE_EXEC_QUEUE_DESTROY 0x07
#define DRM_XE_EXEC 0x08
#define DRM_XE_MMIO 0x09
#define DRM_XE_ENGINE_SET_PROPERTY 0x0a
#define DRM_XE_EXEC_QUEUE_SET_PROPERTY 0x0a
#define DRM_XE_WAIT_USER_FENCE 0x0b
#define DRM_XE_VM_MADVISE 0x0c
#define DRM_XE_ENGINE_GET_PROPERTY 0x0d
#define DRM_XE_EXEC_QUEUE_GET_PROPERTY 0x0d
/* Must be kept compact -- no holes */
#define DRM_IOCTL_XE_DEVICE_QUERY DRM_IOWR(DRM_COMMAND_BASE + DRM_XE_DEVICE_QUERY, struct drm_xe_device_query)
@ -109,12 +119,12 @@ struct xe_user_extension {
#define DRM_IOCTL_XE_VM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_XE_VM_CREATE, struct drm_xe_vm_create)
#define DRM_IOCTL_XE_VM_DESTROY DRM_IOW(DRM_COMMAND_BASE + DRM_XE_VM_DESTROY, struct drm_xe_vm_destroy)
#define DRM_IOCTL_XE_VM_BIND DRM_IOW(DRM_COMMAND_BASE + DRM_XE_VM_BIND, struct drm_xe_vm_bind)
#define DRM_IOCTL_XE_ENGINE_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_XE_ENGINE_CREATE, struct drm_xe_engine_create)
#define DRM_IOCTL_XE_ENGINE_GET_PROPERTY DRM_IOWR(DRM_COMMAND_BASE + DRM_XE_ENGINE_GET_PROPERTY, struct drm_xe_engine_get_property)
#define DRM_IOCTL_XE_ENGINE_DESTROY DRM_IOW(DRM_COMMAND_BASE + DRM_XE_ENGINE_DESTROY, struct drm_xe_engine_destroy)
#define DRM_IOCTL_XE_EXEC_QUEUE_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_XE_EXEC_QUEUE_CREATE, struct drm_xe_exec_queue_create)
#define DRM_IOCTL_XE_EXEC_QUEUE_GET_PROPERTY DRM_IOWR(DRM_COMMAND_BASE + DRM_XE_EXEC_QUEUE_GET_PROPERTY, struct drm_xe_exec_queue_get_property)
#define DRM_IOCTL_XE_EXEC_QUEUE_DESTROY DRM_IOW(DRM_COMMAND_BASE + DRM_XE_EXEC_QUEUE_DESTROY, struct drm_xe_exec_queue_destroy)
#define DRM_IOCTL_XE_EXEC DRM_IOW(DRM_COMMAND_BASE + DRM_XE_EXEC, struct drm_xe_exec)
#define DRM_IOCTL_XE_MMIO DRM_IOWR(DRM_COMMAND_BASE + DRM_XE_MMIO, struct drm_xe_mmio)
#define DRM_IOCTL_XE_ENGINE_SET_PROPERTY DRM_IOW(DRM_COMMAND_BASE + DRM_XE_ENGINE_SET_PROPERTY, struct drm_xe_engine_set_property)
#define DRM_IOCTL_XE_EXEC_QUEUE_SET_PROPERTY DRM_IOW(DRM_COMMAND_BASE + DRM_XE_EXEC_QUEUE_SET_PROPERTY, struct drm_xe_exec_queue_set_property)
#define DRM_IOCTL_XE_WAIT_USER_FENCE DRM_IOWR(DRM_COMMAND_BASE + DRM_XE_WAIT_USER_FENCE, struct drm_xe_wait_user_fence)
#define DRM_IOCTL_XE_VM_MADVISE DRM_IOW(DRM_COMMAND_BASE + DRM_XE_VM_MADVISE, struct drm_xe_vm_madvise)
@ -246,7 +256,6 @@ struct drm_xe_query_config {
#define XE_QUERY_CONFIG_REV_AND_DEVICE_ID 0
#define XE_QUERY_CONFIG_FLAGS 1
#define XE_QUERY_CONFIG_FLAGS_HAS_VRAM (0x1 << 0)
#define XE_QUERY_CONFIG_FLAGS_USE_GUC (0x1 << 1)
#define XE_QUERY_CONFIG_MIN_ALIGNEMENT 2
#define XE_QUERY_CONFIG_VA_BITS 3
#define XE_QUERY_CONFIG_GT_COUNT 4
@ -640,11 +649,11 @@ struct drm_xe_vm_bind {
__u32 vm_id;
/**
* @engine_id: engine_id, must be of class DRM_XE_ENGINE_CLASS_VM_BIND
* and engine must have same vm_id. If zero, the default VM bind engine
* @exec_queue_id: exec_queue_id, must be of class DRM_XE_ENGINE_CLASS_VM_BIND
* and exec queue must have same vm_id. If zero, the default VM bind engine
* is used.
*/
__u32 engine_id;
__u32 exec_queue_id;
/** @num_binds: number of binds in this IOCTL */
__u32 num_binds;
@ -676,8 +685,8 @@ struct drm_xe_vm_bind {
__u64 reserved[2];
};
/** struct drm_xe_ext_engine_set_property - engine set property extension */
struct drm_xe_ext_engine_set_property {
/** struct drm_xe_ext_exec_queue_set_property - exec queue set property extension */
struct drm_xe_ext_exec_queue_set_property {
/** @base: base user extension */
struct xe_user_extension base;
@ -692,32 +701,32 @@ struct drm_xe_ext_engine_set_property {
};
/**
* struct drm_xe_engine_set_property - engine set property
* struct drm_xe_exec_queue_set_property - exec queue set property
*
* Same namespace for extensions as drm_xe_engine_create
* Same namespace for extensions as drm_xe_exec_queue_create
*/
struct drm_xe_engine_set_property {
struct drm_xe_exec_queue_set_property {
/** @extensions: Pointer to the first extension struct, if any */
__u64 extensions;
/** @engine_id: Engine ID */
__u32 engine_id;
/** @exec_queue_id: Exec queue ID */
__u32 exec_queue_id;
#define XE_ENGINE_SET_PROPERTY_PRIORITY 0
#define XE_ENGINE_SET_PROPERTY_TIMESLICE 1
#define XE_ENGINE_SET_PROPERTY_PREEMPTION_TIMEOUT 2
#define XE_EXEC_QUEUE_SET_PROPERTY_PRIORITY 0
#define XE_EXEC_QUEUE_SET_PROPERTY_TIMESLICE 1
#define XE_EXEC_QUEUE_SET_PROPERTY_PREEMPTION_TIMEOUT 2
/*
* Long running or ULLS engine mode. DMA fences not allowed in this
* mode. Must match the value of DRM_XE_VM_CREATE_COMPUTE_MODE, serves
* as a sanity check the UMD knows what it is doing. Can only be set at
* engine create time.
*/
#define XE_ENGINE_SET_PROPERTY_COMPUTE_MODE 3
#define XE_ENGINE_SET_PROPERTY_PERSISTENCE 4
#define XE_ENGINE_SET_PROPERTY_JOB_TIMEOUT 5
#define XE_ENGINE_SET_PROPERTY_ACC_TRIGGER 6
#define XE_ENGINE_SET_PROPERTY_ACC_NOTIFY 7
#define XE_ENGINE_SET_PROPERTY_ACC_GRANULARITY 8
#define XE_EXEC_QUEUE_SET_PROPERTY_COMPUTE_MODE 3
#define XE_EXEC_QUEUE_SET_PROPERTY_PERSISTENCE 4
#define XE_EXEC_QUEUE_SET_PROPERTY_JOB_TIMEOUT 5
#define XE_EXEC_QUEUE_SET_PROPERTY_ACC_TRIGGER 6
#define XE_EXEC_QUEUE_SET_PROPERTY_ACC_NOTIFY 7
#define XE_EXEC_QUEUE_SET_PROPERTY_ACC_GRANULARITY 8
/** @property: property to set */
__u32 property;
@ -746,25 +755,25 @@ struct drm_xe_engine_class_instance {
__u16 gt_id;
};
struct drm_xe_engine_create {
#define XE_ENGINE_EXTENSION_SET_PROPERTY 0
struct drm_xe_exec_queue_create {
#define XE_EXEC_QUEUE_EXTENSION_SET_PROPERTY 0
/** @extensions: Pointer to the first extension struct, if any */
__u64 extensions;
/** @width: submission width (number BB per exec) for this engine */
/** @width: submission width (number BB per exec) for this exec queue */
__u16 width;
/** @num_placements: number of valid placements for this engine */
/** @num_placements: number of valid placements for this exec queue */
__u16 num_placements;
/** @vm_id: VM to use for this engine */
/** @vm_id: VM to use for this exec queue */
__u32 vm_id;
/** @flags: MBZ */
__u32 flags;
/** @engine_id: Returned engine ID */
__u32 engine_id;
/** @exec_queue_id: Returned exec queue ID */
__u32 exec_queue_id;
/**
* @instances: user pointer to a 2-d array of struct
@ -779,14 +788,14 @@ struct drm_xe_engine_create {
__u64 reserved[2];
};
struct drm_xe_engine_get_property {
struct drm_xe_exec_queue_get_property {
/** @extensions: Pointer to the first extension struct, if any */
__u64 extensions;
/** @engine_id: Engine ID */
__u32 engine_id;
/** @exec_queue_id: Exec queue ID */
__u32 exec_queue_id;
#define XE_ENGINE_GET_PROPERTY_BAN 0
#define XE_EXEC_QUEUE_GET_PROPERTY_BAN 0
/** @property: property to get */
__u32 property;
@ -797,9 +806,9 @@ struct drm_xe_engine_get_property {
__u64 reserved[2];
};
struct drm_xe_engine_destroy {
/** @engine_id: Engine ID */
__u32 engine_id;
struct drm_xe_exec_queue_destroy {
/** @exec_queue_id: Exec queue ID */
__u32 exec_queue_id;
/** @pad: MBZ */
__u32 pad;
@ -846,8 +855,8 @@ struct drm_xe_exec {
/** @extensions: Pointer to the first extension struct, if any */
__u64 extensions;
/** @engine_id: Engine ID for the batch buffer */
__u32 engine_id;
/** @exec_queue_id: Exec queue ID for the batch buffer */
__u32 exec_queue_id;
/** @num_syncs: Amount of struct drm_xe_sync in array. */
__u32 num_syncs;

8
src/gallium/drivers/iris/iris_batch.c
View file

@ -860,12 +860,12 @@ iris_batch_name_to_string(enum iris_batch_name name)
}
static inline bool
context_or_engine_was_banned(struct iris_bufmgr *bufmgr, int ret)
context_or_exec_queue_was_banned(struct iris_bufmgr *bufmgr, int ret)
{
enum intel_kmd_type kmd_type = iris_bufmgr_get_device_info(bufmgr)->kmd_type;
/* In i915 EIO means our context is banned, while on Xe ECANCELED means
* our engine was banned
* our exec queue was banned
*/
if ((kmd_type == INTEL_KMD_TYPE_I915 && ret == -EIO) ||
(kmd_type == INTEL_KMD_TYPE_XE && ret == -ECANCELED))
@ -900,7 +900,7 @@ _iris_batch_flush(struct iris_batch *batch, const char *file, int line)
enum intel_kmd_type kmd_type = iris_bufmgr_get_device_info(bufmgr)->kmd_type;
uint32_t batch_ctx_id = kmd_type == INTEL_KMD_TYPE_I915 ?
batch->i915.ctx_id : batch->xe.engine_id;
batch->i915.ctx_id : batch->xe.exec_queue_id;
fprintf(stderr, "%19s:%-3d: %s batch [%u] flush with %5db (%0.1f%%) "
"(cmds), %4d BOs (%0.1fMb aperture)\n",
file, line, iris_batch_name_to_string(batch->name),
@ -957,7 +957,7 @@ _iris_batch_flush(struct iris_batch *batch, const char *file, int line)
* has been lost and needs to be re-initialized. If this succeeds,
* dubiously claim success...
*/
if (ret && context_or_engine_was_banned(bufmgr, ret)) {
if (ret && context_or_exec_queue_was_banned(bufmgr, ret)) {
enum pipe_reset_status status = iris_batch_check_for_reset(batch);
if (status != PIPE_NO_RESET || ice->context_reset_signaled)

2
src/gallium/drivers/iris/iris_batch.h
View file

@ -99,7 +99,7 @@ struct iris_batch {
uint32_t exec_flags;
} i915;
struct {
uint32_t engine_id;
uint32_t exec_queue_id;
} xe;
};

38
src/gallium/drivers/iris/xe/iris_batch.c
View file

@ -52,7 +52,7 @@ static bool
iris_xe_init_batch(struct iris_bufmgr *bufmgr,
struct intel_query_engine_info *engines_info,
enum intel_engine_class engine_class,
enum iris_context_priority priority, uint32_t *engine_id)
enum iris_context_priority priority, uint32_t *exec_queue_id)
{
struct drm_xe_engine_class_instance *instances;
@ -73,29 +73,29 @@ iris_xe_init_batch(struct iris_bufmgr *bufmgr,
instances[count++].gt_id = engine.gt_id;
}
struct drm_xe_engine_create create = {
struct drm_xe_exec_queue_create create = {
.instances = (uintptr_t)instances,
.vm_id = iris_bufmgr_get_global_vm_id(bufmgr),
.width = 1,
.num_placements = count,
};
struct drm_xe_engine_set_property engine_property = {
.property = XE_ENGINE_SET_PROPERTY_PRIORITY,
struct drm_xe_exec_queue_set_property exec_queue_property = {
.property = XE_EXEC_QUEUE_SET_PROPERTY_PRIORITY,
.value = iris_context_priority_to_drm_sched_priority(priority),
};
int ret = intel_ioctl(iris_bufmgr_get_fd(bufmgr),
DRM_IOCTL_XE_ENGINE_CREATE, &create);
DRM_IOCTL_XE_EXEC_QUEUE_CREATE, &create);
free(instances);
if (ret)
goto error_create_engine;
goto error_create_exec_queue;
engine_property.engine_id = create.engine_id;
intel_ioctl(iris_bufmgr_get_fd(bufmgr), DRM_IOCTL_XE_ENGINE_SET_PROPERTY,
&engine_property);
exec_queue_property.exec_queue_id = create.exec_queue_id;
intel_ioctl(iris_bufmgr_get_fd(bufmgr), DRM_XE_EXEC_QUEUE_SET_PROPERTY,
&exec_queue_property);
/* TODO: handle "protected" context/engine */
*engine_id = create.engine_id;
error_create_engine:
/* TODO: handle "protected" context/exec_queue */
*exec_queue_id = create.exec_queue_id;
error_create_exec_queue:
return ret == 0;
}
@ -132,7 +132,7 @@ void iris_xe_init_batches(struct iris_context *ice)
ASSERTED bool ret;
ret = iris_xe_init_batch(bufmgr, engines_info, engine_classes[name],
ice->priority, &batch->xe.engine_id);
ice->priority, &batch->xe.exec_queue_id);
assert(ret);
}
@ -143,12 +143,12 @@ void iris_xe_destroy_batch(struct iris_batch *batch)
{
struct iris_screen *screen = batch->screen;
struct iris_bufmgr *bufmgr = screen->bufmgr;
struct drm_xe_engine_destroy destroy = {
.engine_id = batch->xe.engine_id,
struct drm_xe_exec_queue_destroy destroy = {
.exec_queue_id = batch->xe.exec_queue_id,
};
ASSERTED int ret;
ret = intel_ioctl(iris_bufmgr_get_fd(bufmgr), DRM_IOCTL_XE_ENGINE_DESTROY,
ret = intel_ioctl(iris_bufmgr_get_fd(bufmgr), DRM_IOCTL_XE_EXEC_QUEUE_DESTROY,
&destroy);
assert(ret == 0);
}
@ -160,7 +160,7 @@ bool iris_xe_replace_batch(struct iris_batch *batch)
struct iris_bufmgr *bufmgr = screen->bufmgr;
struct iris_context *ice = batch->ice;
struct intel_query_engine_info *engines_info;
uint32_t new_engine_id;
uint32_t new_exec_queue_id;
bool ret;
engines_info = intel_engine_get_info(iris_bufmgr_get_fd(bufmgr),
@ -170,10 +170,10 @@ bool iris_xe_replace_batch(struct iris_batch *batch)
iris_xe_map_intel_engine_class(engines_info, engine_classes);
ret = iris_xe_init_batch(bufmgr, engines_info, engine_classes[batch->name],
ice->priority, &new_engine_id);
ice->priority, &new_exec_queue_id);
if (ret) {
iris_xe_destroy_batch(batch);
batch->xe.engine_id = new_engine_id;
batch->xe.exec_queue_id = new_exec_queue_id;
iris_lost_context_state(batch);
}

14
src/gallium/drivers/iris/xe/iris_kmd_backend.c
View file

@ -192,15 +192,15 @@ static enum pipe_reset_status
xe_batch_check_for_reset(struct iris_batch *batch)
{
enum pipe_reset_status status = PIPE_NO_RESET;
struct drm_xe_engine_get_property engine_get_property = {
.engine_id = batch->xe.engine_id,
.property = XE_ENGINE_GET_PROPERTY_BAN,
struct drm_xe_exec_queue_get_property exec_queue_get_property = {
.exec_queue_id = batch->xe.exec_queue_id,
.property = XE_EXEC_QUEUE_GET_PROPERTY_BAN,
};
int ret = intel_ioctl(iris_bufmgr_get_fd(batch->screen->bufmgr),
DRM_IOCTL_XE_ENGINE_GET_PROPERTY,
&engine_get_property);
DRM_IOCTL_XE_EXEC_QUEUE_GET_PROPERTY,
&exec_queue_get_property);
if (ret || engine_get_property.value)
if (ret || exec_queue_get_property.value)
status = PIPE_GUILTY_CONTEXT_RESET;
return status;
@ -383,7 +383,7 @@ xe_batch_submit(struct iris_batch *batch)
}
struct drm_xe_exec exec = {
.engine_id = batch->xe.engine_id,
.exec_queue_id = batch->xe.exec_queue_id,
.num_batch_buffer = 1,
.address = batch->exec_bos[0]->address,
.syncs = (uintptr_t)syncs,

2
src/intel/vulkan/anv_private.h
View file

@ -1065,7 +1065,7 @@ struct anv_queue {
union {
uint32_t exec_flags; /* i915 */
uint32_t engine_id; /* Xe */
uint32_t exec_queue_id; /* Xe */
};
/** Synchronization object for debug purposes (DEBUG_SYNC) */

6
src/intel/vulkan/xe/anv_batch_chain.c
View file

@ -45,7 +45,7 @@ xe_execute_simple_batch(struct anv_queue *queue, struct anv_bo *batch_bo,
.handle = syncobj_handle,
};
struct drm_xe_exec exec = {
.engine_id = queue->engine_id,
.exec_queue_id = queue->exec_queue_id,
.num_batch_buffer = 1,
.address = batch_bo->offset,
.num_syncs = 1,
@ -186,7 +186,7 @@ xe_queue_exec_utrace_locked(struct anv_queue *queue,
#endif
struct drm_xe_exec exec = {
.engine_id = queue->engine_id,
.exec_queue_id = queue->exec_queue_id,
.num_batch_buffer = 1,
.syncs = (uintptr_t)&xe_sync,
.num_syncs = 1,
@ -234,7 +234,7 @@ xe_queue_exec_locked(struct anv_queue *queue,
utrace_submit = NULL;
struct drm_xe_exec exec = {
.engine_id = queue->engine_id,
.exec_queue_id = queue->exec_queue_id,
.num_batch_buffer = 1,
.syncs = (uintptr_t)xe_syncs,
.num_syncs = xe_syncs_count,

12
src/intel/vulkan/xe/anv_device.c
View file

@ -164,14 +164,14 @@ anv_xe_device_check_status(struct vk_device *vk_device)
VkResult result = VK_SUCCESS;
for (uint32_t i = 0; i < device->queue_count; i++) {
struct drm_xe_engine_get_property engine_get_property = {
.engine_id = device->queues[i].engine_id,
.property = XE_ENGINE_GET_PROPERTY_BAN,
struct drm_xe_exec_queue_get_property exec_queue_get_property = {
.exec_queue_id = device->queues[i].exec_queue_id,
.property = XE_EXEC_QUEUE_GET_PROPERTY_BAN,
};
int ret = intel_ioctl(device->fd, DRM_IOCTL_XE_ENGINE_GET_PROPERTY,
&engine_get_property);
int ret = intel_ioctl(device->fd, DRM_IOCTL_XE_EXEC_QUEUE_GET_PROPERTY,
&exec_queue_get_property);
if (ret || engine_get_property.value) {
if (ret || exec_queue_get_property.value) {
result = vk_device_set_lost(&device->vk, "One or more queues banned");
break;
}

24
src/intel/vulkan/xe/anv_queue.c
View file

@ -78,19 +78,19 @@ anv_xe_create_engine(struct anv_device *device,
}
assert(device->vm_id != 0);
struct drm_xe_engine_create create = {
struct drm_xe_exec_queue_create create = {
/* Allows KMD to pick one of those engines for the submission queue */
.instances = (uintptr_t)instances,
.vm_id = device->vm_id,
.width = 1,
.num_placements = count,
};
int ret = intel_ioctl(device->fd, DRM_IOCTL_XE_ENGINE_CREATE, &create);
int ret = intel_ioctl(device->fd, DRM_IOCTL_XE_EXEC_QUEUE_CREATE, &create);
vk_free(&device->vk.alloc, instances);
if (ret)
return vk_errorf(device, VK_ERROR_UNKNOWN, "Unable to create engine");
return vk_errorf(device, VK_ERROR_UNKNOWN, "Unable to create exec queue");
queue->engine_id = create.engine_id;
queue->exec_queue_id = create.exec_queue_id;
const VkDeviceQueueGlobalPriorityCreateInfoKHR *queue_priority =
vk_find_struct_const(pCreateInfo->pNext,
@ -108,13 +108,13 @@ anv_xe_create_engine(struct anv_device *device,
if (priority > physical->max_context_priority)
goto priority_error;
struct drm_xe_engine_set_property engine_property = {
.engine_id = create.engine_id,
.property = XE_ENGINE_SET_PROPERTY_PRIORITY,
struct drm_xe_exec_queue_set_property exec_queue_property = {
.exec_queue_id = create.exec_queue_id,
.property = XE_EXEC_QUEUE_SET_PROPERTY_PRIORITY,
.value = anv_vk_priority_to_drm_sched_priority(priority),
};
ret = intel_ioctl(device->fd, DRM_IOCTL_XE_ENGINE_SET_PROPERTY,
&engine_property);
ret = intel_ioctl(device->fd, DRM_XE_EXEC_QUEUE_SET_PROPERTY,
&exec_queue_property);
if (ret && priority > VK_QUEUE_GLOBAL_PRIORITY_MEDIUM_KHR)
goto priority_error;
}
@ -129,8 +129,8 @@ priority_error:
void
anv_xe_destroy_engine(struct anv_device *device, struct anv_queue *queue)
{
struct drm_xe_engine_destroy destroy = {
.engine_id = queue->engine_id,
struct drm_xe_exec_queue_destroy destroy = {
.exec_queue_id = queue->exec_queue_id,
};
intel_ioctl(device->fd, DRM_IOCTL_XE_ENGINE_DESTROY, &destroy);
intel_ioctl(device->fd, DRM_IOCTL_XE_EXEC_QUEUE_DESTROY, &destroy);
}