Commit graph

37619 commits

Author SHA1 Message Date
Alyssa Rosenzweig
fcdfb67711 panfrost/midgard: Set integer mods
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
2019-04-24 02:22:32 +00:00
Alyssa Rosenzweig
422aceb407 panfrost/midgard: Document sign-extension/zero-extension bits (vector)
For floating point ops, these bits determine the "negate?" and "abs?"
modifiers. For integer ops, it turns out they control how sign/zero
extension work, useful for mixing types.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
2019-04-24 02:22:32 +00:00
Alyssa Rosenzweig
b453c877d9 panfrost/midgard: Update integer op list
In the future, we might want to switch to a table-based approach, but
for now, at least have it current.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
2019-04-24 02:22:32 +00:00
Alyssa Rosenzweig
0b380a7868 panfrost/midgard: Remove unused mir_next_block
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
2019-04-24 02:22:32 +00:00
Alyssa Rosenzweig
879ff866b6 panfrost/midgard: Fix off-by-one in successor analysis
This reduces register pressure substantially since we get smaller
liveness ranges.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
2019-04-24 02:22:31 +00:00
Alyssa Rosenzweig
521ac6e5b1 panfrost/midgard: Track loop depth
This fixes nested loops.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
2019-04-24 02:22:31 +00:00
Alyssa Rosenzweig
84f09ff433 panfrost/midgard: Dead code eliminate MIR
We reshuffle the existing "dead move elimination" pass into a generic
dead code elimination layer, fixing bugs incurred with looping in the
process.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
2019-04-24 02:22:31 +00:00
Alyssa Rosenzweig
328a5ef598 panfrost: Use actual imov instruction
The bug this worked around is no longer applicable, it seems -- remove
the hack that breaks more than it fixes.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
2019-04-24 02:22:31 +00:00
Alyssa Rosenzweig
12cd89da81 panfrost: Disable indirect outputs for now
The hardware needs this lowered anyway; for now, might as well use
mesa's default lowering for pure conformance reasons.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
2019-04-24 02:22:31 +00:00
Alyssa Rosenzweig
9db5816e02 panfrost/midgard: imul can only run on *mul
This restriction makes sense logically. Not sure why it wasn't obeyed
before. In conjunction with previous commit's disclaimer, fixes
dEQP-GLES2.functional.shaders.loop.for_dynamic_iterations.*

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
2019-04-24 02:22:31 +00:00
Alyssa Rosenzweig
a1aaf72915 panfrost/midgard: Don't try to inline constants on branches
Along with a corresponding fix to the move elimination pass (not
included here yet -- I just have it disabled for now), this will fix
dEQP-GLES2.functional.shaders.loops.for_uniform_iterations.*

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
2019-04-24 02:22:31 +00:00
Alyssa Rosenzweig
c0fb2605dc panfrost: Respect backwards branches in RA
Fixes a bunch of issues with looping. Honestly, I'm not sure why loops
worked at all before.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
2019-04-24 02:22:31 +00:00
Alyssa Rosenzweig
7d45bd9c91 panfrost/midgard: Remove useless MIR dump
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
2019-04-24 02:22:31 +00:00
Alyssa Rosenzweig
8b15f8a343 panfrost/midgard: Respect component of bcsel condition
Fixes a bunch of non-vec4 indexing.varying_array tests.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
2019-04-24 02:22:31 +00:00
Alyssa Rosenzweig
6a466c0a06 panfrost/midgard: Implement indirect loads of varyings/UBOs
This adds preliminary support for indirect loads of varying arrays and
uniform arrays, bringing a few new tests in shader.indexing.* to
passing, although there remains a number of cases still missing.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
2019-04-24 02:22:31 +00:00
Alyssa Rosenzweig
1f7b3884c9 panfrost/midgard: Pipe through varying arrays
Varying arrays sometimes are lowered to a series of directly accessed
varyings (which we handled okay), but when indirectly accessed, they
appear as a single array; we need to handle this as well.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
2019-04-24 02:22:31 +00:00
Alyssa Rosenzweig
042d0bb5c3 panfrost/mdg/disasm: Print raw varying_parameters
The semantics of this field are not well understood; it is better to
print it unconditionally along with the other unknown state, rather than
silently eat the value. Without this change, some critical state was
being lost in some shaders (notably, the offset for load/store
scratchpad intructions found in shaders that spill registers.)

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
2019-04-24 02:22:31 +00:00
Kenneth Graunke
864873dea9 iris: Prefer staging blits when destination supports CCS_E.
Otherwise our textures don't get color compression.  Thanks to
Eero Tamminen for noticing this was missing!

Improves performance of GLB27_FillTestC24Z16 on my Apollolake
laptop with single channel RAM by 2.3x.

Reported-by: Eero Tamminen <eero.t.tamminen@intel.com>
2019-04-23 18:59:27 -07:00
Marek Olšák
d8b296d3ad gallium: replace drm_driver_descriptor::configuration with driconf_xml
PIPE_CAPs are better.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2019-04-23 21:20:26 -04:00
Marek Olšák
8ae50e6004 gallium: replace DRM_CONF_SHARE_FD with PIPE_CAP_DMABUF
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2019-04-23 21:20:26 -04:00
Marek Olšák
e3841368f3 gallium: replace DRM_CONF_THROTTLE with PIPE_CAP_MAX_FRAMES_IN_FLIGHT
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2019-04-23 21:20:24 -04:00
Marek Olšák
a20800f49d st/dri: simplify throttling code
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2019-04-23 21:19:48 -04:00
Marek Olšák
d9838f653a gallium: document conservative rasterization flags
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2019-04-23 21:19:48 -04:00
Timothy Arceri
a6b7068ff5 st/mesa/radeonsi: fix race between destruction of types and shader compilation
Commit 624789e370 moved the destruction of types out of atexit() and
made use of a ref count instead. This is useful for avoiding a crash
where drivers such as radeonsi are still compiling in a thread when the app
exits and has not called MakeCurrent to change from the current context.

While the above scenario is technically an app bug we shouldn't crash.
However that change caused another race condition between the shader
compilation tread in radeonsi and context teardown functions.

This patch makes two changes to fix this new problem:

First we explicitly call _mesa_destroy_shader_compiler_types() when destroying
the st context rather than calling it indirectly via _mesa_free_context_data().
We do this as we must call it after st_destroy_context_priv() so that we don't
destory the glsl types before the compilation threads finish.

Next wait for the shader threads to finish in si_destroy_context() this
also means we need to call context destroy before destroying the queues
in si_destroy_screen().

Fixes: 624789e370 ("compiler/glsl: handle case where we have multiple users for types")

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2019-04-24 10:23:10 +10:00
Mike Blumenkrantz
b53d256db8 iris: add support for INTEL_conservative_rasterization
this hooks up the iris gallium driver to existing mesa bits which handle
the implementation

resolves kwg/mesa#8

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2019-04-23 16:36:30 -07:00
Mike Blumenkrantz
1b9041c76a gallium: add pipe cap for inner_coverage conservative raster mode
this can be used by drivers which support the extension to indicate support

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2019-04-23 16:36:00 -07:00
Kenneth Graunke
2208d5a683 iris: Fix DrawTransformFeedback math when there's a buffer offset
We need to subtract the starting offset from the final offset before
dividing by the stride.  See src/intel/vulkan/genX_cmd_buffer.c:3142.

Not known to fix anything.
2019-04-23 15:57:07 -07:00
Kenneth Graunke
38db20245b iris: Make some offset math helpers take a const isl_surf pointer 2019-04-23 15:47:10 -07:00
Chia-I Wu
cc53815ae1 virgl: skip empty cmdbufs
Several empty cmdbufs are submitted by app/xserver per frame, from
glamor_block_handler for example.  Let's skip them.

Signed-off-by: Chia-I Wu <olvaffe@gmail.com>
Reviewed-by: Gurchetan Singh <gurchetansingh@chromium.org>
2019-04-23 19:07:48 +00:00
Eric Anholt
ec686a66db gallium: Remove the malloc pipebuffer manager.
This has been unused since r600 stopped using it in 2010.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
Reviewed-by: Kristian Høgsberg <hoegsberg@gmail.com>
2019-04-23 10:36:07 -07:00
Eric Anholt
6345dfc8f3 gallium: Remove the "alt" pipebuffer manager interface.
This one would allocate from two underlying pools, but has never been
used.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
Reviewed-by: Kristian Høgsberg <hoegsberg@gmail.com>
2019-04-23 10:36:07 -07:00
Eric Anholt
8e31a4f27f gallium: Remove the ondemand pipebuffer manager.
I couldn't find any uses in the tree since its introduction.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
Reviewed-by: Kristian Høgsberg <hoegsberg@gmail.com>
2019-04-23 10:36:07 -07:00
Eric Anholt
f5c08d9818 gallium: Remove the pool pipebuffer manager.
Noticed while trying to decide if pipebuffer was of any use to me, and
found that nothing has used it in the last 10 years at least.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
Reviewed-by: Kristian Høgsberg <hoegsberg@gmail.com>
2019-04-23 10:36:07 -07:00
Jonathan Marek
d133f55a99 freedreno: a2xx: same gmem2mem sequence for all tiles
Set REG_A2XX_RB_COPY_DEST_OFFSET in the tile init as it won't get touched
by the draw batch. Then gmem2mem is the same for all tiles.

Similar to what is done in a6xx, but only for gmem2mem.

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Rob Clark <robdclark@gmail.com>
2019-04-23 17:13:32 +00:00
Jonathan Marek
4107e0678a freedreno: a2xx: enable batch reordering
Batch reordering on a2xx is now tested and functional.

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Rob Clark <robdclark@gmail.com>
2019-04-23 17:13:32 +00:00
Jonathan Marek
7f670ca5fd freedreno: a2xx: use nir_lower_io for TGSI shaders
Allows removing the load_deref/store_deref code in the compiler.

tgsi_to_nir now uses screen instead of options so we can simplify that too.

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Rob Clark <robdclark@gmail.com>
2019-04-23 17:13:32 +00:00
Jonathan Marek
bce4f11dbc freedreno: a2xx: disable PIPE_CAP_PACKED_UNIFORMS
a2xx driver is currently broken when PIPE_CAP_PACKED_UNIFORMS is enabled,
disable it for now.

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Reviewed-by: Rob Clark <robdclark@gmail.com>
2019-04-23 17:13:32 +00:00
Jonathan Marek
418c3d9a4f freedreno: a2xx: fix builtin blit program compilation
tgsi_to_nir now requires a screen pointer and is used by fd2_prog_init.
fd2_prog_init is used before fd_context_init so set the pointer manually.

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Rob Clark <robdclark@gmail.com>
2019-04-23 17:13:32 +00:00
Jonathan Marek
33cafb41a2 svga: add new ATC formats to the format conversion table
Fixes the static assertion error.

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
2019-04-23 17:11:56 +00:00
Jonathan Marek
0e696416f9 freedreno: a2xx: add GL_AMD_compressed_ATC_texture support
Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
2019-04-23 17:11:56 +00:00
Jonathan Marek
734409096b freedreno: a3xx: add GL_AMD_compressed_ATC_texture support
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
2019-04-23 17:11:56 +00:00
Jonathan Marek
bfa72e4d52 llvmpipe, softpipe: no support for ATC textures
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
2019-04-23 17:11:56 +00:00
Jonathan Marek
ea254fcd3c gallium: add ATC format support
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
2019-04-23 17:11:56 +00:00
Marek Olšák
951d60f8cd radeonsi: delay adding BOs at the beginning of IBs until the first draw
so that bound compute shader resources won't be added when they are not
needed and same for graphics.

Acked-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2019-04-23 11:36:36 -04:00
Marek Olšák
09bb8c8557 radeonsi: add helper si_get_minimum_num_gfx_cs_dwords
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Acked-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2019-04-23 11:36:34 -04:00
Marek Olšák
c59d238bb0 radeonsi: add si_cp_copy_data
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Acked-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2019-04-23 11:36:33 -04:00
Marek Olšák
694e320643 winsys/amdgpu: clean up and remove nonsensical assertion
The assertion considers max_dw from the current IB in the chain, but
big_ib_buffer is a buffer for the next IB, which can be smaller.

Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Acked-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2019-04-23 11:36:31 -04:00
Marek Olšák
1807f6cfe9 winsys/amdgpu: enable chaining for compute IBs
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Acked-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2019-04-23 11:36:06 -04:00
Marek Olšák
b99bed6246 winsys/amdgpu: reorder chunks, make BO_HANDLES first, IB and FENCE last
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Acked-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2019-04-23 11:28:56 -04:00
Marek Olšák
437d032b7d winsys/amdgpu: make IBs writable and expose their address
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Acked-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2019-04-23 11:28:56 -04:00