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Author SHA1 Message Date
Rhys Perry
869253b66c aco: support VS prologs with unaligned access 
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29071>
 2024-05-13 17:22:26 +00:00
Rhys Perry
9ec2fa392f aco: copy VS prolog constants after loads 
This way, the loads start earlier.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29071>
 2024-05-13 17:22:26 +00:00
Rhys Perry
46b8ba8154 aco: form hard clauses in VS prologs 
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29071>
 2024-05-13 17:22:26 +00:00
Marek Olšák
58a5de5c34 amd: add gfx12 register definitions into the register header generator 
The generator renamed some definitions to resolve conflicts.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Acked-by: Timur Kristóf <timur.kristof@gmail.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29007>
 2024-05-11 22:14:05 -04:00
Samuel Pitoiset
53a142ad23 aco: add support for remapping color attachments 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27263>
 2024-05-07 10:35:04 +00:00
Daniel Schürmann
2d0c6647f0 aco: use SGPR phi lowering for all scalar phis 
No fossil-db changes.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28661>
 2024-04-26 08:39:01 +00:00
Daniel Schürmann
6ec6899bff aco: use SGPR phi lowering for all loop header phis 
No fossil-db changes.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28661>
 2024-04-26 08:39:01 +00:00
Daniel Schürmann
7c01193299 aco: use SGPR phi lowering for uniform phis in divergent merge blocks 
The fossil changes are due to a slightly different register allocation
from a reversed order of phi instructions.

Totals from 1620 (2.04% of 79395) affected shaders: (GFX10.3)

Instrs: 730683 -> 732621 (+0.27%); split: -0.02%, +0.28%
CodeSize: 3888464 -> 3898488 (+0.26%); split: -0.00%, +0.26%
Latency: 3274291 -> 3275549 (+0.04%); split: -0.02%, +0.06%
InvThroughput: 606625 -> 606661 (+0.01%); split: -0.00%, +0.01%
VClause: 9541 -> 9538 (-0.03%)
SClause: 17296 -> 17272 (-0.14%); split: -0.16%, +0.02%
Copies: 81392 -> 83231 (+2.26%); split: -0.17%, +2.43%
Branches: 27023 -> 27020 (-0.01%); split: -0.03%, +0.02%
VALU: 383380 -> 382749 (-0.16%)
SALU: 160895 -> 163369 (+1.54%); split: -0.03%, +1.57%
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28661>
 2024-04-26 08:39:01 +00:00
Daniel Schürmann
6e3446422f aco: introduce aco_opcode::p_boolean_phi 
This opcode is only used during instruction selection and
immediately lowered to linear phis afterwards.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28661>
 2024-04-26 08:39:01 +00:00
Rhys Perry
37e9e8b06c aco: split vop3p results 
Removes copies in the case of:
a = fmul
b = fmul
c = vec4(a.x, a.y, b.x, b.y)

fossil-db (navi31):
Totals from 21 (0.03% of 79395) affected shaders:
Instrs: 96481 -> 96338 (-0.15%)
CodeSize: 548452 -> 548196 (-0.05%); split: -0.13%, +0.09%
Latency: 1514460 -> 1514238 (-0.01%); split: -0.02%, +0.00%
InvThroughput: 683048 -> 682942 (-0.02%); split: -0.02%, +0.00%
VClause: 1611 -> 1613 (+0.12%)
Copies: 21326 -> 21190 (-0.64%)
Branches: 2427 -> 2426 (-0.04%)
PreVGPRs: 2289 -> 2298 (+0.39%)
VALU: 59090 -> 58954 (-0.23%)

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28763>
 2024-04-23 12:31:59 +00:00
Georg Lehmann
4b5016a537 aco: support high_16bits FS IO 
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28435>
 2024-04-10 07:49:27 +00:00
Georg Lehmann
893ee883fe aco: use v1 definition for v_interp_p1lv_f16 
The result of the first interpolation step is always fp32.

Fixes: 1647e098e9 ("aco: implement 16-bit interp")
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28435>
 2024-04-10 07:49:26 +00:00
Rhys Perry
0f2d5ed75c aco: assume no unreachable blocks 
These shouldn't happen anymore.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28301>
 2024-04-08 18:38:39 +00:00
Rhys Perry
543ca160a5 nir,aco: add test intrinsics 
These don't really do anything. They're just a source and user of SSA
defs.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28301>
 2024-04-08 18:38:39 +00:00
Rhys Perry
0a25af1d4e aco: save/reset/combine has_divergent_continue in uniform branches 
For
if (uniform) {
   if (divergent)
      continue
} else {
   break
}
we don't need to consider the continue to be divergent.

No fossil-db changes.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28301>
 2024-04-08 18:38:39 +00:00
Rhys Perry
46c734ff02 aco: ensure loop exits exist in NIR 
This simplifies instruction selection and fixes the case where the loop
ends with a continue instruction.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28301>
 2024-04-08 18:38:39 +00:00
Samuel Pitoiset
7a69d78ba2 aco: use SPDX-License-Identifier 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28622>
 2024-04-08 15:49:25 +00:00
Rhys Perry
6b301eae36 aco: implement mqsad_4x8 and shfr 
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26251>
 2024-04-05 11:01:39 +00:00
Timur Kristóf
8883b88dd4 aco: Delete all TCS epilog code. 
Now that neither RADV nor RadeonSI uses TCS epilogs, we don't
need to keep the code to compile them in ACO either.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28425>
 2024-03-30 21:56:39 +01:00
Timur Kristóf
3fd002f6d5 radv, aco: Remove the code that jumped to RADV's TCS epilogs. 
The actual TCS epilog selection code is kept unchanged for now,
we'll delete it when RadeonSI also gets rid of TCS epilogs.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28408>
 2024-03-28 23:44:03 +00:00
Daniel Schürmann
a863c7951e aco: remove create_instruction() template parameter 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28370>
 2024-03-28 11:25:43 +00:00
Daniel Schürmann
9b0ebcc39b aco: change return type of create_instruction() to Instruction* 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28370>
 2024-03-28 11:25:43 +00:00
Daniel Schürmann
1187189235 aco: unify different SALU types into single struct SALU_instruction 
This removes
- SOP1_instruction
- SOP2_instruction
- SOPC_instruction
- SOPK_instruction
- SOPP_instruction

and their corresponding methods.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28370>
 2024-03-28 11:25:43 +00:00
Daniel Schürmann
5d265257a0 aco: remove SOPP_instruction::block member 
Re-use SOPP_instruction::imm instead.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28370>
 2024-03-28 11:25:43 +00:00
Timur Kristóf
fcf574f4c1 radv, aco: Delete now dead TCS epilog code. 
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28371>
 2024-03-28 09:41:08 +00:00
Timur Kristóf
023d7fc76d aco: Use tess factors when TCS jumps to epilog. 
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28371>
 2024-03-28 09:41:08 +00:00
Timur Kristóf
3422084026 aco: Use common helper for counting tess level components. 
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28371>
 2024-03-28 09:41:08 +00:00
Marek Olšák
6773595ed0 nir: rename AMD XFB intrinsics to *_gfx11_amd 
to indicate it's only for gfx11.

Acked-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27952>
 2024-03-22 21:58:02 +00:00
Daniel Schürmann
9bbb9f1104 aco: use small_vec as Block::edge_vec for predecessors and successors 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27984>
 2024-03-19 13:06:58 +00:00
Georg Lehmann
67997fd735 aco: avoid full 32bit imul for uniform reduce/scan 
Foz-DB Navi31:
Totals from 24 (0.03% of 79395) affected shaders:
Instrs: 1172275 -> 1172078 (-0.02%)
CodeSize: 5974424 -> 5973860 (-0.01%)
Latency: 5896216 -> 5895923 (-0.00%)
InvThroughput: 1167928 -> 1167869 (-0.01%)
VALU: 625756 -> 625636 (-0.02%)

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28223>
 2024-03-18 13:37:28 +00:00
Rhys Perry
ec892c4d2b aco: don't reuse misaligned attribute destination VGPRs in VS prologs 
Since we split misaligned attributes, we could overwrite one of these
VGPRs in the middle of loading the attribute.

For example:
   v_add_u32_e32 v4, vcc, s7, v1
   s_waitcnt lgkmcnt(0)
   buffer_load_dword v4, v4, s[32:35], 0 idxen
   buffer_load_dword v5, v4, s[32:35], 0 idxen offset:4
can overwrite the vertex index in the load of the first component.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27920>
 2024-03-14 15:30:12 +00:00
Rhys Perry
df7024bcdd radv,aco: allow VS prologs to increase VGPR usage 
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27920>
 2024-03-14 15:30:12 +00:00
Samuel Pitoiset
0ed6aba85a radv,aco: stop duplicating PS/TCS epilog fields 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28042>
 2024-03-08 07:28:47 +00:00
Konstantin Seurer
eb249bb18e aco: Only fix used variables to registers 
Reviewed-by: Friedrich Vock <friedrich.vock@gmx.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27137>
 2024-03-07 20:07:07 +00:00
Rhys Perry
07eab4ab40 aco: require linear vgpr uses to be late kill 
This also removes some linear VGPR tests which will be replaced soon
anyway.

fossil-db (navi31):
Totals from 107 (0.14% of 79242) affected shaders:
Instrs: 66203 -> 66211 (+0.01%); split: -0.09%, +0.10%
CodeSize: 354644 -> 354588 (-0.02%); split: -0.08%, +0.07%
VGPRs: 4476 -> 4452 (-0.54%); split: -0.80%, +0.27%
Latency: 513863 -> 513877 (+0.00%); split: -0.08%, +0.08%
InvThroughput: 68871 -> 68870 (-0.00%); split: -0.02%, +0.02%
SClause: 1589 -> 1590 (+0.06%)
PreVGPRs: 3404 -> 3415 (+0.32%)

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27697>
 2024-03-06 12:55:45 +00:00
Rhys Perry
5e17a39b15 aco: allow p_start_linear_vgpr to use multiple operands 
Merging the p_create_vector into the p_start_linear_vgpr is useful since
we stopped attempting to place the p_start_linear_vgpr definition in the
same registers as the operand.

fossil-db (navi31):
Totals from 927 (1.17% of 79242) affected shaders:
MaxWaves: 26412 -> 26442 (+0.11%)
Instrs: 938328 -> 938181 (-0.02%); split: -0.14%, +0.13%
CodeSize: 4891448 -> 4890820 (-0.01%); split: -0.11%, +0.10%
VGPRs: 47016 -> 47004 (-0.03%); split: -0.13%, +0.10%
SpillSGPRs: 222 -> 226 (+1.80%)
Latency: 5076065 -> 5075191 (-0.02%); split: -0.12%, +0.10%
InvThroughput: 712316 -> 712421 (+0.01%); split: -0.09%, +0.10%
SClause: 27992 -> 27972 (-0.07%); split: -0.09%, +0.02%
Copies: 38042 -> 38104 (+0.16%); split: -1.95%, +2.12%
PreVGPRs: 39448 -> 39369 (-0.20%)
VALU: 570157 -> 570224 (+0.01%); split: -0.13%, +0.14%
SALU: 51672 -> 51678 (+0.01%); split: -0.01%, +0.02%

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27697>
 2024-03-06 12:55:45 +00:00
Chia-I Wu
3d4dfae7eb aco: fix nir_op_pack_32_4x8 handling 
I started seeing

  ACO ERROR:
      In file ../src/amd/compiler/aco_validate.cpp:98
      Operand and Definition types do not match:  s1: %44 = p_parallelcopy %158
  test_basic: ../src/amd/compiler/aco_interface.cpp:85: void validate(aco::Program*):
      Assertion `is_valid' failed.

since commit 52ee4cf229 ("nir/builder: Teach nir_pack_bits and
nir_unpack_bits about 32_4x8").

Fixes: e0d232c2fc ("aco: implement nir_op_pack_32_4x8").  I
Suggested-by: Georg Lehmann <dadschoorse@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27972>
 2024-03-05 20:38:34 +00:00
Georg Lehmann
230743da2e nir: remove rotate scope 
All other subgroup operations do not have a scope in NIR, so for consistency
rotate shouldn't have one either.

Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27964>
 2024-03-05 14:12:21 +00:00
Bas Nieuwenhuizen
c7b2ac3377 radv: Remove ray_launch_size_addr_amd system value. 
Not used anymore, so clean it up.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27664>
 2024-02-17 11:08:16 +00:00
Daniel Schürmann
2649717a36 aco: enable WQM if demote is used with maximal reconvergence 
If otherwise no helper lanes are required by the shader, then demote
behaves like discard and immediately terminates the invocations.
With maximal reconvergence, however, we need to ensure that helper lanes
are not terminated unless the entire quad was demoted.
In order to fix this, generally enable helper lanes in this unlikely
corner case and avoid a major refactor.

Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27277>
 2024-02-09 05:32:35 +00:00
Marek Olšák
72948d9ff9 radeonsi,aco: remove the VS prolog 
The upside is that this removes 600 lines of code. The downside is
that if instance divisors are used, we will compile the VS on demand.

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27120>
 2024-02-07 09:50:53 +00:00
Georg Lehmann
4c74077b62 aco: implement rotate 
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27118>
 2024-01-24 16:38:40 +00:00
Georg Lehmann
0a03cf5b3c aco: remove boolean shuffle isel 
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27116>
 2024-01-19 20:13:34 +00:00
Georg Lehmann
6b031daf16 aco: implement as_uniform and ballot_relaxed 
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27116>
 2024-01-19 20:13:34 +00:00
Rhys Perry
ae54cbeb3f nir: remove sad_u8x4 
All uses of this can be replaced with msad_4x8.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26907>
 2024-01-05 18:55:22 +00:00
Rhys Perry
1410735a62 aco: implement msad_4x8 
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26907>
 2024-01-05 18:55:22 +00:00
Friedrich Vock
1e3541728b radv,aco: Convert 1D ray launches to 2D 
Because we use unaligned dispatches, 1D launches only use 8 threads per
wave. Converting to 2D and fixing up launch IDs in the prolog
significantly increases occupancy.

Gives ~30% uplift in Ghostwire Tokyo.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26105>
 2024-01-05 17:08:05 +00:00
Georg Lehmann
71edf4de5e aco/gfx12: implement broadcast dmask shrink behavior 
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26897>
 2024-01-05 12:03:54 +00:00
Georg Lehmann
4a6ee2c483 aco: shrink buffer stores with undef/zero components 
Buffer stores store 0 like image stores for unspecified components.

Foz-DB Navi21:
Totals from 91 (0.11% of 79330) affected shaders:
Instrs: 63327 -> 63121 (-0.33%)
CodeSize: 315312 -> 314440 (-0.28%); split: -0.28%, +0.00%
VGPRs: 3144 -> 3120 (-0.76%)
Latency: 441424 -> 441300 (-0.03%); split: -0.03%, +0.00%
InvThroughput: 65501 -> 65130 (-0.57%)
Copies: 6197 -> 5999 (-3.20%)
PreVGPRs: 2197 -> 2182 (-0.68%)

Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26897>
 2024-01-05 12:03:54 +00:00
Georg Lehmann
9ecfd7919b aco: optimize 32bit fsign by using fmulz with Inf 
2 instruction fsign with the power of cursed DX9 floating point rules.

Foz-DB Navi31:
Totals from 3803 (4.86% of 78196) affected shaders:
Instrs: 8436366 -> 8412549 (-0.28%); split: -0.29%, +0.00%
CodeSize: 43174284 -> 43114676 (-0.14%); split: -0.14%, +0.01%
SpillSGPRs: 3241 -> 3247 (+0.19%)
Latency: 66333841 -> 66287361 (-0.07%); split: -0.08%, +0.01%
InvThroughput: 10331902 -> 10316916 (-0.15%); split: -0.15%, +0.01%
VClause: 165455 -> 165472 (+0.01%); split: -0.01%, +0.02%
SClause: 242352 -> 242335 (-0.01%); split: -0.02%, +0.01%
Copies: 604086 -> 605781 (+0.28%); split: -0.04%, +0.32%
Branches: 214017 -> 214013 (-0.00%)
PreSGPRs: 209413 -> 209726 (+0.15%)

Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26765>
 2024-01-02 13:07:30 +01:00