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radv,aco: stop duplicating PS/TCS epilog fields

Browse source 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28042>
This commit is contained in:
Samuel Pitoiset 2024-03-07 13:20:27 +01:00 • committed by Marge Bot
parent 974d1395a2
commit 0ed6aba85a
7 changed files with 16 additions and 21 deletions
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5
src/amd/compiler/aco_instruction_selection.cpp
View file

@ -11130,7 +11130,7 @@ create_fs_jump_to_epilog(isel_context* ctx)
}
}
Temp continue_pc = convert_pointer_to_64_bit(ctx, get_arg(ctx, ctx->program->info.ps.epilog_pc));
Temp continue_pc = convert_pointer_to_64_bit(ctx, get_arg(ctx, ctx->program->info.epilog_pc));
aco_ptr<Pseudo_instruction> jump{create_instruction<Pseudo_instruction>(
aco_opcode::p_jump_to_epilog, Format::PSEUDO, 1 + exports.size(), 0)};
@ -11275,8 +11275,7 @@ create_tcs_jump_to_epilog(isel_context* ctx)
Operand::c32(0u), Operand::c32(8u), Operand::c32(0u));
rel_patch_id.setFixed(vgpr_start.advance(8u));
Temp continue_pc =
convert_pointer_to_64_bit(ctx, get_arg(ctx, ctx->program->info.tcs.epilog_pc));
Temp continue_pc = convert_pointer_to_64_bit(ctx, get_arg(ctx, ctx->program->info.epilog_pc));
aco_ptr<Pseudo_instruction> jump{
create_instruction<Pseudo_instruction>(aco_opcode::p_jump_to_epilog, Format::PSEUDO, 9, 0)};

5
src/amd/compiler/aco_shader_info.h
View file

@ -137,6 +137,7 @@ struct aco_shader_info {
bool has_epilog; /* Only for TCS or PS. */
bool merged_shader_compiled_separately; /* GFX9+ */
struct ac_arg next_stage_pc;
struct ac_arg epilog_pc; /* Vulkan only */
struct {
bool tcs_in_out_eq;
uint64_t tcs_temp_only_input_mask;
@ -147,7 +148,6 @@ struct aco_shader_info {
/* Vulkan only */
uint32_t num_lds_blocks;
struct ac_arg epilog_pc;
uint32_t num_linked_outputs;
uint32_t num_linked_patch_outputs;
uint32_t tcs_vertices_out;
@ -163,9 +163,6 @@ struct aco_shader_info {
unsigned spi_ps_input_ena;
unsigned spi_ps_input_addr;
/* Vulkan only */
struct ac_arg epilog_pc;
/* OpenGL only */
struct ac_arg alpha_reference;
} ps;

3
src/amd/vulkan/radv_aco_shader_info.h
View file

@ -64,9 +64,8 @@ radv_aco_convert_shader_info(struct aco_shader_info *aco_info, const struct radv
aco_info->gfx9_gs_ring_lds_size = radv->gs_ring_info.lds_size;
aco_info->is_trap_handler_shader = radv->type == RADV_SHADER_TYPE_TRAP_HANDLER;
aco_info->image_2d_view_of_3d = radv_key->image_2d_view_of_3d;
aco_info->ps.epilog_pc = radv_args->ps_epilog_pc;
aco_info->epilog_pc = radv_args->epilog_pc;
aco_info->hw_stage = radv_select_hw_stage(radv, gfx_level);
aco_info->tcs.epilog_pc = radv_args->tcs_epilog_pc;
aco_info->tcs.tcs_offchip_layout = radv_args->tcs_offchip_layout;
aco_info->next_stage_pc = radv_args->next_stage_pc;
}

4
src/amd/vulkan/radv_cmd_buffer.c
View file

@ -1882,7 +1882,7 @@ radv_emit_ps_epilog_state(struct radv_cmd_buffer *cmd_buffer, struct radv_shader
assert((ps_epilog->va >> 32) == cmd_buffer->device->physical_device->rad_info.address32_hi);
struct radv_userdata_info *loc = &ps_shader->info.user_sgprs_locs.shader_data[AC_UD_PS_EPILOG_PC];
struct radv_userdata_info *loc = &ps_shader->info.user_sgprs_locs.shader_data[AC_UD_EPILOG_PC];
uint32_t base_reg = ps_shader->info.user_data_0;
assert(loc->sgpr_idx != -1);
assert(loc->num_sgprs == 1);
@ -1921,7 +1921,7 @@ radv_emit_tcs_epilog_state(struct radv_cmd_buffer *cmd_buffer, struct radv_shade
assert((tcs_epilog->va >> 32) == cmd_buffer->device->physical_device->rad_info.address32_hi);
struct radv_userdata_info *loc = &tcs->info.user_sgprs_locs.shader_data[AC_UD_TCS_EPILOG_PC];
struct radv_userdata_info *loc = &tcs->info.user_sgprs_locs.shader_data[AC_UD_EPILOG_PC];
uint32_t base_reg = tcs->info.user_data_0;
assert(loc->sgpr_idx != -1);
assert(loc->num_sgprs == 1);

5
src/amd/vulkan/radv_shader.h
View file

@ -217,12 +217,12 @@ enum radv_ud_index {
AC_UD_TASK_RING_ENTRY = 13,
AC_UD_NUM_VERTS_PER_PRIM = 14,
AC_UD_NEXT_STAGE_PC = 15,
AC_UD_SHADER_START = 16,
AC_UD_EPILOG_PC = 16,
AC_UD_SHADER_START = 17,
AC_UD_VS_VERTEX_BUFFERS = AC_UD_SHADER_START,
AC_UD_VS_BASE_VERTEX_START_INSTANCE,
AC_UD_VS_PROLOG_INPUTS,
AC_UD_VS_MAX_UD,
AC_UD_PS_EPILOG_PC,
AC_UD_PS_STATE,
AC_UD_PS_MAX_UD,
AC_UD_CS_GRID_SIZE = AC_UD_SHADER_START,
@ -236,7 +236,6 @@ enum radv_ud_index {
AC_UD_CS_MAX_UD,
AC_UD_GS_MAX_UD,
AC_UD_TCS_OFFCHIP_LAYOUT = AC_UD_VS_MAX_UD,
AC_UD_TCS_EPILOG_PC,
AC_UD_TCS_MAX_UD,
/* We might not know the previous stage when compiling a geometry shader, so we just
* declare both TES and VS user SGPRs.

10
src/amd/vulkan/radv_shader_args.c
View file

@ -411,7 +411,7 @@ declare_unmerged_vs_tcs_args(const enum amd_gfx_level gfx_level, const struct ra
add_ud_arg(args, 1, AC_ARG_INT, &args->ac.view_index, AC_UD_VIEW_INDEX);
add_ud_arg(args, 1, AC_ARG_INT, &args->tcs_offchip_layout, AC_UD_TCS_OFFCHIP_LAYOUT);
add_ud_arg(args, 1, AC_ARG_INT, &args->tcs_epilog_pc, AC_UD_TCS_EPILOG_PC);
add_ud_arg(args, 1, AC_ARG_INT, &args->epilog_pc, AC_UD_EPILOG_PC);
add_ud_arg(args, 1, AC_ARG_INT, &args->next_stage_pc, AC_UD_NEXT_STAGE_PC);
/* VGPRs (TCS first, then VS) */
@ -436,7 +436,7 @@ declare_unmerged_vs_tcs_args(const enum amd_gfx_level gfx_level, const struct ra
ac_add_preserved(&args->ac, &args->ac.push_constants);
ac_add_preserved(&args->ac, &args->ac.view_index);
ac_add_preserved(&args->ac, &args->tcs_offchip_layout);
ac_add_preserved(&args->ac, &args->tcs_epilog_pc);
ac_add_preserved(&args->ac, &args->epilog_pc);
/* Preserved VGPRs */
ac_add_preserved(&args->ac, &args->ac.tcs_patch_id);
@ -677,7 +677,7 @@ declare_shader_args(const struct radv_device *device, const struct radv_graphics
}
if (info->has_epilog) {
add_ud_arg(args, 1, AC_ARG_INT, &args->tcs_epilog_pc, AC_UD_TCS_EPILOG_PC);
add_ud_arg(args, 1, AC_ARG_INT, &args->epilog_pc, AC_UD_EPILOG_PC);
}
ac_add_arg(&args->ac, AC_ARG_VGPR, 1, AC_ARG_INT, &args->ac.tcs_patch_id);
@ -697,7 +697,7 @@ declare_shader_args(const struct radv_device *device, const struct radv_graphics
}
if (info->has_epilog) {
add_ud_arg(args, 1, AC_ARG_INT, &args->tcs_epilog_pc, AC_UD_TCS_EPILOG_PC);
add_ud_arg(args, 1, AC_ARG_INT, &args->epilog_pc, AC_UD_EPILOG_PC);
}
ac_add_arg(&args->ac, AC_ARG_SGPR, 1, AC_ARG_INT, &args->ac.tess_offchip_offset);
@ -834,7 +834,7 @@ declare_shader_args(const struct radv_device *device, const struct radv_graphics
declare_global_input_sgprs(info, user_sgpr_info, args);
if (info->has_epilog) {
add_ud_arg(args, 1, AC_ARG_INT, &args->ps_epilog_pc, AC_UD_PS_EPILOG_PC);
add_ud_arg(args, 1, AC_ARG_INT, &args->epilog_pc, AC_UD_EPILOG_PC);
}
if (radv_ps_needs_state_sgpr(info, gfx_state))

5
src/amd/vulkan/radv_shader_args.h
View file

@ -55,7 +55,6 @@ struct radv_shader_args {
struct ac_arg ngg_viewport_translate[2];
/* Fragment shaders */
struct ac_arg ps_epilog_pc;
struct ac_arg ps_state;
struct ac_arg prolog_inputs;
@ -73,7 +72,6 @@ struct radv_shader_args {
* # [12:19] = the LS-HS vertex stride in DWORDS
*/
struct ac_arg tcs_offchip_layout;
struct ac_arg tcs_epilog_pc;
/* TCS epilogs */
struct ac_arg patch_base;
@ -96,6 +94,9 @@ struct radv_shader_args {
/* For non-monolithic VS or TES on GFX9+. */
struct ac_arg next_stage_pc;
/* PS/TCS epilogs PC. */
struct ac_arg epilog_pc;
struct radv_userdata_locations user_sgprs_locs;
unsigned num_user_sgprs;