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nir,aco: add test intrinsics

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These don't really do anything. They're just a source and user of SSA
defs.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28301>
This commit is contained in:
Rhys Perry 2024-03-20 12:30:45 +00:00 • committed by Marge Bot
parent 0a25af1d4e
commit 543ca160a5
4 changed files with 20 additions and 2 deletions
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9
src/amd/compiler/aco_instruction_selection.cpp
View file

@ -9341,6 +9341,15 @@ visit_intrinsic(isel_context* ctx, nir_intrinsic_instr* instr)
break;
}
case nir_intrinsic_cmat_muladd_amd: visit_cmat_muladd(ctx, instr); break;
case nir_intrinsic_unit_test_amd:
bld.pseudo(aco_opcode::p_unit_test, Operand::c32(nir_intrinsic_base(instr)),
get_ssa_temp(ctx, instr->src[0].ssa));
break;
case nir_intrinsic_unit_test_uniform_amd:
case nir_intrinsic_unit_test_divergent_amd:
bld.pseudo(aco_opcode::p_unit_test, Definition(get_ssa_temp(ctx, &instr->def)),
Operand::c32(nir_intrinsic_base(instr)));
break;
default:
isel_err(&instr->instr, "Unimplemented intrinsic instr");
abort();

6
src/amd/compiler/aco_instruction_selection_setup.cpp
View file

@ -461,7 +461,8 @@ init_context(isel_context* ctx, nir_shader* shader)
case nir_intrinsic_load_scalar_arg_amd:
case nir_intrinsic_load_lds_ngg_scratch_base_amd:
case nir_intrinsic_load_lds_ngg_gs_out_vertex_base_amd:
case nir_intrinsic_load_smem_amd: type = RegType::sgpr; break;
case nir_intrinsic_load_smem_amd:
case nir_intrinsic_unit_test_uniform_amd: type = RegType::sgpr; break;
case nir_intrinsic_load_sample_id:
case nir_intrinsic_load_input:
case nir_intrinsic_load_output:
@ -507,7 +508,8 @@ init_context(isel_context* ctx, nir_shader* shader)
case nir_intrinsic_load_vector_arg_amd:
case nir_intrinsic_load_rt_dynamic_callable_stack_base_amd:
case nir_intrinsic_ordered_xfb_counter_add_gfx11_amd:
case nir_intrinsic_cmat_muladd_amd: type = RegType::vgpr; break;
case nir_intrinsic_cmat_muladd_amd:
case nir_intrinsic_unit_test_divergent_amd: type = RegType::vgpr; break;
case nir_intrinsic_load_shared:
case nir_intrinsic_load_shared2_amd:
/* When the result of these loads is only used by cross-lane instructions,

2
src/compiler/nir/nir_divergence_analysis.c
View file

@ -231,6 +231,7 @@ visit_intrinsic(nir_intrinsic_instr *instr, struct divergence_state *state)
case nir_intrinsic_load_barycentric_optimize_amd:
case nir_intrinsic_load_poly_line_smooth_enabled:
case nir_intrinsic_load_rasterization_primitive_amd:
case nir_intrinsic_unit_test_uniform_amd:
case nir_intrinsic_load_global_constant_uniform_block_intel:
case nir_intrinsic_load_debug_log_desc_amd:
case nir_intrinsic_cmat_length:
@ -637,6 +638,7 @@ visit_intrinsic(nir_intrinsic_instr *instr, struct divergence_state *state)
case nir_intrinsic_load_scratch_base_ptr:
case nir_intrinsic_ordered_xfb_counter_add_gfx11_amd:
case nir_intrinsic_xfb_counter_sub_gfx11_amd:
case nir_intrinsic_unit_test_divergent_amd:
case nir_intrinsic_load_stack:
case nir_intrinsic_load_ray_launch_id:
case nir_intrinsic_load_ray_instance_custom_index:

5
src/compiler/nir/nir_intrinsics.py
View file

@ -1457,6 +1457,11 @@ store("tf_r600", [])
intrinsic("optimization_barrier_vgpr_amd", dest_comp=0, src_comp=[0],
flags=[CAN_ELIMINATE])
# These are no-op intrinsics used as a simple source and user of SSA defs for testing.
intrinsic("unit_test_amd", src_comp=[0], indices=[BASE])
intrinsic("unit_test_uniform_amd", dest_comp=0, indices=[BASE])
intrinsic("unit_test_divergent_amd", dest_comp=0, indices=[BASE])
# Untyped buffer load/store instructions of arbitrary length.
# src[] = { descriptor, vector byte offset, scalar byte offset, index offset }
# The index offset is multiplied by the stride in the descriptor.