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Author SHA1 Message Date
Erik Faye-Lund
f4e7204e73 docs: fix bootstrap-extension 
We shouldn't use this extension at all if we're not using the HTML
builder. This should hopefully fix this issue a bit more fundamentally.

This caused issues when using the spelling extension, something I do
locally from time to time.

Fixes: f72033bb70 ("docs: add bootstrap extension")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29888>
 2024-06-26 13:54:13 +00:00
Erik Faye-Lund
18db05d3e6 vulkan/runtime: implementaiton -> implementation 
Acked-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29890>
 2024-06-26 12:31:00 +00:00
Erik Faye-Lund
3967f8cd84 vulkan/runtime: multiesample -> multisample 
Acked-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29890>
 2024-06-26 12:31:00 +00:00
Erik Faye-Lund
788d1b5a67 vulkan/runtime: abreviation -> abbreviation 
Acked-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29890>
 2024-06-26 12:31:00 +00:00
Erik Faye-Lund
947446ade7 vulkan/runtime: initizlie -> initialize 
Acked-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29890>
 2024-06-26 12:31:00 +00:00
Erik Faye-Lund
a966a11161 vulkan/runtime: tne -> the 
This is clearly a typo.

Acked-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29890>
 2024-06-26 12:31:00 +00:00
Karol Herbst
e5bb32da98 rusticl: enable v3d 
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25362>
 2024-06-26 10:04:03 +00:00
Karol Herbst
0b85476d86 v3d: never replace a mapped bo 
The application might have a pointer into the mapped bo.

Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25362>
 2024-06-26 10:04:03 +00:00
Karol Herbst
e5c4ea9323 v3d: fix MAX_GLOBAL_SIZE and MAX_MEM_ALLOC_SIZE 
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25362>
 2024-06-26 10:04:03 +00:00
Karol Herbst
6768c81974 v3d: support variable shared memory 
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25362>
 2024-06-26 10:04:03 +00:00
Karol Herbst
61b1a14e91 v3d: lower 64 bit ALUs 
Even though rusticl won't advertise support for 64 bit ints, some of the
libclc builtins still use 64 bit operations to lower 32 bit ALU ops.

Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25362>
 2024-06-26 10:04:03 +00:00
Karol Herbst
7ff96fb5b0 v3d: lower CL alus 
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25362>
 2024-06-26 10:04:03 +00:00
Karol Herbst
8f72e60c75 v3d: treat SHADER_KERNEL as SHADER_COMPUTE 
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25362>
 2024-06-26 10:04:03 +00:00
Karol Herbst
3889a8e26c v3d: implement gallium APIs for OpenCL support 
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25362>
 2024-06-26 10:04:03 +00:00
Karol Herbst
742984a325 broadcom/compiler: handle variable shared memory 
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25362>
 2024-06-26 10:04:03 +00:00
Karol Herbst
9bf0b3a112 broadcom/compiler: call nir_lower_64bit_phis 
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25362>
 2024-06-26 10:04:03 +00:00
Karol Herbst
4a169a518e broadcom/compiler: implement load_kernel_input 
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25362>
 2024-06-26 10:04:03 +00:00
Karol Herbst
caa3872f76 broadcom/compiler: abort on unknown intrinsics 
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25362>
 2024-06-26 10:04:03 +00:00
Karol Herbst
f8ab9c0e93 broadcom/compiler: handle up to vec16 load_uniforms 
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25362>
 2024-06-26 10:04:03 +00:00
Karol Herbst
e050b13777 broadcom/compiler: try handling 8/16 bit alu operations 
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25362>
 2024-06-26 10:04:02 +00:00
Karol Herbst
c7f9cca985 broadcom/compiler: fix iu2f32 for 8 and 16 bit inputs 
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25362>
 2024-06-26 10:04:02 +00:00
Karol Herbst
214121e9b0 broadcom/compiler: handle fp16 conversion ops 
As long as fp16 isn't advertized it's not doing much, but it also doesn't
hurt to add them.

Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25362>
 2024-06-26 10:04:02 +00:00
Karol Herbst
c2ec65eeda broadcom/compiler: add generated v3d_nir_lower_algebraic 
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25362>
 2024-06-26 10:04:02 +00:00
Karol Herbst
a8f4ff691b rusticl/kernel/launch: fix global work offsets for 32 bit archs again 
Fixes: bb2453c649 ("rusticl/kernel: move most of the code in launch inside the closure")
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25362>
 2024-06-26 10:04:02 +00:00
Karol Herbst
39721a7476 rusticl/mesa/screen: handle get_timestamp not set by driver 
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25362>
 2024-06-26 10:04:02 +00:00
Karol Herbst
bb33dbeeaa rusticl/mesa/context: handle clear_buffer not set by driver 
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25362>
 2024-06-26 10:04:02 +00:00
Karol Herbst
be4f3c2aa8 rusticl/device: require PIPE_CAP_TEXTURE_SAMPLER_INDEPENDENT for image support 
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25362>
 2024-06-26 10:04:02 +00:00
Karol Herbst
0fa4eaf6f6 gallium: add PIPE_CAP_TEXTURE_SAMPLER_INDEPENDENT 
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25362>
 2024-06-26 10:04:02 +00:00
Karol Herbst
d5da434851 nir/opt_sink: add load_kernel_input 
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25362>
 2024-06-26 10:04:02 +00:00
Karol Herbst
535e617ccd nir/lower_alu: support 8 and 16 bit bit_count 
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25362>
 2024-06-26 10:04:02 +00:00
Daniel Schürmann
c4a38c6583 aco/spill: don't remove spilled phis 
They will be removed during register allocation.

Few changes due to different phi order.
Totals from 14 (0.02% of 79395) affected shaders: (GFX11)

Instrs: 315724 -> 315675 (-0.02%); split: -0.02%, +0.01%
CodeSize: 1673608 -> 1673268 (-0.02%); split: -0.03%, +0.00%
Latency: 3194243 -> 3189025 (-0.16%); split: -0.19%, +0.03%
InvThroughput: 638369 -> 637323 (-0.16%); split: -0.19%, +0.03%
VClause: 5716 -> 5714 (-0.03%)
Copies: 37786 -> 37748 (-0.10%); split: -0.13%, +0.03%
Branches: 10469 -> 10454 (-0.14%); split: -0.16%, +0.02%
VALU: 182498 -> 182454 (-0.02%); split: -0.03%, +0.00%
SALU: 36038 -> 36046 (+0.02%); split: -0.01%, +0.04%
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29804>
 2024-06-26 09:42:34 +00:00
Daniel Schürmann
634051f913 aco/live_var_analysis: ignore dead phis 
Since we don't emit code for dead phis, we also don't
have to keep their operands around.

Totals from 44 (0.06% of 79395) affected shaders: (GFX11)

MaxWaves: 648 -> 650 (+0.31%)
Instrs: 449898 -> 449120 (-0.17%); split: -0.18%, +0.00%
CodeSize: 2395000 -> 2389300 (-0.24%); split: -0.24%, +0.00%
VGPRs: 5504 -> 5468 (-0.65%)
Latency: 9005058 -> 9000966 (-0.05%); split: -0.07%, +0.03%
InvThroughput: 2154567 -> 2139095 (-0.72%); split: -0.77%, +0.06%
VClause: 8362 -> 8354 (-0.10%)
SClause: 9135 -> 9134 (-0.01%)
Copies: 60678 -> 60118 (-0.92%); split: -0.93%, +0.01%
Branches: 14379 -> 14385 (+0.04%)
PreSGPRs: 3877 -> 3863 (-0.36%)
PreVGPRs: 6318 -> 6286 (-0.51%)
VALU: 266975 -> 266301 (-0.25%); split: -0.25%, +0.00%
SALU: 52741 -> 52667 (-0.14%); split: -0.15%, +0.01%
VMEM: 16140 -> 16132 (-0.05%)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29804>
 2024-06-26 09:42:34 +00:00
Daniel Schürmann
708e1a73f5 aco/live_var_analysis: slightly refactor handling of additional register demand for Operand copies 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29804>
 2024-06-26 09:42:34 +00:00
Daniel Schürmann
5cfa5b784b aco: remove get_demand_before() 
The register demand before executing an instruction is now included
in the instruction's register demand and this function is unused.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29804>
 2024-06-26 09:42:34 +00:00
Daniel Schürmann
09f1c40f2e aco: track and use the live-in register demand per basic block 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29804>
 2024-06-26 09:42:34 +00:00
Daniel Schürmann
001c8caae0 aco: calculate register demand per instruction as maximum necessary to execute the instruction 
Previously, the register demand per instruction was calculated as the number of
live variables in the register file after executing an instruction plus additional
temporary registers, necessary during the execution of the instruction.
With this change, now it also includes all variables which are live right before
executing an instruction, i.e. killed Operands.

Care has been taken so that the invariant

register_demand[idx] = register_demand[idx - 1] - get_temp_registers(prev_instr)
                        + get_live_changes(instr) + get_temp_registers(instr)

still holds.

Slight changes in scheduling:

Totals from 316 (0.40% of 79395) affected shaders: (GFX11)

Instrs: 301329 -> 300777 (-0.18%); split: -0.31%, +0.12%
CodeSize: 1577976 -> 1576204 (-0.11%); split: -0.21%, +0.10%
SpillSGPRs: 448 -> 447 (-0.22%)
Latency: 1736349 -> 1726182 (-0.59%); split: -2.01%, +1.42%
InvThroughput: 243894 -> 243883 (-0.00%); split: -0.03%, +0.03%
VClause: 6134 -> 6280 (+2.38%); split: -1.04%, +3.42%
SClause: 6142 -> 6137 (-0.08%); split: -0.13%, +0.05%
Copies: 14037 -> 14032 (-0.04%); split: -0.56%, +0.52%
Branches: 3284 -> 3283 (-0.03%)
VALU: 182750 -> 182718 (-0.02%); split: -0.04%, +0.03%
SALU: 18522 -> 18538 (+0.09%)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29804>
 2024-06-26 09:42:33 +00:00
Daniel Schürmann
4c2f231cc0 aco/spill: Unconditionally add 2 SGPRs to live-in demand 
Due to undefined Operands, it might not be enough to check the
predecessors' register demand.

Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29804>
 2024-06-26 09:42:33 +00:00
Daniel Schürmann
26c58ca9de aco/scheduler: fix register_demand validation debug code 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29804>
 2024-06-26 09:42:33 +00:00
Rhys Perry
e3ffc244f5 aco: skip continue_or_break LCSSA phis when not needed 
Fixes:
//exec is empty here
loop {
   %1:s[16-17] = ...
   if () {
      break
   }
   %2:s[16-17] = ...
   continue_or_break
}
%3 = phi %1, undef
//because of the undef, %2 can use s[16-17] and overwrite the address
load(%3:s[16-17])

No fossil-db changes.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Fixes: bbe4652430 ("aco: create lcssa phis for continue_or_break loops when necessary")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/11333
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29838>
 2024-06-26 09:10:54 +00:00
Julian Orth
77759f7683 egl/wayland: ignore unsupported driver configs 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29904>
 2024-06-26 06:56:39 +00:00
Jianxun Zhang
3589035d61 iris: Disable predraw resolve (xe2) 
Fixes piglit test:
arb_texture_barrier-blending-in-shader 32 1 1 64 7 -auto -fbo

src/intel/blorp/blorp_genX_exec.h:910: blorp_emit_ps_config:
Assertion `!"" "Invalid fast clear op"' failed.

Suggested by Kenneth Graunke <kenneth@whitecape.org>

Signed-off-by: Jianxun Zhang <jianxun.zhang@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29906>
 2024-06-26 05:25:44 +00:00
Jianxun Zhang
dc26ad1e86 anv: Update synchronization of fast clear (xe2) 
Signed-off-by: Jianxun Zhang <jianxun.zhang@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29906>
 2024-06-26 05:25:44 +00:00
Jianxun Zhang
930ea030ed isl: Initialize the last usage in isl_encode_aux_mode[] (xe2) 
The ISL_AUX_USAGE_STC_CCS is the last defined usage. We could
get a random value from isl_encode_aux_mode[] once it is passed
as index if its element is not initialized.

Explicit initialization of ISL_AUX_USAGE_HIZ_CCS_WT is added too.

Suggested by Nanley Chery <nanley.g.chery@intel.com>

Signed-off-by: Jianxun Zhang <jianxun.zhang@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29906>
 2024-06-26 05:25:44 +00:00
Jianxun Zhang
9d3ce65628 blorp: Don't convert ccs_e formats for copy (xe2) 
Fix:
dEQP-GLES3.functional.texture.filtering.3d.formats.rgb9_e5_linear

blorp_blit.c:2770: get_ccs_compatible_copy_format:
Assertion `!"" "Not a compressible format"' failed.

Signed-off-by: Jianxun Zhang <jianxun.zhang@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29906>
 2024-06-26 05:25:43 +00:00
Jianxun Zhang
255889a795 isl: Remove restriction of CCS_E support on formats (xe2) 
Signed-off-by: Jianxun Zhang <jianxun.zhang@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29906>
 2024-06-26 05:25:43 +00:00
Jianxun Zhang
31b48fd041 iris: Workaround: Don't allocate compressed bo from cache (xe2) 
There should be some deeper causes to dig out. The bo-caching
system shouldn't affect the compression by design.

Fixes:
dEQP-GLES3.functional.texture.filtering.3d.formats.rgb9_e5_linear
dEQP-GLES3.functional.texture.filtering.3d.formats.rgb9_e5_linear_mipmap_linear

The two cases can pass if we run them respectively. But once they
are fed to glcts in a test case list file (test.list) to run together,
the second test case hangs for a while and eventually fails, regardless
which of them is the second.

./glcts --deqp-caselist-file=test.list

Signed-off-by: Jianxun Zhang <jianxun.zhang@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29906>
 2024-06-26 05:25:43 +00:00
Jianxun Zhang
8a815c83c2 iris: Update synchronization of fast clear (xe2) 
Signed-off-by: Jianxun Zhang <jianxun.zhang@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29906>
 2024-06-26 05:25:43 +00:00
Jianxun Zhang
6073f091bb anv: Disable PAT-based compression on depth images (xe2) 
Signed-off-by: Jianxun Zhang <jianxun.zhang@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29906>
 2024-06-26 05:25:43 +00:00
Jianxun Zhang
b6f9702cf1 iris: Disable PAT-based compression on depth surfaces (xe2) 
Fix: Piglit
PIGLIT_PLATFORM="gbm" piglit/bin/getteximage-depth -auto -fbo

Signed-off-by: Jianxun Zhang <jianxun.zhang@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29906>
 2024-06-26 05:25:43 +00:00
Jianxun Zhang
e835b53a03 anv: Don't enable compression on external bos (xe2) 
Fix:

dEQP-VK.synchronization.cross_instance.suballocated.
write_draw_indexed_read_blit_image.image_128x128_r16
_uint_binary_semaphore_fence_fd

Signed-off-by: Jianxun Zhang <jianxun.zhang@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29906>
 2024-06-26 05:25:43 +00:00