Commit graph

27982 commits

Author SHA1 Message Date
Nicolai Hähnle
374aa2bb27 gallium/u_queue: assert that users must wait on fences before destroying them
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net>
2016-07-11 11:04:44 +02:00
Nicolai Hähnle
a0a616720a gallium/u_queue: guard fence->signalled checks with fence->mutex
I have seen a hang during application shutdown that could be explained by the
following race condition which this patch fixes:

1. Worker thread enters util_queue_fence_signal, sets fence->signalled = true.
2. Main thread calls util_queue_job_wait, which returns immediately.
3. Main thread deletes the job and fence structures, leaving garbage behind.
4. Worker thread calls pipe_condvar_broadcast, which gets stuck forever because
   it is accessing garbage.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net>
2016-07-11 11:03:59 +02:00
Nicolai Hähnle
b479c47a9c radeonsi: fix bad assertion in si_emit_sample_mask
The blitter sets mask == 1, which is fine since it doesn't use smoothing.
Fixes a regression introduced in commit 5bcfbf91.

Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net>
2016-07-09 19:46:54 +02:00
Christian König
64ac4aef27 radeon/uvd: simplify sending context buffer message
Just send it whenever it is allocated.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
2016-07-08 21:03:32 +02:00
Christian König
6b474e06a2 radeon/uvd: fix contex buffer destruction in the error path
Destroying a not allocated buffer is harmless.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
2016-07-08 21:03:32 +02:00
Christian König
36df04dac4 radeon/uvd: move polaris fw check into radeon_video.c v2
It's actually not very clever to claim to support H.264
and then fail to create a decoder.

v2: prefix FW macro with UVD_.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
2016-07-08 21:03:31 +02:00
Christian König
5290bf43c8 radeon/video: fix coding style in radeon_video.c v2
v2: fix other tabs as well.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
2016-07-08 21:03:31 +02:00
Brian Paul
74163475b0 svga: simplify/fix 1D/2D array resource copies
Fixes the one of the piglit arb_copy_image-targets tests for 1D arrays.
Previously, we were applying the 1D array z/face adjustment twice.

Also simplify the copy_region_vgpu10() function.  It never has to copy
multiple array layers/slices.  The Mesa code for glCopyImageSubData does
the loop over slices/faces.

Reviewed-by: Charmaine Lee <charmainel@vmware.com>
2016-07-08 12:53:21 -06:00
Brian Paul
fb26317604 svga: remove unused variable
Reviewed-by: Charmaine Lee <charmainel@vmware.com>
2016-07-08 12:53:21 -06:00
Brian Paul
689293ad52 svga: add dumping for more device commands
Signed-off-by: Brian Paul <brianp@vmware.com>
2016-07-08 12:53:21 -06:00
Brian Paul
599c333d07 svga: silence a couple unused variable warnings
Signed-off-by: Brian Paul <brianp@vmware.com>
2016-07-08 12:53:20 -06:00
Charmaine Lee
c3c7ff014b svga: rebind using render target surfaces in hw draw state
Currently when we rebind framebuffer resources at the beginning of
the command buffer, we use the color buffer surfaces saved in the context
hw clear state. But the surfaces could be different from the actual
emitted render target surfaces if any of the color buffer surfaces
is also used for shader resource, in that case, we create
a backed surface for the collided render target surface. So to rebind
the framebuffer resources correctly, use the render target surfaces saved
in the context hw draw state.

Tested with Heaven, Lightsmark2008, MTT piglit, glretrace, conform.

Reviewed-by: Brian Paul <brianp@vmware.com>
2016-07-08 12:53:20 -06:00
Charmaine Lee
da98cee067 svga: invalidate gb surface before it is reused
With this patch, a guest-backed surface will be invalidated
using the SVGA_3D_CMD_INVALIDATE_GB_SURFACE command before
the surface is reused. This fixes the updating dirty image error
from the device when a surface is reused.

v2: Instead of invalidating the surface when it is reused,
    send the invalidate command before the surface is put into
    the recycle pool.

v3: (1) surface invalidate is a noop operation in Linux winsys, since
        surface invalidation is not needed for DMA path.
    (2) Instead of invalidating the surface content in
        svga_screen_surface_destroy() when a surface is to be destroyed,
        it is done in svga_screen_cache_flush() when the surface is
        no longer referenced in a command buffer and is ready to
        be moved to the unused list. At this point, the surface will
        be moved to the invalidate list. When the surface invalidation
        is submitted, the surface will be moved to the unused list.

Tested with piglit, glretrace.

Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Sinclair Yeh <syeh@vmware.com>
2016-07-08 12:53:20 -06:00
Brian Paul
ca531aeeb1 svga: fix use of provoking vertex control
If the SVGA3D_DEVCAP_DX_PROVOKING_VERTEX query returns false, never
define rasterizer state objects with provokingVertexLast set.  Despite
what the device reports, it may interpret the provokingVertexLast flag
anyway.  This fixes an issue when using capability clamping.

Tested with piglit provoking-vertex and glsl-fs-flat-color tests.

VMware bug 1550143.

Reviewed-by: <charmainel@vmware.com>
2016-07-08 12:53:20 -06:00
Nayan Deshmukh
af18a04755 vl: add half pixel to v_tex before adding offsets
Since pixel center lies at 0.5, add half_pixel to vtex
before adding offsets to it.

Signed-off-by: Nayan Deshmukh <nayan26deshmukh@gmail.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
2016-07-08 20:51:12 +02:00
Samuel Pitoiset
a0bf1768c7 nvc0/ir: remove unused resource info loading helpers
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
2016-07-08 19:12:23 +02:00
Samuel Pitoiset
ed3a284382 nvc0/ir: refactor the surfaces info loading logic
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
2016-07-08 19:12:21 +02:00
Samuel Pitoiset
9cdbe80745 nvc0/ir: move the shift left op inside loadTexHandle()
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
2016-07-08 19:12:06 +02:00
Nicolai Hähnle
04d93ea619 radeonsi: disable multi-threading when shader dumps are enabled
Otherwise, shader dumps can become interleaved and unusable.

Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2016-07-08 10:59:36 +02:00
Nicolai Hähnle
7ffc832ab8 radeonsi: use multi-threaded compilation in debug contexts
We only have to stay single-threaded when debug output must be synchronous.
This yields better parallelism in shader-db runs for me.

Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2016-07-08 10:59:32 +02:00
Nicolai Hähnle
2909e292fc gallium: add async flag to pipe_debug_callback
v2: fix typo db -> cb

Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2016-07-08 10:58:52 +02:00
Nicolai Hähnle
5bcfbf91e5 radeonsi: catch a potential state tracker error with non-MSAA FBs
At least st/mesa ensures this, so I'd rather not handle deviations in radeonsi.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2016-07-08 10:53:05 +02:00
Nicolai Hähnle
d938b8c0bf radeonsi: explicitly choose center locations for 1xAA on Polaris
Unlike SC, the small primitive filter does not automatically use center
locations in 1xAA mode, so this is needed to avoid artifacts caused by
the small primitive filter discarding triangles that it shouldn't.

As a side effect of how the effective number of samples is now calculated,
this patch also avoids submitting the sample locations for line/poly smoothing
when they're not really needed.

Cc: 12.0 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2016-07-08 10:52:50 +02:00
Nicolai Hähnle
7d2ce5258f r600g: call cayman_emit_msaa_sample_locs only when needed
In the case of nr_samples <= 1, that function is (currently) a no-op anyway.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2016-07-08 10:52:45 +02:00
Mathias Fröhlich
13affe0d3f osmesa: Export OSMesaCreateContextAttribs.
Since the function is exported like any other
public api function and put in the header
as if you could link against it, export it also
from shared objects.

Signed-off-by: Mathias Fröhlich <Mathias.Froehlich@web.de>
Reviewed-by: Brian Paul <brianp@vmware.com>
Cc: "11.2 12.0" <mesa-stable@lists.freedesktop.org>
2016-07-07 06:19:13 +02:00
Tom Stellard
513fccdfb6 radeon/llvm: Use alloca instructions for larger arrays
We were storing arrays in vectors, which was leading to some really bad
spill code for large arrays.  allocas instructions are a better fit for
arrays and LLVM optimizations are more geared toward dealing with
allocas instead of vectors.

For arrays that have 16 or less 32-bit elements, we will continue to use
vectors, because this will force LLVM to store them in registers and
use indirect registers, which is usually faster for small arrays.

In the future we should use allocas for all arrays and teach LLVM
how to store allocas in registers.

This fixes the piglit test:

spec/glsl-1.50/execution/geometry/max-input-component

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2016-07-06 19:47:38 +00:00
Tom Stellard
02873a7b0c radeon/llvm: Add helpers for loading and storing data from arrays.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2016-07-06 19:47:38 +00:00
Tom Stellard
2dc48984b2 radeon/llvm: Remove uses_temp_indirect_addressing() function
bld->indirect_files is never set, so this function always returns false.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2016-07-06 19:47:38 +00:00
Rob Clark
09fe35b450 gallium: un-inline pipe_surface_desc
Want to re-use this struct, so un-inline it.

Signed-off-by: Rob Clark <robdclark@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2016-07-06 10:17:30 -04:00
Rob Clark
def044376a gallium/util: make util_copy_framebuffer_state(src=NULL) work
Be more consistent with the other u_inlines util_copy_xyz_state()
helpers and support NULL src.

Signed-off-by: Rob Clark <robclark@freedesktop.org>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2016-07-06 10:17:30 -04:00
Nicolai Hähnle
660cd3de4a winsys/amdgpu: avoid flushed depth when possible
If a depth/stencil texture has no mipmaps, we can always get a layout that is
compatible with DB and TC.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2016-07-06 10:43:52 +02:00
Nicolai Hähnle
7000dfd5c3 gallium/radeon: add depth/stencil_adjusted output to surface computation
This fixes a rare bug with stencil texturing -- seen on Polaris and Tonga,
though it's basically a function of the memory configuration so could affect
other parts as well.

Fixes piglit "unaligned-blit * stencil downsample" and various
"fbo-depth-array *stencil*" tests.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2016-07-06 10:43:52 +02:00
Nicolai Hähnle
68fe270e71 gallium/radeon: allocate only the required plane for flushed depth
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2016-07-06 10:43:52 +02:00
Nicolai Hähnle
1a0a8efcce radeonsi: decompress to flushed depth texture when required
v2: s/dirty_level_mask/stencil_dirty_level_mask/ in stencil case

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2016-07-06 10:43:51 +02:00
Nicolai Hähnle
4b7961da77 radeonsi: extract DB->CB copy logic into its own function
Also clean up some of the looping.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2016-07-06 10:43:51 +02:00
Nicolai Hähnle
18cc825fb9 radeonsi: sample from flushed depth texture when required
Note that this has no effect yet. A case where can_sample_z/s can be false
in radeonsi will be added in a later patch.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2016-07-06 10:43:51 +02:00
Nicolai Hähnle
f2eb34f82f gallium/radeon: replace is_flushing_texture with db_compatible
This is a left-over of when I considered generalizing the separate stencil
support. I do prefer the new name since it emphasizes what flushing vs.
non-flushing means from a functional point-of-view, namely special handling
of the texture format.

v2: adjust r600_init_color_surface as well

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2016-07-06 10:43:48 +02:00
Nicolai Hähnle
dd65126153 gallium/radeon: add can_sample_z/s flags for textures
v2: adjust r600_init_color_surface as well

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2016-07-06 10:43:43 +02:00
Nicolai Hähnle
065eeb79f7 radeonsi: correctly mark levels of 3D textures as fully decompressed
Account for the fact that max_layer is minified for higher levels.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2016-07-06 10:42:49 +02:00
Nicolai Hähnle
19f8d2a843 gallium/radeon/winsyses: remove unused stencil_offset
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2016-07-06 10:42:49 +02:00
Nicolai Hähnle
3a1da559c5 gallium/radeon: remove redundant null-pointer check
v2: keep using r600_texture_reference

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2016-07-06 10:42:48 +02:00
Nicolai Hähnle
5b87eef031 gallium/radeon: print StencilLayout only once
It is the same for all levels.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2016-07-06 10:42:48 +02:00
Nicolai Hähnle
bae066c3f0 gallium/radeon: flush stdout after printing texture information
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2016-07-06 10:42:48 +02:00
Charmaine Lee
32651c67d1 svga: avoid emitting redundant DXSetRenderTargets command
Tested with Lightsmark2008, MTT piglit, glretrace, conform.

Reviewed-by: Sinclair Yeh <syeh@vmware.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
2016-07-05 16:58:29 -06:00
Leo Liu
aa7d42a5f9 radeon/vce: update encRefPic addr and array mode to tiled
Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
2016-07-05 09:15:50 -04:00
Leo Liu
e560a11b87 radeon/vce: increase cpb height alignment
Height should be aligned with 2 macroblocks, thus making safer
for tiled mode

Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
2016-07-05 09:15:47 -04:00
Emil Velikov
744d0d8f3b swr: automake: don't ship LLVM version specific generated sources
Otherwise things will fail to build, if the builder is using another
version of LLVM.

v2: annotate all the dependencies of builder_gen.h
v3: clean the generated files as needed
v4: comment cleanups (Tim)

Cc: "12.0" <mesa-stable@lists.freedesktop.org>
Tested-by: Tim Rowley <timothy.o.rowley@intel.com>
Tested-by: Chuck Atkins <chuck.atkins@kitware.com> (v2)
Reported-by: Chuck Atkins <chuck.atkins@kitware.com>
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
2016-07-05 12:17:05 +01:00
Emil Velikov
f98530b739 clover: conditionally use MESA_GIT_SHA1
Considering how hard/annoying it was for many peoples' workflow to
properly generate the macro, it will be demoted to conditionally
available with follow-up commits.

v2: Kill off gracious blank line (Vedran).

Cc: mesa-stable@lists.freedesktop.org
Cc: Vedran Miletić <vedran@miletic.net>
Cc: Francisco Jerez <currojerez@riseup.net>
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com> (v1)
Reviewed-by: Vedran Miletić <vedran@miletic.net>
2016-07-05 12:14:34 +01:00
Samuel Pitoiset
c1fb3290a6 nvc0/ir: rename NVE4_SU_INFO_XXX to NVC0_SU_INFO_XXX
While we are at it, fix a typo inside the comment which describes
what those constants are for.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
2016-07-05 01:44:15 +02:00
Samuel Pitoiset
f3b9fff3c3 nvc0/ir: reset the base offset for indirect images accesses
In presence of an indirect image access, the base offset should be
zeroed because the stride will be computed twice. This is a pretty
rare situation but it can happen when tex.r > 0.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: "11.2 12.0" <mesa-stable@lists.freedesktop.org>
2016-07-05 01:44:12 +02:00