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gallium/radeon: add depth/stencil_adjusted output to surface computation

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This fixes a rare bug with stencil texturing -- seen on Polaris and Tonga,
though it's basically a function of the memory configuration so could affect
other parts as well.

Fixes piglit "unaligned-blit * stencil downsample" and various
"fbo-depth-array *stencil*" tests.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
This commit is contained in:
Nicolai Hähnle 2016-06-30 20:04:54 +02:00
parent 68fe270e71
commit 7000dfd5c3
3 changed files with 14 additions and 2 deletions
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4
src/gallium/drivers/radeon/r600_texture.c
View file

@ -1030,8 +1030,8 @@ r600_texture_create_object(struct pipe_screen *screen,
if (base->flags & (R600_RESOURCE_FLAG_TRANSFER |
R600_RESOURCE_FLAG_FLUSHED_DEPTH) ||
rscreen->chip_class >= EVERGREEN) {
rtex->can_sample_z = true;
rtex->can_sample_s = true;
rtex->can_sample_z = !rtex->surface.depth_adjusted;
rtex->can_sample_s = !rtex->surface.stencil_adjusted;
} else {
if (rtex->resource.b.b.nr_samples <= 1 &&
(rtex->resource.b.b.format == PIPE_FORMAT_Z16_UNORM ||

8
src/gallium/drivers/radeon/radeon_winsys.h
View file

@ -401,6 +401,14 @@ struct radeon_surf {
uint32_t macro_tile_index;
uint32_t micro_tile_mode; /* displayable, thin, depth, rotated */
/* Whether the depth miptree or stencil miptree as used by the DB are
* adjusted from their TC compatible form to ensure depth/stencil
* compatibility. If either is true, the corresponding plane cannot be
* sampled from.
*/
bool depth_adjusted;
bool stencil_adjusted;
uint64_t dcc_size;
uint64_t dcc_alignment;
};

4
src/gallium/winsys/amdgpu/drm/amdgpu_surface.c
View file

@ -454,6 +454,10 @@ static int amdgpu_surface_init(struct radeon_winsys *rws,
if (r)
return r;
/* DB uses the depth pitch for both stencil and depth. */
if (surf->stencil_level[level].nblk_x != surf->level[level].nblk_x)
surf->stencil_adjusted = true;
if (level == 0) {
/* For 2D modes only. */
if (AddrSurfInfoOut.tileMode >= ADDR_TM_2D_TILED_THIN1) {