Commit graph

26018 commits

Author SHA1 Message Date
Brian Paul
f0339f502c mesa: replace assertion with no-op function assignment 2009-09-24 12:37:34 -06:00
Brian Paul
964792b025 mesa: added comment 2009-09-24 12:37:06 -06:00
Brian Paul
1a81611725 vbo: limit number of warnings to 10
Otherwise some apps will emit tons of warnings.
2009-09-24 12:36:05 -06:00
Pauli Nieminen
1d2dca194c radeon: Fix scissors for r600 KMS.
Radeon generic scissors code had problem that some of code was using exclusive
and some inclusive bottom right corner. Only r600 driver is using exclusive
coordinate so changed generic code to pass inclusive coordinate and r600 driver
changes BR coordinate to be exclusive.
2009-09-24 20:37:55 +03:00
Brian Paul
7549a8397b Merge branch 'mesa_7_5_branch' into mesa_7_6_branch 2009-09-24 10:52:15 -06:00
Brian Paul
a64d4516a0 tgsi/sse: Pass the lodbias, not zero. More comments.
This fixes the glean/glsl1 "texture2D(), with bias" test when using SSE.
2009-09-24 10:28:09 -06:00
Brian Paul
a491e25b1f mesa: added default case return to silence warning 2009-09-24 10:28:09 -06:00
Brian Paul
00ddd4f9e9 glsl: init var to silence warning 2009-09-24 10:28:09 -06:00
Brian Paul
e44c084be5 glsl: fix missing initializers warning 2009-09-24 10:28:09 -06:00
Andre Maasikas
2058dfaa47 r600: add support for CUBE textures, also TXP
seems to work here ...
2009-09-24 10:03:37 -04:00
Alex Deucher
639fb1472d r600: fix typo in the last commit
128 gprs, 256 reg-based consts
2009-09-24 10:03:22 -04:00
Alex Deucher
28308c9260 r600: various cleanups
- max texture size is 8k, but mesa doesn't support
that at the moment.
- attempt to set shader limits to what the hw actually
supports
- clean up some old r300 cruft
- no need to explicitly disable irqs.  This is fixed
in the drm now.

Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
2009-09-24 10:03:08 -04:00
Andre Maasikas
ed91d10347 r600: fix some issues with LIT instruction
- MUL_LIT is ALU.Trans instruction
- some Trans instructions can take 3 arguments
- don't clobber dst.x, use dst.z as temp, it'll get written correct
  value in last insn
- respect source swizzles
2009-09-24 10:02:37 -04:00
Alex Deucher
48559c7605 r600: fix point sizes
registers takes radius
2009-09-24 10:02:22 -04:00
Alex Deucher
095db818c6 r600: fix polygon offset 2009-09-24 10:02:08 -04:00
Alex Deucher
ec14d59afa radeon: don't build non-r600 span code on r600 2009-09-24 10:01:56 -04:00
Alex Deucher
dbec27be85 r600: minor span cleanups 2009-09-24 10:01:41 -04:00
Andre Maasikas
2cd2dc34ac r600: support position_invariant programs 2009-09-24 10:00:58 -04:00
Alex Deucher
9437ac9bcc r600: add span support for 1D tiles
1D tile span support for depth/stencil/color/textures

Z and stencil buffers are always tiled, so this fixes
sw access to Z and stencil buffers.  color and textures
are currently linear, but this adds span support when we
implement 1D tiling.

This fixes the text in progs/demos/engine and progs/tests/z*
2009-09-24 09:59:45 -04:00
Alex Deucher
93a7ea6ba0 r600: fix warning
Noticed by rnoland on IRC.
2009-09-24 09:59:32 -04:00
Andre Maasikas
7f5a958c80 r600: fix texcoords from constants
with some minor updates from Richard.
2009-09-24 09:59:15 -04:00
Andre Maasikas
9edd1a441c r600: enable caching of vertex programs 2009-09-24 09:59:00 -04:00
Alex Deucher
6552a103f9 r600: check if textures are actually enabled before submission
noticed by taiu on IRC.
2009-09-24 09:58:36 -04:00
Alex Deucher
65b01d449c r600: fix ftp for dri1
We use t->bo for dri1 since r600 uses CS for dri1.
2009-09-24 09:58:17 -04:00
Dave Airlie
b1e417413f r600: don't setup hardware state if TFP
if we have a BO here it means TFP and we should have set it
up already.

tested by b0le on #radeon
2009-09-24 09:57:45 -04:00
Alex Deucher
cbab3d7f2a r600: fix dri2 clipping 2009-09-24 09:56:18 -04:00
Maciej Cencora
84c7afd9e0 r300: fallback to software rendering if we are out of free texcoords
Fixes #22741
2009-09-23 23:22:33 +02:00
Brian Paul
2acd5de226 swrast: add lod bias when texture sampling
Mostly fixes progs/demos/lodbias when MESA_TEX_PROG=1.  But the LOD still
seems off by -1 or so.
May be an issue with the params passed to _swrast_compute_lambda()
2009-09-23 13:36:44 -06:00
Brian Paul
890f37d4d9 mesa: don't bias LOD in shader interpreter; do it in swrast 2009-09-23 13:36:44 -06:00
Brian Paul
ad935c3f47 swrast: fix typo in partial derivatives parameter passing 2009-09-23 13:36:43 -06:00
Keith Whitwell
be66ff51ec st/mesa: trim calculated userbuffer size
In get_array_bounds we were previously defining a user buffer sized as
(nr_vertices * stride).  The trouble is that if the vertex data
occupies less than stride bytes, the extra tailing (stride - size)
bytes may extend outside the memory actually allocated by the app and
caused a segfault.

To fix this, define a the buffer bounds to be:

   ptr .. ptr + (nr-1)*stride + element_size
2009-09-23 18:55:46 +01:00
Brian Paul
e41707beca softpipe: added max texture/surface size sanity check 2009-09-23 10:50:38 -06:00
Brian Paul
84b956c29b softpipe: increase MAX_WIDTH/HEIGTH 4096 to match max texture size 2009-09-23 10:46:27 -06:00
Brian Paul
926b965ed5 mesa: don't re-use the meta glDrawPixels VBO; create a new one each time
This should help to work around bugs 24083 and 23670.
2009-09-22 15:58:49 -06:00
Brian Paul
f338de4018 mesa: fix more buffer object error messages 2009-09-22 13:47:49 -06:00
Brian Paul
ba002eb196 Merge branch 'mesa_7_5_branch' into mesa_7_6_branch
Conflicts:

	src/mesa/main/bufferobj.c
2009-09-22 13:44:43 -06:00
Brian Paul
bc75464760 glx: include string.h to silence missing memset() prototype warning 2009-09-22 13:19:15 -06:00
Brian Paul
52cadf7592 mesa: fix error message text 2009-09-22 13:19:11 -06:00
Nicolai Hähnle
8cc12ffb34 r300: Fix crash reported in bug #24066
Signed-off-by: Nicolai Hähnle <nhaehnle@gmail.com>
2009-09-22 21:00:01 +02:00
Tormod Volden
e857303305 GLX: Warn only once about applications calling GLX 1.3 functions
The warnings introduced in 1f309c40b8
would pour out generously from some applications. This patch adds a
"warn once" wrapper macro, heavily inspired by
src/mesa/drivers/dri/r600/radeon_debug.h

Signed-off-by: Tormod Volden <debian.tormod@gmail.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
2009-09-21 15:29:52 -07:00
Brian Paul
6559eaef59 Merge branch 'mesa_7_5_branch' into mesa_7_6_branch 2009-09-21 14:49:46 -06:00
Brian Paul
2655d43756 mesa: refine the error checking vbo_exec_DrawRangeElements()
If the 'end' index is out of bounds issue a warning as before.  But instead
of just no-op'ing the draw call, examine the actual array indices to see
if they're OK.  If the max array index is out of bounds, issue another
warning and no-op the draw call.  Otherwise, draw normally.  This is a
debug build-only feature since it could impact performance.

This "fixes" the missing torus in the OGL Distilled / Picking demo.
2009-09-21 14:25:39 -06:00
Brian Paul
44d260329e mesa: make max_buffer_index() a non-static function 2009-09-21 14:25:39 -06:00
Maciej Cencora
ff5535c521 radeon: update buffer map/unmap code for changes introduced in 92033a9516 and 822c796481 2009-09-21 21:13:01 +02:00
Maciej Cencora
db928a5e91 mesa: add some debug info to teximage.c 2009-09-21 21:12:55 +02:00
Maciej Cencora
ab4ec85f6c r300: fix a typo 2009-09-21 21:12:31 +02:00
Eric Anholt
2b83483fb4 intel: Mark the FBO as incomplete if there's no intel_renderbuffer for it.
This happens to rendering with textures with a border, which had resulted
in a segfault on dereferencing the irb.

(cherry-picked from commit 8bba183b9e)
2009-09-21 10:02:38 -06:00
Brian Paul
5a0b29050f softpipe: Fix cube face selection.
If arx and ary are equal, we still want to choose from one of them,
and not arz.

(cherry picked from commit de685b37a9)
2009-09-21 08:36:05 -06:00
Brian Paul
077e3de989 swrast: fix cube face selection
If arx and ary are equal, we still want to choose from one of them,
and not arz.

This is the same as Michal's softpipe fix.
2009-09-21 08:36:05 -06:00
Nicolai Hähnle
526430ade1 r300: Zero-initialize register for NV_vertex_program
Signed-off-by: Nicolai Hähnle <nhaehnle@gmail.com>
2009-09-21 12:56:16 +02:00