Commit graph

97128 commits

Author SHA1 Message Date
Emil Velikov
ef5dbb54f6 cherry-ignore: meson: fix strtof locale support check
Meson is explicitly disabled in branch.

Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
2017-12-18 15:03:17 +00:00
Bas Nieuwenhuizen
67d3591310 radv: Fix multi-layer blits.
We did not set the layer correctly for the dst, as we would keep
using the base layer. Same for the source image.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=102710
CC: <mesa-stable@lists.freedesktop.org>
Reviewed-by: Dave Airlie <airlied@redhat.com>
(cherry picked from commit b42e106d4d)
2017-12-18 14:58:35 +00:00
Marek Olšák
658028572b radeonsi: don't call force_dcc_off for buffers
This was undefined yet harmless behavior in LLVM.
Not anymore - it causes a hang now.

Cc: 17.3 <mesa-stable@lists.freedesktop.org>
Tested-by: Michel Dänzer <michel.daenzer@amd.com>
(cherry picked from commit 35c3cbad3c)
2017-12-18 14:58:23 +00:00
Emil Velikov
455ff75892 util: scons: wire up the sha1 test
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
Reviewed-by: Andres Gomez <agomez@igalia.com>
(cherry picked from commit 5d03a68640)
2017-12-15 19:10:23 +00:00
Matt Turner
60ed1a07f2 util: Add a SHA1 unit test program
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
(cherry picked from commit 513d7ffa23)
2017-12-15 19:10:22 +00:00
Matt Turner
9a49b36368 util: Assume little endian in the absence of platform-specific handling
(cherry picked from commit 6a353479a7)

Squashed with:

util: Use preprocessor correctly

Fixes: 6a353479a7 ("util: Assume little endian in the absence of
                      platform-specific handling")
(cherry picked from commit b8cbad624b)

Squashed with:

util: Just give up and define PIPE_ARCH_LITTLE_ENDIAN on MSVC

MSVC doesn't support #warning?! Getting really tired of this.

(cherry picked from commit 676761252b)

Squashed with:

util: Also include endian.h on cygwin

If u_endian.h can't determine the endianess, the default behaviour in sha1.c
is to build for big-endian

Signed-off-by: Jon Turney <jon.turney@dronecode.org.uk>
Reviewed-by: Matt Turner <mattst88@gmail.com>
(cherry picked from commit 2c62ccb10a)
2017-12-15 19:09:31 +00:00
Eric Anholt
4b4d8dad71 broadcom/vc4: Fix handling of GFXH-515 workaround with a start vertex count.
We failed to take the start into account for how many vertices to draw in
this round, so we would end up decrementing count below 0, which as an
unsigned number meant we would loop until the CLs soon ran out of space.

When I wrote the code I was thinking about how to use the previously
emitted shader state (no index bias baked into the elements) by emitting
up to 65535 and then only re-emitting with bias for the second wround, but
that doesn't work if the start is over 65535.  Instead, just delay
emitting shader state until we get into the drawarrays GFXH-515 loop and
always bake the bias in when we're doing the workaround.

(cherry picked from commit 84ab48c15c)
2017-12-14 22:56:46 +00:00
Fabian Bieler
77148639d3 glsl: Fix gl_NormalScale.
GLSL shaders can access the normal scale factor with the built-in
gl_NormalScale.  Mesa's modelspace lighting optimization uses a different
normal scale factor than defined in the spec.  We have to take care not
to use this factor for gl_NormalScale.

Mesa already defines two seperate states: state.normalScale and
state.internal.normalScale.  The first is used by the glsl compiler
while the later is used by the fixed function T&L pipeline.  Previously
the only difference was some component swizzling.  With this commit
state.normalScale always uses the normal scale factor for eyespace
lighting.

Reviewed-by: Brian Paul <brianp@vmware.com>
(cherry picked from commit c3ee464d7a)
2017-12-14 22:56:46 +00:00
Fabian Bieler
140c735963 glsl: Match order of gl_LightSourceParameters elements.
spotExponent and spotCosCutoff were swapped in the
gl_builtin_uniform_element struct.
Now the order matches across gl_builtin_uniform_element,
glsl_struct_field and the spec.

Reviewed-by: Brian Paul <brianp@vmware.com>
(cherry picked from commit 9bdb5457f4)
2017-12-14 22:56:46 +00:00
Jason Ekstrand
c798b07981 i965: Switch over to fully external-or-not MOCS scheme
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
(cherry picked from commit 4b1e70cc57)
2017-12-14 22:56:46 +00:00
Bas Nieuwenhuizen
829490e5e5 radv: Don't advertise VK_EXT_debug_report.
We never supported it. Missed during copy and pasting.

Fixes: 17201a2eb0 "radv: port to using updated anv entrypoint/extension generator."
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
(cherry picked from commit 4eb0dca46b)
[Emil Velikov: trivial conflicts]
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>

Conflicts:
	src/amd/vulkan/radv_extensions.py
2017-12-14 22:56:46 +00:00
Brian Paul
994ee73949 gallium/aux: include nr_samples in util_resource_size() computation
This function is only used in two places:
1. VMware driver, but only for HUD reporting
2. st/nine state tracker, used for texture memory accounting

Fixes: a69efa9482 ("util: add new util_resource_size() function in
u_resource.[ch]")

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Reviewed-by: Charmaine Lee <charmainel@vmware.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
(cherry picked from commit dde8309cde)
2017-12-14 22:56:46 +00:00
Vadym Shovkoplias
cc91efb8b5 util/disk_cache: Remove unneeded free() on always null string
At this point dc_job->cache_item_metadata.keys always equals
NULL, so call to free() is useless

Fixes: b86ecea344 ("util/disk_cache: write cache item metadata to disk")
Signed-off-by: Vadym Shovkoplias <vadym.shovkoplias@globallogic.com>
Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com>
(cherry picked from commit b2490a326c)
2017-12-14 22:56:46 +00:00
Timothy Arceri
1a79226d85 glsl: get correct member type when processing xfb ifc arrays
This fixes a crash in:

KHR-GL45.enhanced_layouts.xfb_block_stride

Fixes: 0822517936 "glsl: add helper to process xfb qualifiers during linking"
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
(cherry picked from commit 9d53ccccb2)
2017-12-14 22:56:46 +00:00
Nicolai Hähnle
8396774313 radeonsi: fix the R600_RESOURCE_FLAG_UNMAPPABLE check
The flag is on the pipe_resource, not the r600_resource.

I don't see an obvious bug related to this, but it could potentially lead
to suboptimal placement of some resources.

Fixes: a41587433c ("gallium/radeon: add R600_RESOURCE_FLAG_UNMAPPABLE")
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
(cherry picked from commit 5e2962c949)
2017-12-14 22:56:46 +00:00
Pierre Moreau
9d9f6b3633 nvc0/ir: Properly lower 64-bit shifts when the shift value is >32
Fixes: 61d7676df7 "nvc0/ir: add support for 64-bit shift lowering on SM20/SM30"

Fixes fs-shift-scalar-by-scalar.shader_test from piglit for the current
set-up:

uniform int64_t ival -0x7dfcfefbdf6536ff # bit pattern: 0x82030104209ac901
uniform uint64_t uval 0x1400000085010203
uniform int shl 36
uniform int shr 36
uniform int64_t iexpected_shl 0x09ac901000000000
uniform int64_t iexpected_shr -0x7dfcff0 # bit pattern: 0xfffffffff8203010
uniform uint64_t uexpected_shl 0x5010203000000000
uniform uint64_t uexpected_shr 0x0000000001400000
draw rect ortho 12 0 4 4

Signed-off-by: Pierre Moreau <pierre.morrow@free.fr>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
(cherry picked from commit 9bee12160b)
2017-12-14 22:56:46 +00:00
Vadym Shovkoplias
74849cec0f glx/dri3: Remove unused deviceName variable
deviceName string is declared, assigned and freed but actually
never used in dri3_create_screen() function.

Fixes: 2d94601582 ("Add DRI3+Present loader")
Signed-off-by: Vadym Shovkoplias <vadym.shovkoplias@globallogic.com>
Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com>
(cherry picked from commit d555929239)
2017-12-14 22:56:46 +00:00
Eric Engestrom
3fbe230348 compiler: use NDEBUG to guard asserts
nir_validate.c's #endif already had the correct NDEBUG comment

Fixes: dcb1acdea0 "nir/validate: Only build in debug mode"
Fixes: 9ff71b649b "i965/nir: Validate that NIR passes call nir_metadata_preserve()"
Signed-off-by: Eric Engestrom <eric.engestrom@imgtec.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
(cherry picked from commit 7b85b9b877)
[Emil Velikov: trivial conflicts]
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>

Conflicts:
	src/compiler/nir/nir.h
2017-12-14 22:56:46 +00:00
Bruce Cherniak
219d03127d swr: Fix KNOB_MAX_WORKER_THREADS thread creation override.
Environment variable KNOB_MAX_WORKER_THREADS allows the user to override
default thread creation and thread binding.  Previous commit to adjust
linux cpu topology caused setting this KNOB to bind all threads to a single
core.

This patch restores correct functionality of override.

Cc: <mesa-stable@lists.freedesktop.org>

Reviewed-by: Tim Rowley <timothy.o.rowley@intel.com>
(cherry picked from commit 709f5bdc4a)
2017-12-14 22:56:46 +00:00
Brian Paul
8dee6d0063 xlib: call _mesa_warning() instead of fprintf()
We use _mesa_warning() everywhere else in this code.  Change requested
by Rick Irons of Mathworks.

CC: <mesa-stable@lists.freedesktop.org>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
(cherry picked from commit 7a46063803)
2017-12-14 22:56:46 +00:00
Marek Olšák
b0fe64f747 winsys/amdgpu: disable local BOs again due to worse performance
Cc: 17.3 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
(cherry picked from commit bf0904e31f)
2017-12-14 22:56:46 +00:00
Bas Nieuwenhuizen
5878b98dbc spirv: Fix loading an entire block at once.
There is no chain, so  checking the length ends with a SEGFAULT.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=103579
Cc: <mesa-stable@lists.freedesktop.org>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
(cherry picked from commit b926da241a)
[Emil Velikov: trivial conflicts]
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>

Conflicts:
	src/compiler/spirv/vtn_variables.c
2017-12-14 22:56:46 +00:00
Leo Liu
778eaf9887 radeon/vce: move destroy command before feedback command
VCE processing IBs starts from session and task info at first level,
other commands processed subsequently. The task info for destroy is
embedded to destroy command, resulting that feedback command is not
properly procoessed. This is causing kernel spin VM fault messages on
Polaris and Vega10 card when running ends at encode application.

The fix is also verified on VCE physical mode card.

Signed-off-by: Leo Liu <leo.liu@amd.com>
Cc: mesa-stable@lists.freedesktop.org
Acked-by: Christian König <christian.koenig@amd.com>
(cherry picked from commit 6d74cb2570)
2017-12-14 22:56:46 +00:00
Ben Crocker
584791e18a docs/llvmpipe: document ppc64le as alternative architecture to x86.
Power8, Power8NV, and Power9 are supported on an equal footing
with X86.

Cc: "17.2" "17.3" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Ben Crocker <bcrocker@redhat.com>
Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com>

[Eric: changed formatting, reworded a bit (with Ben's ack)]
Signed-off-by: Eric Engestrom <eric.engestrom@imgtec.com>
(cherry picked from commit 060eb314eb)
2017-12-14 22:56:46 +00:00
James Legg
d0cfca9de9 nir/opcodes: Fix constant-folding of bitfield_insert
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=104119
CC: <mesa-stable@lists.freedesktop.org>
CC: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
(cherry picked from commit 947470d10b)
2017-12-14 22:56:46 +00:00
Alex Smith
0c8d5a8c1f radv: Add LLVM version to the device name string
Allows apps to determine the LLVM version so that they can decide
whether or not to enable workarounds for LLVM issues.

Signed-off-by: Alex Smith <asmith@feralinteractive.com>
Cc: "17.2 17.3" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
(cherry picked from commit 8fda98c4f1)
2017-12-14 22:56:46 +00:00
Kenneth Graunke
7254a74ff2 meta: Fix ClearTexture with GL_DEPTH_COMPONENT.
We only handled unpacking for GL_DEPTH_STENCIL formats.

Cemu was hitting _mesa_problem() for an unsupported format in
_mesa_unpack_float_32_uint_24_8_depth_stencil_row(), because the
format was depth-only, rather than depth-stencil.

Cc: "13.0 12.0" <mesa-stable@lists.freedesktop.org>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=94739
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=103966
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
(cherry picked from commit 8705ed13e3)
2017-12-14 22:56:45 +00:00
Kenneth Graunke
73b7caef62 meta: Initialize depth/clear values on declaration.
This helps avoid compiler warningss in the next commit - everything
was initialized, but it wasn't obvious to static analysis.

Suggested-by: Tapani Pälli <tapani.palli@intel.com>
(cherry picked from commit d6d16c0218)
2017-12-14 22:56:45 +00:00
Gert Wollny
9433d8977c r600/sb: do not convert if-blocks that contain indirect array access
If an array is accessed within an if block, then currently it is not known
whether the value in the address register is involved in the evaluation of the
if condition, and converting the if condition may actually result in
out-of-bounds array access. Consequently, if blocks that contain indirect array
access should not be converted.

Fixes piglits on r600/BARTS:
spec/glsl-1.10/execution/variable-indexing/
  vs-output-array-float-index-wr
  vs-output-array-vec3-index-wr
  vs-output-array-vec4-index-wr

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=104143

Signed-off-by: Gert Wollny <gw.fossdev@gmail.com>
Cc: <mesa-stable@lists.freedesktop.org>
Signed-off-by: Dave Airlie <airlied@redhat.com>
(cherry picked from commit 6c268ea79a)
2017-12-14 22:56:45 +00:00
Marek Olšák
d92f520e1f radeonsi: allow DMABUF exports for local buffers
Cc: 17.3 <mesa-stable@lists.freedesktop.org>
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
(cherry picked from commit 010214b403)
[Emil Velikov: s/sscreen/rscreen/]
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>

Conflicts:
	src/gallium/drivers/radeon/r600_texture.c
2017-12-14 22:56:45 +00:00
Marek Olšák
b6fd93f8dc radeonsi: flush the context after resource_copy_region for buffer exports
Cc: 17.2 17.3 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
(cherry picked from commit 5e805cc74b)
2017-12-14 22:56:45 +00:00
Emil Velikov
49a612d158 docs: add sha256 checksums for 17.3.0
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
2017-12-08 13:53:30 +00:00
Emil Velikov
8d55da9f57 docs: Update 17.3.0 release notes
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
2017-12-08 13:47:33 +00:00
Emil Velikov
c4b070d25c Update version to 17.3.0(final)
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
2017-12-08 13:30:44 +00:00
Emil Velikov
30abe7dfae Update version to 17.3.0-rc6
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
2017-12-04 08:53:39 +00:00
Jason Ekstrand
5ac9d91ee3 i965: Disable regular fast-clears (CCS_D) on gen9+
This partially reverts commit 3e57e9494c
which caused a bunch of GPU hangs on several Source titles.  To date, we
have no clue why these hangs are actually happening.  This undoes the
final effect of 3e57e9494c and gets us back to not hanging.  Tested
with Team Fortress 2.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=102435
Fixes: 3e57e9494c
Cc: mesa-stable@lists.freedesktop.org
(cherry picked from commit ee57b15ec7)
2017-12-01 19:02:52 +00:00
Vinson Lee
4eae5b39ee anv: Check if memfd_create is already defined.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=103909
Signed-off-by: Vinson Lee <vlee@freedesktop.org>
Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com>
(cherry picked from commit 8c1e4b1afc)
[Emil Velikov: drop NA hunks]
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>

Conflicts:
	configure.ac
	meson.build
	src/intel/vulkan/anv_allocator.c
2017-12-01 19:02:47 +00:00
Vadym Shovkoplias
4e84aaa906 intel/blorp: Fix possible NULL pointer dereferencing
Fix incomplete check of input params in blorp_surf_convert_to_uncompressed()
which can lead to NULL pointer dereferencing.

Fixes: 5ae8043fed ("intel/blorp: Add an entrypoint for doing
bit-for-bit copies")
Fixes: f395d0abc8 ("intel/blorp: Internally expose
surf_convert_to_uncompressed")
Reviewed-by: Emil Velikov <emli.velikov@collabora.com>
Reviewed-by: Andres Gomez <agomez@igalia.com>

(cherry picked from commit cdb3eb7174)
2017-12-01 17:13:02 +00:00
Kenneth Graunke
bcd4f26b41 i965: Reorganize batch/state BO fields into a 'brw_growing_bo' struct.
We're about to add more of them, and need to pass the whole lot of them
around together when growing them.  Putting them in a struct makes this
much easier.

brw->batch.batch.bo is a bit of a mouthful, but it's nice to have things
labeled 'batch' and 'state' now that we have multiple buffers.

Fixes: 2dfc119f22 "i965: Grow the batch/state buffers if we need space and can't flush."
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=103101
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
(cherry picked from commit 74e38739ca)
[Emil Velikov: remove NA blorp_get_surface_base_address hunk]
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>

Conflicts:
	src/mesa/drivers/dri/i965/genX_blorp_exec.c
2017-12-01 17:12:26 +00:00
Kenneth Graunke
447afbf31b i965: Don't grow batch/state buffer on every emit after an overflow.
Once we reach the intended size of the buffer (BATCH_SZ or STATE_SZ), we
try and flush.  If we're not allowed to flush, we resort to growing the
buffer so that there's space for the data we need to emit.

We accidentally got the threshold wrong.  The first non-wrappable call
beyond (e.g.) STATE_SZ would grow the buffer to floor(1.5 * STATE_SZ),
The next call would see we were beyond STATE_SZ and think we needed to
grow a second time - when the buffer was already large enough.

We still want to flush when we hit STATE_SZ, but for growing, we should
use the actual size of the buffer as the threshold.  This way, we only
grow when actually necessary.

v2: Simplify the control flow (suggested by Jordan)

Fixes: 2dfc119f22 "i965: Grow the batch/state buffers if we need space and can't flush."
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
(cherry picked from commit ca43616586)
2017-12-01 17:09:03 +00:00
Kenneth Graunke
09f6bd5ef2 i965: Preserve EXEC_OBJECT_CAPTURE when growing the BO.
The original state buffer was marked with EXEC_OBJECT_CAPTURE.  When
growing it, we want to preserve that flag so we continue to capture it
in GPU hang reports.

Fixes: 2dfc119f22 "i965: Grow the batch/state buffers if we need space and can't flush."
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
(cherry picked from commit 52d32917e1)
2017-12-01 17:08:55 +00:00
Kenneth Graunke
a49b70d2ec i965: Use old_bo->align when growing batch/state buffer instead of 4096.
The intention here is make the new BO use the same alignment as the old
BO.  This isn't strictly necessary, but we would have to update the
'alignment' field in the validation list when swapping it out, and we
don't bother today.

The batch and state buffers use an alignment of 4096, so this should be
equivalent - it's just clearer than cut and pasting a magic constant.

Fixes: 2dfc119f22 "i965: Grow the batch/state buffers if we need space and can't flush."
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
(cherry picked from commit 2af7085460)
2017-12-01 17:08:50 +00:00
Kenneth Graunke
f1050f0435 i965: Program the dynamic state heap size to MAX_STATE_SIZE.
STATE_BASE_ADDRESS specifies a maximum size of the dynamic state
section, beyond which data supposedly reads back as 0.  On Gen8+,
we were programming it to the size of the buffer.  This worked fine
until we started growing the state buffer in commit 2dfc119f22.
When the state buffer grows, the value in STATE_BASE_ADDRESS becomes
too small, and our state beyond STATE_SZ bytes would read back as 0.

To avoid having to update the value, we program it to MAX_STATE_SIZE.
We used to program the upper bound to the maximum on older hardware
anyway, so programming it too large isn't a big deal.

Bogus SURFACE_STATE can easily lead to GPU hangs and misrendering.
DiRT Rally was hitting the statebuffer growth path, and suffered from
bad texture corruption and GPU hangs (usually around the same time).

This patch fixes both issues.

Fixes: 2dfc119f22 "i965: Grow the batch/state buffers if we need space and can't flush."
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=103101
Tested-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
(cherry picked from commit cfc5af588c)
2017-12-01 17:08:03 +00:00
Marek Olšák
14e528b2db radeonsi/gfx9: fix importing shared textures with DCC
VI has 11 dwords at least. GFX9 has 10 dwords.

Cc: 17.2 17.3 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
(cherry picked from commit ed4780383c)
[Emil Velikov: s|radeon/r600_texture.c|radeonsi/si_state.c|]
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>

Conflicts:
	src/gallium/drivers/radeon/r600_texture.c
2017-12-01 17:07:20 +00:00
Frank Richter
c846d72523 gallium/wgl: fix default pixel format issue
When creating a context without SetPixelFormat() don't blindly take the
pixel format reported by GDI. Instead, look for our own closest pixel
format.

Minor clean-ups added by Brian Paul.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=103412
Reviewed-by: Brian Paul <brianp@vmware.com>
Tested-by: Brian Paul <brianp@vmware.com>
(cherry picked from commit bf41b2b262)
2017-11-29 19:46:17 +00:00
Roland Scheidegger
56993f4b8a r600: set DX10_CLAMP for compute shader too
I really intended to set this for all shader stages by
3835009796 but missed it for compute shaders
(because it's in a different source file...).

Reviewed-by: Dave Airlie <airlied@redhat.com>
(cherry picked from commit 71e630753e)
2017-11-29 19:45:15 +00:00
Roland Scheidegger
9b2c27a39e r600: use DX10_CLAMP bit in shader setup
The docs are not very concise in what this really does, however both
Alex Deucher and Nicolai Hähnle suggested this only really affects instructions
using the CLAMP output modifier, and I've confirmed that with the newly
changed piglit isinf_and_isnan test.
So, with this bit set, if an instruction has the CLAMP modifier bit (which
clamps to [0,1]) set, then NaNs will be converted to zero, otherwise the result
will be NaN.
D3D10 would require this, glsl doesn't have modifiers (with mesa
clamp(x,0,1) would get converted to such a modifier) coupled with a
whatever-floats-your-boat specified NaN behavior, but the clamp behavior
should probably always be used (this also matches what a decomposition into
min(1.0, max(x, 0.0)) would do, if min/max also adhere to the ieee spec of
picking the non-nan result).
Some apps may in fact rely on this, as this prevents misrenderings in
This War of Mine since using ieee muls
(ce7a045fee), without having to use clamped
rcp opcode, which would also fix this bug there.
radeonsi also seems to set this bit nowadays if I see that righ (albeit the
llvm amdgpu code comment now says "Make clamp modifier on NaN input returns 0"
instead of "Do not clamp NAN to 0" since it was changed, which also looks
a bit misleading).

v2: set it in all shader stages.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=103544

Reviewed-by: Dave Airlie <airlied@redhat.com>
(cherry picked from commit 3835009796)
2017-11-29 19:45:12 +00:00
Roland Scheidegger
6954eb1a2a r600: use min_dx10/max_dx10 instead of min/max
I believe this is the safe thing to do, especially ever since the driver
actually generates NaNs for muls too.
The ISA docs are not very helpful here, however the dx10 versions will pick
a non-nan result over a NaN one (this is also the ieee754 behavior), whereas
the non-dx10 ones will pick the NaN (verified by newly changed piglit
isinf-and-isnan test).
Other "modern" drivers will most likely do the same.
This was shown to make some difference for bug 103544, albeit it is not
required to fix it.

Reviewed-by: Dave Airlie <airlied@redhat.com>
(cherry picked from commit aab0bfc648)
2017-11-29 19:44:58 +00:00
Nicolai Hähnle
b79e15b086 glsl: fix interpolateAtXxx(some_vec[idx], ...) with dynamic idx
The dynamic index of a vector (not array!) is lowered to a sequence of
conditional assignments. However, the interpolate_at_* expressions
require that the interpolant is an l-value of a shader input.

So instead of doing conditional assignments of parts of the shader input
and then interpolating that (which is nonsensical), we interpolate the
entire shader input and then do conditional assignments of the interpolated
result.

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
(cherry picked from commit ca63a5ed3e)
2017-11-29 19:42:26 +00:00
Nicolai Hähnle
77cba992c3 glsl: allow any l-value of an input variable as interpolant in interpolateAt*
The intended rule has been clarified in GLSL 4.60, Section 8.13.2
(Interpolation Functions):

   "For all of the interpolation functions, interpolant must be an l-value
    from an in declaration; this can include a variable, a block or
    structure member, an array element, or some combination of these.
    Component selection operators (e.g., .xy) may be used when specifying
    interpolant."

For members of interface blocks, var->data.must_be_shader_input must be
determined on-the-fly after lowering interface blocks, since we don't want
to disable varying packing for an entire block just because one input in it
is used in interpolateAt*.

v2: keep setting must_be_shader_input in ast_function (Ian)
v3: follow the relaxed rule of GLSL 4.60
v4: only apply the relaxed rules to desktop GL
    (the ES WG decided that the relaxed rules may apply in a future version
     but not retroactively; see also
     dEQP-GLES31.functional.shaders.multisample_interpolation.interpolate_at_centroid.negative.*)

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=101378
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com> (v1)
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
(cherry picked from commit 4f42450b86)
2017-11-29 19:42:24 +00:00