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nvc0/ir: Properly lower 64-bit shifts when the shift value is >32

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Fixes: 61d7676df7 "nvc0/ir: add support for 64-bit shift lowering on SM20/SM30"

Fixes fs-shift-scalar-by-scalar.shader_test from piglit for the current
set-up:

uniform int64_t ival -0x7dfcfefbdf6536ff # bit pattern: 0x82030104209ac901
uniform uint64_t uval 0x1400000085010203
uniform int shl 36
uniform int shr 36
uniform int64_t iexpected_shl 0x09ac901000000000
uniform int64_t iexpected_shr -0x7dfcff0 # bit pattern: 0xfffffffff8203010
uniform uint64_t uexpected_shl 0x5010203000000000
uniform uint64_t uexpected_shr 0x0000000001400000
draw rect ortho 12 0 4 4

Signed-off-by: Pierre Moreau <pierre.morrow@free.fr>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
This commit is contained in:
Pierre Moreau 2017-12-03 21:28:57 +01:00 • committed by Ilia Mirkin
parent 9bdb5457f4
commit 9bee12160b
1 changed files with 1 additions and 1 deletions
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2
src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp
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@ -216,7 +216,7 @@ NVC0LegalizeSSA::handleShift(Instruction *lo)
// Compute LO (all shift values)
bld.mkOp2(op, type, (dst[0] = bld.getSSA()), src[0], shift);
// Compute HI (shift > 32)
bld.mkOp2(op, type, (hi2 = bld.getSSA()), src[1],
bld.mkOp2(op, type, (hi2 = bld.getSSA()), src[0],
bld.mkOp1v(OP_NEG, TYPE_S32, bld.getSSA(), x32_minus_shift))
->setPredicate(CC_NOT_P, pred);
bld.mkOp2(OP_UNION, TYPE_U32, (dst[1] = bld.getSSA()), hi1, hi2);