Commit graph

160227 commits

Author SHA1 Message Date
Jason Ekstrand
ea185aef03 iris: Handle resource offsets in buffer copies
Fixes: c5b22441f1 ("iris: Fix buffer -> buffer copy_region")
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15811>
2022-09-22 03:33:00 +00:00
Jason Ekstrand
f4c05f319e iris: Fix more BO alignments
Fixes: 32c5d6d1dc ("iris: Add an alignment parameter to iris_bo_alloc()")
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15811>
2022-09-22 03:33:00 +00:00
Jason Ekstrand
2984134395 iris: Use a larger alignment for buffer allocations
This is likely required for OpenGL buffer texture allocations.  It'll
also make buffer copies faster if things are generally nicely aligned.
It's definitely required for OpenCL.

Fixes: 32c5d6d1dc ("iris: Add an alignment parameter to iris_bo_alloc()")
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15811>
2022-09-22 03:33:00 +00:00
Alyssa Rosenzweig
c17fcbaa2f agx: Account for mask when writing registers
To use fewer registers.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18687>
2022-09-22 03:23:36 +00:00
Alyssa Rosenzweig
5cd2371318 agx: Pass mask into ld/st_tile instructions
Properly handle render target formats with <4 components.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18687>
2022-09-22 03:23:36 +00:00
Alyssa Rosenzweig
640fd089a2 agx: Ensure that the optimizer sees legitimate SSA
Expecting it to keep around unused definitions around is wishful. Add an
"anchoring" unit_test instruction to consume the results so they don't
have to be precoloured registers.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18687>
2022-09-22 03:23:36 +00:00
Alyssa Rosenzweig
52467c2d1e agx: Test fsat+f2f16 together
Something I hit when mucking with this pass.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18687>
2022-09-22 03:23:36 +00:00
Alyssa Rosenzweig
3e86522cf2 agx: Validate immediates
In particular the new sizing rules.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18687>
2022-09-22 03:23:36 +00:00
Alyssa Rosenzweig
14f2be1f33 agx: Use 16-bit immediates
This is slightly more accurate in the IR, and means we instruction
select the current 16-bit size floating point instructions when all
non-immediate operands are 16-bit.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18687>
2022-09-22 03:23:36 +00:00
Alyssa Rosenzweig
e302e5d527 agx: Emit fewer combines for intrinsics
A bunch of the emitted combines were unnecessary, or unnecessarily
large. Fix the accounting now that combines are variable size.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18687>
2022-09-22 03:23:36 +00:00
Alyssa Rosenzweig
e887a11b06 agx: Fix bfi_mask packing
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18687>
2022-09-22 03:23:36 +00:00
José Roberto de Souza
89d2cdad37 intel/dev: Adjust prefetch_size values for MTL engines
MTL has different CS prefetch sizes for each CS type.
So here replacing the cs_prefetch_size in intel_device_info struct
by a function that takes as argument the i915 engine class.

Fixes:
- func.cmd-buffer.small-secondaries.q0
- dEQP-VK.multiview.secondary_cmd_buffer.*
- Several other VK CTS tests that uses secondary_cmd_buffer

v2:
- renamed to intel_device_info_get_engine_prefetch() (Jordan)

v3:
- renamed to intel_device_info_calc_engine_prefetch()
- store each engine class prefetch in intel_device_info

BSpec: 45718
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18597>
2022-09-22 02:14:47 +00:00
Simon Zeni
029522f67d mesa/st: check egl image and texture target match before binding
Signed-off-by: Simon Zeni <simon@bl4ckb0ne.ca>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18673>
2022-09-22 01:44:32 +00:00
Simon Zeni
6a3f5c6512 mesa: simplify st_egl_image binding process for texture storage
The dmabuf imported edge case is now properly handled.

Signed-off-by: Simon Zeni <simon@bl4ckb0ne.ca>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18673>
2022-09-22 01:44:32 +00:00
Simon Zeni
25f569f58a gallium: track if st_egl_image was created by a dmabuf
This is required by GL_EXT_EGL_image_storage to verify if the image is valid

Signed-off-by: Simon Zeni <simon@bl4ckb0ne.ca>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18673>
2022-09-22 01:44:32 +00:00
Simon Zeni
70e2a1faad mesa: fix EXT_EGL_image_storage target validation
EXT_EGL_image_storage requires OpenGL 4.2, OpenGL ES 3.0, or
ARB_texture_storage, and EXT_direct_state_access or equivalent for
`EGLImageTargetTextureStorageEXT`.

`target` can be one of GL_TEXTURE_2D, GL_TEXTURE_2D_ARRAY, GL_TEXTURE_3D,
GL_TEXTURE_CUBE_MAP, GL_TEXTURE_CUBE_MAP_ARRAY. On non-ES GL it can also be
GL_TEXTURE_1D or GL_TEXTURE_1D_ARRAY. If OES_EGL_image_external is supported,
it can also be GL_TEXTURE_EXTERNAL_OES.

Signed-off-by: Simon Zeni <simon@bl4ckb0ne.ca>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18673>
2022-09-22 01:44:32 +00:00
Mike Blumenkrantz
5b1137043c zink: don't always set VK_DYNAMIC_STATE_VERTEX_INPUT_BINDING_STRIDE_EXT with gpl
this is illegal

Fixes: 86e4fcd9a9 ("zink: add a graphics pipeline library implementation")

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18729>
2022-09-22 01:12:01 +00:00
Mike Blumenkrantz
5c6d61635d zink: don't call CmdBindVertexBuffers2EXT with no attributes
cc: mesa-stable

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18729>
2022-09-22 01:12:01 +00:00
Sil Vilerino
a70bac6252 d3d12: Make get_feedback return correctly on error when writing *size=0
Reviewed-by: Giancarlo Devich <gdevich@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18715>
2022-09-21 23:31:15 +00:00
Sil Vilerino
ef8bd5ca9e d3d12: Extract into common variable for metadata slot calculation
Removes duplicated code using X modulo D3D12_VIDEO_ENC_METADATA_BUFFERS_COUNT

Reviewed-by: Giancarlo Devich <gdevich@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18715>
2022-09-21 23:31:15 +00:00
Sil Vilerino
4e3d93212a d3d12: Enhance get_feedback not enough buffers message
Indicate to increase if the env var D3D12_VIDEO_ENC_METADATA_BUFFERS_COUNT
if not enough buffers in the get_feedback function

Reviewed-by: Giancarlo Devich <gdevich@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18715>
2022-09-21 23:31:15 +00:00
Sil Vilerino
e8474bca5a d3d12: Fix redundant/inconsistent initializations for d3d12_video_encoder
Reviewed-by: Giancarlo Devich <gdevich@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18715>
2022-09-21 23:31:15 +00:00
Sil Vilerino
5b5b5a7ed8 d3d12: Add output buffer to inflight resourceset
Reviewed-by: Giancarlo Devich <gdevich@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18715>
2022-09-21 23:31:15 +00:00
Sil Vilerino
ec16c95e75 d3d12: Make d3d12 encode operations async and do not block waiting
Separate d3d12_video_encode flush on end_frame (ie. vaEndPicture) from fence sync in get_feedback (ie. vaSyncSurface/Buffer)

Reviewed-by: Giancarlo Devich <gdevich@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18715>
2022-09-21 23:31:15 +00:00
Sil Vilerino
5269d660af d3d12: Have d3d12_video_encoder keep separate references for enc, heap and dpb allocations for in flight resources
Reviewed-by: Giancarlo Devich <gdevich@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18715>
2022-09-21 23:31:15 +00:00
Sil Vilerino
24433f3a29 d3d12: d3d12_video_encoder add reset() to prevent leaks on re-allocation
Reviewed-by: Giancarlo Devich <gdevich@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18715>
2022-09-21 23:31:15 +00:00
Sil Vilerino
8e50d5cc0d d3d12: Encoder to use independent command allocators per in flight resource set
Reviewed-by: Giancarlo Devich <gdevich@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18715>
2022-09-21 23:31:15 +00:00
Sil Vilerino
f9b850cd55 d3d12: Move encode configuration and capabilities into separate structs
Reviewed-by: Giancarlo Devich <gdevich@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18715>
2022-09-21 23:31:15 +00:00
Sil Vilerino
29f2c5afbf d3d12: Change d3d12_video_encoder to not automatically flush
With PIPE_VIDEO_CAP_REQUIRES_FLUSH_ON_END_FRAME reported as 1, the frontend will call flush()

Reviewed-by: Giancarlo Devich <gdevich@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18715>
2022-09-21 23:31:15 +00:00
Sil Vilerino
59f2c71773 d3d12: Keep track of feedbacks from previous encode executions
Keep track of previous executed encodes with their metadata as vaSyncSurface
which queries this can be called with latency of several frames.
Fixes gstreamer encoding tearing issues

Reviewed-by: Giancarlo Devich <gdevich@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18715>
2022-09-21 23:31:15 +00:00
Sil Vilerino
45e9e2693d d3d12: Export some util functions from d3d12_fence for d3d12 video
Reviewed-by: Giancarlo Devich <gdevich@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18715>
2022-09-21 23:31:15 +00:00
Sil Vilerino
ed329865ba d3d12: Change type of m_FenceValue to uint64_t in d3d12_video_encoder
Reviewed-by: Giancarlo Devich <gdevich@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18715>
2022-09-21 23:31:15 +00:00
Sil Vilerino
9fb3b2ab12 d3d12: Add support for PIPE_VIDEO_CAP_ENC_SUPPORTS_ASYNC_OPERATION
Add support for PIPE_VIDEO_CAP_ENC_SUPPORTS_ASYNC_OPERATION based on D3D12_VIDEO_ENC_ASYNC env variable defaulted to true

Reviewed-by: Giancarlo Devich <gdevich@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18715>
2022-09-21 23:31:15 +00:00
Sil Vilerino
fe2b28192f d3d12: Report PIPE_VIDEO_CAP_REQUIRES_FLUSH_ON_END_FRAME
Reviewed-by: Giancarlo Devich <gdevich@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18715>
2022-09-21 23:31:15 +00:00
Sil Vilerino
a92cfd5c88 d3d12: Add initialization values for d3d12_video_encoder
Reviewed-by: Giancarlo Devich <gdevich@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18715>
2022-09-21 23:31:15 +00:00
Sil Vilerino
020c0af732 d3d12: Video process - Remove unnecessary batches flush
Make resident and sync in flush() method instead of before to avoid extra batch flushes

Reviewed-by: Giancarlo Devich <gdevich@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18715>
2022-09-21 23:31:15 +00:00
Sil Vilerino
b47b9d96fd d3d12: Update HEVC Encode GOP on I frames too
Update GOP also on I HEVC frames in d3d12_video_encoder_update_hevc_gop_configuration

Reviewed-by: Giancarlo Devich <gdevich@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18715>
2022-09-21 23:31:15 +00:00
Sil Vilerino
229c6f79a6 frontends/va: Implement vaSyncBuffer
Reviewed-by: Ruijing Dong <ruijing.dong@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18715>
2022-09-21 23:31:15 +00:00
Georg Lehmann
84c0529258 aco: Unswizzle v_pk_fma_f16 literals to produce more v_pk_fmac_f16.
No Foz-DB difference, but it reduces code size in some angle shaders.

Signed-off-by: Georg Lehmann <dadschoorse@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18676>
2022-09-21 23:04:06 +00:00
Jonathan Gray
ed5d16cec1 iris: check i915 features after hw gen
when running recent Mesa on i855 (gen 2) without amber drivers:
  error: Kernel is too old for Iris. Consider upgrading to kernel v4.16.

  libGL error: glx: failed to create dri3 screen
  libGL error: failed to load driver: iris
  error: Kernel is too old for Iris. Consider upgrading to kernel v4.16.

  libGL error: glx: failed to create dri2 screen
  libGL error: failed to load driver: iris

move the i915 feature check to after the hardware generation check
which results in:
  MESA: warning: Driver does not support the 0x3582 PCI ID.
  libGL error: glx: failed to create dri3 screen
  libGL error: failed to load driver: iris
  MESA: warning: Driver does not support the 0x3582 PCI ID.
  libGL error: glx: failed to create dri2 screen
  libGL error: failed to load driver: iris

Cc: mesa-stable
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18563>
2022-09-21 22:38:33 +00:00
Brian Paul
4e2d88781d gallivm: fix nir AOS swizzling issues
The nir code for AOS (aka linear) mode had a number of issues.

In some cases, the RGB->BGR swizzling wasn't happening, leading to
incorrect colors.  In other cases, bad swizzling caused the first
pixel's color to be written to four adjacent pixels.

Writemasks must also be swizzled.  For example, if an instruction's
writemask indicates the X component but the AOS component order is
BGRA we need to change the writemask to Z.

Another issue was with constant buffer values not getting consistently
convert to BGRA order.  Fixing this involves removing the
lp_nir_aos_conv_const() function and immediately converting immediate
values from 4 x f32 in [0,1] to 16 x u8 when we translate nir's
load_const so that we know the value is in the right linear/AOS layout
right away.

Finally, the llvmpipe_nir_fn_is_linear_compat() function was not
checking that nir_instr_type_load_const values are in [0,1] for AOS
execution.  The info.unclamped_immediates field is not needed for
the NIR path (but still used for the old TGSI path).

This fixes quite a few tests in our VMware suite.

Signed-off-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18213>
2022-09-21 21:55:11 +00:00
Brian Paul
d82abf448d gallivm: asst. clean-ups in lp_bld_sample_soa.c
Wrap lines to 78 chars.  Move var decls to where they're first used.
Etc.

Signed-off-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18213>
2022-09-21 21:55:11 +00:00
Brian Paul
a4ce5d74d7 llvmpipe: asst. formatting, clean-ups in lp_state_fs.c
Wrap lines to 78 chars.  Move var decls to where they're first used.
Etc.

Signed-off-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18213>
2022-09-21 21:55:11 +00:00
Brian Paul
bd7ed4c6a2 gallivm: change texture/sampler_index params to unsigned
To match other functions taking those params.

Signed-off-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18213>
2022-09-21 21:55:11 +00:00
Brian Paul
9b86745d69 gallivm: move lp_build_nir_aos_context declaration, etc
Move the lp_build_nir_aos_context struct declaration and
lp_nir_aos_context() cast wrapper from lp_bld_nir.h to
lp_bld_nir_aos.c and use the cast wrapper in more places.

Signed-off-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18213>
2022-09-21 21:55:11 +00:00
Brian Paul
2967cc25ea util: allow GALLIUM_LOG_FILE=stdout
To log gallium info to stdout instead of a file.

Signed-off-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18213>
2022-09-21 21:55:11 +00:00
Brian Paul
69f7c91fe9 llvmpipe: always pass non-zero writemask to assign_reg()
Removes an uneeded conditional expression.

Signed-off-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18213>
2022-09-21 21:55:11 +00:00
Brian Paul
9fbb77445c llvmpipe: further bump LP_MAX_TGSI_SHADER_IMAGES to 64
I previously bumped this to 32, but we need at least 64 to pass
a few other VMware tests (e.g. dx11-slots-uav-write-vs-gs-all-64).

Also update/generalize a comment.

Signed-off-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18213>
2022-09-21 21:55:11 +00:00
Brian Paul
ce65c7f0e9 lavapipe: s/u_foreach_bit/u_foreach_bit64/ in handle_pipeline_access()
Since the lvp_access_info fields are uint64_t.

Signed-off-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18213>
2022-09-21 21:55:11 +00:00
Chia-I Wu
79208d8bf3 turnip: advertise VkExternalFenceProperties correctly
Remove tu_GetPhysicalDeviceExternalFenceProperties and let the common
entrypoint does the work.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18711>
2022-09-21 20:55:41 +00:00