fdo-mirrors/mesa
1
0
Fork 0
mirror of https://gitlab.freedesktop.org/mesa/mesa.git synced 2025-12-23 15:30:14 +01:00
Code Issues Projects Releases Packages Wiki Activity Actions 1
52324 commits 64 branches 914 tags 1 GiB
Commit graph

52324 commits

This branch
This branch
All branches
Author SHA1 Message Date
Niels Ole Salscheider
8cc1860d4a st/mesa: index can be negative in the PROGRAM_CONSTANT case 
NOTE: This is a candidate for the 8.0 branch.

Reviewed-by: Brian Paul <brianp@vmware.com>
 2012-08-16 08:56:09 -06:00
Brian Paul
fd41cbc557 mesa: add cast to silence warning in _mesa_pack_rgba_span_from_ints() 2012-08-16 08:55:48 -06:00
Brian Paul
658044cde1 meta: remove unused variable 2012-08-16 08:53:55 -06:00
Michel Dänzer
1b11395a36 radeonsi: Fix symbol conflicts with r600g. 
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=50389

Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
 2012-08-16 12:01:16 +02:00
Michel Dänzer
51d9f37a72 radeonsi: Fix memory leaks if returning early from some state functions. 
Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
 2012-08-16 11:58:24 +02:00
Michel Dänzer
4b64fa2ff1 radeonsi: Fix LLVM context leak. 
Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
 2012-08-16 11:58:24 +02:00
Michel Dänzer
18abc270c5 gallium/radeon: Don't assign virtual address space for BO that already has one. 
We'd end up re-using the old one and throwing away the new one anyway, but only
after a roundtrip to the kernel.

Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
 2012-08-16 11:58:24 +02:00
Michel Dänzer
a60be05284 gallium/radeon: Create hole for waste when allocating from va_offset. 
Otherwise, the wasted area could never be used for an allocation again.

Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
 2012-08-16 11:58:24 +02:00
Michel Dänzer
1f455ef5bc gallium/radeon: Fix potential address space loss in radeon_bomgr_force_va(). 
Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
 2012-08-16 11:58:23 +02:00
Michel Dänzer
6d59b7f6dc gallium/radeon: Delete uppermost virtual address space hole if it's at the top. 
Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
 2012-08-16 11:58:23 +02:00
Michel Dänzer
f5fe81daea gallium/radeon: Fix losing holes when allocating virtual address space. 
If a hole exactly matches the allocated size plus alignment, we would fail to
preserve the alignment as a hole. This would result in never being able to use
the alignment area for an allocation again.

Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
 2012-08-16 11:58:23 +02:00
Michel Dänzer
206d07625c gallium/radeon: Merge holes when freeing virtual address space. 
Otherwise we'll likely end up with an ever increasing amount of ever smaller
holes.

Requires keeping the list ordered wrt offsets.

Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
 2012-08-16 09:39:36 +02:00
Michel Dänzer
c25968f3e2 gallium/radeon: Make va_offset 64 bits wide. 
Otherwise we'd wrap around after 32 bits. The kernel currently limits GPU
virtual address space to 4GB anyway, but that will probably change sooner or
later, and this would result in confusing error messages when running out of
virtual address space even now.

Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
 2012-08-16 09:37:33 +02:00
Vinson Lee
1597176f70 llvmpipe: Silence Coverity incorrect sizeof expression defect. 
Signed-off-by: Vinson Lee <vlee@freedesktop.org>
Reviewed-by: José Fonseca <jfonseca@vmware.com>
 2012-08-15 22:15:49 -07:00
Vinson Lee
3d6892c479 scons: Add option to enable floating-point textures. 
Signed-off-by: Vinson Lee <vlee@freedesktop.org>
Reviewed-by: José Fonseca <jfonseca@vmware.com>
 2012-08-15 22:04:24 -07:00
Dave Airlie
6a3ac03f2b glx/dri2: add dri2 prime support. 
This adds support for having libGL pick a different driver for prime support.

DRI_PRIME env var is set to the value retrieved from the server randr
provider calls, by the calling process. (generally DRI_PRIME=1 will be
the right answer).

Signed-off-by: Dave Airlie <airlied@redhat.com>
 2012-08-16 10:02:10 +10:00
Vincent Lejeune
565a4e2a86 radeon/llvm: Enable if-cvt 
Signed-off-by: Tom Stellard <thomas.stellard@amd.com>
 2012-08-15 21:07:14 +00:00
Vincent Lejeune
a614979286 radeon/llvm: Add callbacks needed by if-cvt 
Signed-off-by: Tom Stellard <thomas.stellard@amd.com>
 2012-08-15 21:07:14 +00:00
Vincent Lejeune
0eca5fd919 radeon/llvm: Lower branch/branch_cond into predicated jump 
Signed-off-by: Tom Stellard <thomas.stellard@amd.com>
 2012-08-15 21:07:14 +00:00
Vincent Lejeune
6db2e9fdb0 radeon/llvm: Add a predicated JUMP instruction 
Signed-off-by: Tom Stellard <thomas.stellard@amd.com>
 2012-08-15 21:07:13 +00:00
Vincent Lejeune
8263408a91 radeon/llvm: Support for predicate bit 
Tom Stellard:
  - A few changes to predicate register defs

Signed-off-by: Tom Stellard <thomas.stellard@amd.com>
 2012-08-15 21:07:13 +00:00
Vincent Lejeune
8f597d57e9 r600g: Glue to handle predicate aware output from llvm 
Signed-off-by: Tom Stellard <thomas.stellard@amd.com>
 2012-08-15 21:07:13 +00:00
Vincent Lejeune
72f7632c6b r600g: Fix instruction group merge when there are predicated insts. 
Signed-off-by: Tom Stellard <thomas.stellard@amd.com>
 2012-08-15 21:07:13 +00:00
Vincent Lejeune
56227f875b radeon/llvm: Do not use PV/PS if PRED_SEL does not match 
Signed-off-by: Tom Stellard <thomas.stellard@amd.com>
 2012-08-15 21:07:13 +00:00
Vincent Lejeune
da676eab93 r600g: Add support for predicates 
Signed-off-by: Tom Stellard <thomas.stellard@amd.com>
 2012-08-15 21:07:13 +00:00
Christian König
cf76edd300 radeonsi: move ps sampler state into PM4 stream 
Signed-off-by: Christian König <deathsimple@vodafone.de>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
 2012-08-15 22:13:19 +02:00
Christian König
ec5b698525 radeonsi: move ps sampler views into PM4 stream 
Signed-off-by: Christian König <deathsimple@vodafone.de>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
 2012-08-15 22:13:19 +02:00
Christian König
54de6f452c radeonsi: move vertex state descriptors into PM4 stream 
Signed-off-by: Christian König <deathsimple@vodafone.de>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
 2012-08-15 22:13:19 +02:00
Christian König
f2c95d93db radeonsi: add shader data infrastructure 
With this we can embed data for the shaders (like resource
descriptors) into the PM4 stream.

Signed-off-by: Christian König <deathsimple@vodafone.de>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
 2012-08-15 22:13:19 +02:00
Christian König
4444b9d1ec radeon/llvm: add support to fetch temps as vectors 
Necessary for texture fetches with temp regs as source on SI.

Signed-off-by: Christian König <deathsimple@vodafone.de>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
 2012-08-15 22:13:19 +02:00
Tom Stellard
b6051bc785 radeon/llvm: Remove AMDGPUUtil.cpp 2012-08-15 18:35:26 +00:00
Apostolos Bartziokas
040c2e0456 radeon/llvm: Cleanup AMDGPUUtil.cpp 2012-08-15 18:35:25 +00:00
Tom Stellard
3aaa209293 radeon/llvm: Lower loads from USE_SGPR adddress space during DAG lowering 2012-08-15 18:35:25 +00:00
Tom Stellard
40c41fe890 radeon/llvm: Add live-in registers during DAG lowering 
Psuedo instructions emulating live-in registers have been removed
and their corresponding intrinsics are now being lowered during DAG
lowering.
 2012-08-15 18:35:25 +00:00
Tom Stellard
f3480f9234 radeon/llvm: Lower store_output intrinsic during DAG lowering 2012-08-15 18:35:25 +00:00
Tom Stellard
a76a0f7422 radeon/llvm: Force VTX_READ instructions to use same reg for src and dst 
I was seeing some GPU hangs that seemed to be cause by ALU instructions
writing to the same register used as the source for VTX_READ.  Adding
this constraint to the VTX_READ instructions avoids this situation.
 2012-08-15 18:35:25 +00:00
Marek Olšák
97b4b97b2f radeonsi: fix build breakage after u_blitter changes 2012-08-15 20:03:37 +02:00
Marek Olšák
e0cc61bd91 gallium/u_blitter: document custom meta helpers 2012-08-15 19:20:58 +02:00
Marek Olšák
b3b5bb9ddb r600g: disable handling of DISCARD_RANGE 
https://bugs.freedesktop.org/show_bug.cgi?id=53130
 2012-08-15 19:20:58 +02:00
Marek Olšák
44f14ebd7b r600g: implement timestamp query and get_timestamp hook 
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
 2012-08-15 19:20:58 +02:00
Marek Olšák
1932bc8aae r600g: enable MSAA on evergreen by default 
v2: add the DRM version check
 2012-08-15 19:20:58 +02:00
Marek Olšák
870af19d70 r600g: implement copying between MSAA textures 2012-08-15 19:20:58 +02:00
Marek Olšák
0f86915c53 r600g: implement MSAA color resolve 2012-08-15 19:20:58 +02:00
Marek Olšák
94b634eca0 r600g: implement MSAA depth-stencil decompression and resolve 
and integer textures, which are resolved the same as depth, I think.
 2012-08-15 19:20:58 +02:00
Marek Olšák
6d3ad2dd2b r600g: implement TXQ_LZ opcode 2012-08-15 19:20:57 +02:00
Marek Olšák
4b78df9c81 r600g: implement MSAA rendering and texturing for evergreen and cayman 2012-08-15 19:20:57 +02:00
Marek Olšák
a01791add0 r600g: implement set_sample_mask 2012-08-15 19:20:57 +02:00
Marek Olšák
6517225078 r600g: implement alpha-to-coverage 2012-08-15 19:20:57 +02:00
Marek Olšák
26cb887ea2 r600g: implement alpha-to-one 2012-08-15 19:20:57 +02:00
Marek Olšák
4f21595276 r600g: remove support for 3-channel colorbuffers 
We have no sampler support for them.
 2012-08-15 19:20:57 +02:00