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radeonsi: Fix symbol conflicts with r600g.

Browse source 
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=50389

Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Michel Dänzer 2012-08-16 10:37:44 +02:00 • committed by Michel Dänzer
parent 51d9f37a72
commit 1b11395a36
10 changed files with 276 additions and 290 deletions
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10
src/gallium/drivers/radeonsi/r600.h
View file

@ -98,8 +98,8 @@ struct r600_so_target {
struct r600_context;
struct r600_screen;
void r600_get_backend_mask(struct r600_context *ctx);
void r600_context_flush(struct r600_context *ctx, unsigned flags);
void si_get_backend_mask(struct r600_context *ctx);
void si_context_flush(struct r600_context *ctx, unsigned flags);
struct r600_query *r600_context_query_create(struct r600_context *ctx, unsigned query_type);
void r600_context_query_destroy(struct r600_context *ctx, struct r600_query *query);
@ -112,11 +112,11 @@ void r600_context_queries_suspend(struct r600_context *ctx);
void r600_context_queries_resume(struct r600_context *ctx);
void r600_query_predication(struct r600_context *ctx, struct r600_query *query, int operation,
int flag_wait);
void r600_context_emit_fence(struct r600_context *ctx, struct si_resource *fence,
unsigned offset, unsigned value);
void si_context_emit_fence(struct r600_context *ctx, struct si_resource *fence,
unsigned offset, unsigned value);
void r600_context_draw_opaque_count(struct r600_context *ctx, struct r600_so_target *t);
void r600_need_cs_space(struct r600_context *ctx, unsigned num_dw, boolean count_draw_in);
void si_need_cs_space(struct r600_context *ctx, unsigned num_dw, boolean count_draw_in);
int si_context_init(struct r600_context *ctx);

10
src/gallium/drivers/radeonsi/r600_blit.c
View file

@ -113,7 +113,7 @@ static unsigned u_num_layers(struct pipe_resource *r, unsigned level)
}
}
void r600_blit_uncompress_depth(struct pipe_context *ctx, struct r600_resource_texture *texture)
void si_blit_uncompress_depth(struct pipe_context *ctx, struct r600_resource_texture *texture)
{
struct r600_context *rctx = (struct r600_context *)ctx;
unsigned layer, level;
@ -153,7 +153,7 @@ void r600_blit_uncompress_depth(struct pipe_context *ctx, struct r600_resource_t
texture->dirty_db = FALSE;
}
void r600_flush_depth_textures(struct r600_context *rctx)
void si_flush_depth_textures(struct r600_context *rctx)
{
unsigned int i;
@ -173,7 +173,7 @@ void r600_flush_depth_textures(struct r600_context *rctx)
if (tex->is_flushing_texture)
continue;
r600_blit_uncompress_depth(&rctx->context, tex);
si_blit_uncompress_depth(&rctx->context, tex);
}
/* also check CB here */
@ -187,7 +187,7 @@ void r600_flush_depth_textures(struct r600_context *rctx)
if (tex->is_flushing_texture)
continue;
r600_blit_uncompress_depth(&rctx->context, tex);
si_blit_uncompress_depth(&rctx->context, tex);
}
}
@ -374,7 +374,7 @@ static void r600_resource_copy_region(struct pipe_context *ctx,
r600_reset_blittable_to_compressed(dst, dst_level, &orig_info[1]);
}
void r600_init_blit_functions(struct r600_context *rctx)
void si_init_blit_functions(struct r600_context *rctx)
{
rctx->context.clear = r600_clear;
rctx->context.clear_render_target = r600_clear_render_target;

8
src/gallium/drivers/radeonsi/r600_buffer.c
View file

@ -114,7 +114,7 @@ static const struct u_resource_vtbl r600_buffer_vtbl =
NULL /* transfer_inline_write */
};
bool r600_init_resource(struct r600_screen *rscreen,
bool si_init_resource(struct r600_screen *rscreen,
struct si_resource *res,
unsigned size, unsigned alignment,
unsigned bind, unsigned usage)
@ -156,8 +156,8 @@ bool r600_init_resource(struct r600_screen *rscreen,
return true;
}
struct pipe_resource *r600_buffer_create(struct pipe_screen *screen,
const struct pipe_resource *templ)
struct pipe_resource *si_buffer_create(struct pipe_screen *screen,
const struct pipe_resource *templ)
{
struct r600_screen *rscreen = (struct r600_screen*)screen;
struct si_resource *rbuffer;
@ -171,7 +171,7 @@ struct pipe_resource *r600_buffer_create(struct pipe_screen *screen,
rbuffer->b.b.screen = screen;
rbuffer->b.vtbl = &r600_buffer_vtbl;
if (!r600_init_resource(rscreen, rbuffer, templ->width0, alignment, templ->bind, templ->usage)) {
if (!si_init_resource(rscreen, rbuffer, templ->width0, alignment, templ->bind, templ->usage)) {
FREE(rbuffer);
return NULL;
}

18
src/gallium/drivers/radeonsi/r600_hw_context.c
View file

@ -33,7 +33,7 @@
#define GROUP_FORCE_NEW_BLOCK 0
/* Get backends mask */
void r600_get_backend_mask(struct r600_context *ctx)
void si_get_backend_mask(struct r600_context *ctx)
{
struct radeon_winsys_cs *cs = ctx->cs;
struct si_resource *buffer;
@ -116,7 +116,7 @@ err:
}
/* initialize */
void r600_need_cs_space(struct r600_context *ctx, unsigned num_dw,
void si_need_cs_space(struct r600_context *ctx, unsigned num_dw,
boolean count_draw_in)
{
/* The number of dwords we already used in the CS so far. */
@ -177,7 +177,7 @@ static void r600_flush_framebuffer(struct r600_context *ctx)
ctx->flags &= ~R600_CONTEXT_DST_CACHES_DIRTY;
}
void r600_context_flush(struct r600_context *ctx, unsigned flags)
void si_context_flush(struct r600_context *ctx, unsigned flags)
{
struct radeon_winsys_cs *cs = ctx->cs;
bool queries_suspended = false;
@ -235,12 +235,12 @@ void r600_context_flush(struct r600_context *ctx, unsigned flags)
si_pm4_reset_emitted(ctx);
}
void r600_context_emit_fence(struct r600_context *ctx, struct si_resource *fence_bo, unsigned offset, unsigned value)
void si_context_emit_fence(struct r600_context *ctx, struct si_resource *fence_bo, unsigned offset, unsigned value)
{
struct radeon_winsys_cs *cs = ctx->cs;
uint64_t va;
r600_need_cs_space(ctx, 10, FALSE);
si_need_cs_space(ctx, 10, FALSE);
va = r600_resource_va(&ctx->screen->screen, (void*)fence_bo);
va = va + (offset << 2);
@ -364,7 +364,7 @@ void r600_query_begin(struct r600_context *ctx, struct r600_query *query)
uint32_t *results;
uint64_t va;
r600_need_cs_space(ctx, query->num_cs_dw * 2, TRUE);
si_need_cs_space(ctx, query->num_cs_dw * 2, TRUE);
new_results_end = (query->results_end + query->result_size) % query->buffer->b.b.width0;
@ -495,7 +495,7 @@ void r600_query_predication(struct r600_context *ctx, struct r600_query *query,
uint64_t va;
if (operation == PREDICATION_OP_CLEAR) {
r600_need_cs_space(ctx, 3, FALSE);
si_need_cs_space(ctx, 3, FALSE);
cs->buf[cs->cdw++] = PKT3(PKT3_SET_PREDICATION, 1, 0);
cs->buf[cs->cdw++] = 0;
@ -509,7 +509,7 @@ void r600_query_predication(struct r600_context *ctx, struct r600_query *query,
count = (query->buffer->b.b.width0 + query->results_end - query->results_start) % query->buffer->b.b.width0;
count /= query->result_size;
r600_need_cs_space(ctx, 5 * count, TRUE);
si_need_cs_space(ctx, 5 * count, TRUE);
op = PRED_OP(operation) | PREDICATION_DRAW_VISIBLE |
(flag_wait ? PREDICATION_HINT_WAIT : PREDICATION_HINT_NOWAIT_DRAW);
@ -647,7 +647,7 @@ void r600_context_queries_resume(struct r600_context *ctx)
void r600_context_draw_opaque_count(struct r600_context *ctx, struct r600_so_target *t)
{
struct radeon_winsys_cs *cs = ctx->cs;
r600_need_cs_space(ctx, 14 + 21, TRUE);
si_need_cs_space(ctx, 14 + 21, TRUE);
cs->buf[cs->cdw++] = PKT3(PKT3_SET_CONTEXT_REG, 1, 0);
cs->buf[cs->cdw++] = (R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET - SI_CONTEXT_REG_OFFSET) >> 2;

6
src/gallium/drivers/radeonsi/r600_resource.c
View file

@ -27,9 +27,9 @@ static struct pipe_resource *r600_resource_create(struct pipe_screen *screen,
const struct pipe_resource *templ)
{
if (templ->target == PIPE_BUFFER) {
return r600_buffer_create(screen, templ);
return si_buffer_create(screen, templ);
} else {
return r600_texture_create(screen, templ);
return si_texture_create(screen, templ);
}
}
@ -40,7 +40,7 @@ static struct pipe_resource *r600_resource_from_handle(struct pipe_screen * scre
if (templ->target == PIPE_BUFFER) {
return NULL;
} else {
return r600_texture_from_handle(screen, templ, whandle);
return si_texture_from_handle(screen, templ, whandle);
}
}

20
src/gallium/drivers/radeonsi/r600_resource.h
View file

@ -70,26 +70,14 @@ struct r600_surface {
void r600_init_screen_resource_functions(struct pipe_screen *screen);
/* r600_texture */
struct pipe_resource *r600_texture_create(struct pipe_screen *screen,
struct pipe_resource *si_texture_create(struct pipe_screen *screen,
const struct pipe_resource *templ);
struct pipe_resource *r600_texture_from_handle(struct pipe_screen *screen,
const struct pipe_resource *base,
struct winsys_handle *whandle);
struct pipe_resource *si_texture_from_handle(struct pipe_screen *screen,
const struct pipe_resource *base,
struct winsys_handle *whandle);
int r600_texture_depth_flush(struct pipe_context *ctx, struct pipe_resource *texture, boolean just_create);
/* r600_texture.c texture transfer functions. */
struct pipe_transfer* r600_texture_get_transfer(struct pipe_context *ctx,
struct pipe_resource *texture,
unsigned level,
unsigned usage,
const struct pipe_box *box);
void r600_texture_transfer_destroy(struct pipe_context *ctx,
struct pipe_transfer *trans);
void* r600_texture_transfer_map(struct pipe_context *ctx,
struct pipe_transfer* transfer);
void r600_texture_transfer_unmap(struct pipe_context *ctx,
struct pipe_transfer* transfer);
struct r600_context;

458
src/gallium/drivers/radeonsi/r600_texture.c
View file

@ -66,7 +66,7 @@ static void r600_copy_from_staging_texture(struct pipe_context *ctx, struct r600
0, &sbox);
}
unsigned r600_texture_get_offset(struct r600_resource_texture *rtex,
static unsigned r600_texture_get_offset(struct r600_resource_texture *rtex,
unsigned level, unsigned layer)
{
unsigned offset = rtex->offset[level];
@ -489,222 +489,6 @@ static void r600_texture_destroy(struct pipe_screen *screen,
FREE(rtex);
}
static const struct u_resource_vtbl r600_texture_vtbl =
{
r600_texture_get_handle, /* get_handle */
r600_texture_destroy, /* resource_destroy */
r600_texture_get_transfer, /* get_transfer */
r600_texture_transfer_destroy, /* transfer_destroy */
r600_texture_transfer_map, /* transfer_map */
u_default_transfer_flush_region,/* transfer_flush_region */
r600_texture_transfer_unmap, /* transfer_unmap */
NULL /* transfer_inline_write */
};
static struct r600_resource_texture *
r600_texture_create_object(struct pipe_screen *screen,
const struct pipe_resource *base,
unsigned array_mode,
unsigned pitch_in_bytes_override,
unsigned max_buffer_size,
struct pb_buffer *buf,
boolean alloc_bo,
struct radeon_surface *surface)
{
struct r600_resource_texture *rtex;
struct si_resource *resource;
struct r600_screen *rscreen = (struct r600_screen*)screen;
int r;
rtex = CALLOC_STRUCT(r600_resource_texture);
if (rtex == NULL)
return NULL;
resource = &rtex->resource;
resource->b.b = *base;
resource->b.vtbl = &r600_texture_vtbl;
pipe_reference_init(&resource->b.b.reference, 1);
resource->b.b.screen = screen;
rtex->pitch_override = pitch_in_bytes_override;
rtex->real_format = base->format;
/* only mark depth textures the HW can hit as depth textures */
if (util_format_is_depth_or_stencil(rtex->real_format) && permit_hardware_blit(screen, base))
rtex->depth = 1;
r600_setup_miptree(screen, rtex, array_mode);
rtex->surface = *surface;
r = r600_setup_surface(screen, rtex, array_mode, pitch_in_bytes_override);
if (r) {
FREE(rtex);
return NULL;
}
/* Now create the backing buffer. */
if (!buf && alloc_bo) {
struct pipe_resource *ptex = &rtex->resource.b.b;
unsigned base_align = r600_get_base_alignment(screen, ptex->format, array_mode);
base_align = rtex->surface.bo_alignment;
if (!r600_init_resource(rscreen, resource, rtex->size, base_align, base->bind, base->usage)) {
FREE(rtex);
return NULL;
}
} else if (buf) {
resource->buf = buf;
resource->cs_buf = rscreen->ws->buffer_get_cs_handle(buf);
resource->domains = RADEON_DOMAIN_GTT | RADEON_DOMAIN_VRAM;
}
return rtex;
}
struct pipe_resource *r600_texture_create(struct pipe_screen *screen,
const struct pipe_resource *templ)
{
struct r600_screen *rscreen = (struct r600_screen*)screen;
struct radeon_surface surface;
unsigned array_mode = 0;
int r;
#if 0
if (!(templ->flags & R600_RESOURCE_FLAG_TRANSFER) &&
!(templ->bind & PIPE_BIND_SCANOUT)) {
if (permit_hardware_blit(screen, templ)) {
array_mode = V_009910_ARRAY_2D_TILED_THIN1;
}
}
#endif
r = r600_init_surface(&surface, templ, array_mode);
if (r) {
return NULL;
}
r = rscreen->ws->surface_best(rscreen->ws, &surface);
if (r) {
return NULL;
}
return (struct pipe_resource *)r600_texture_create_object(screen, templ, array_mode,
0, 0, NULL, TRUE, &surface);
}
static struct pipe_surface *r600_create_surface(struct pipe_context *pipe,
struct pipe_resource *texture,
const struct pipe_surface *surf_tmpl)
{
struct r600_resource_texture *rtex = (struct r600_resource_texture*)texture;
struct r600_surface *surface = CALLOC_STRUCT(r600_surface);
unsigned level = surf_tmpl->u.tex.level;
assert(surf_tmpl->u.tex.first_layer == surf_tmpl->u.tex.last_layer);
if (surface == NULL)
return NULL;
/* XXX no offset */
/* offset = r600_texture_get_offset(rtex, level, surf_tmpl->u.tex.first_layer);*/
pipe_reference_init(&surface->base.reference, 1);
pipe_resource_reference(&surface->base.texture, texture);
surface->base.context = pipe;
surface->base.format = surf_tmpl->format;
surface->base.width = mip_minify(texture->width0, level);
surface->base.height = mip_minify(texture->height0, level);
surface->base.usage = surf_tmpl->usage;
surface->base.texture = texture;
surface->base.u.tex.first_layer = surf_tmpl->u.tex.first_layer;
surface->base.u.tex.last_layer = surf_tmpl->u.tex.last_layer;
surface->base.u.tex.level = level;
surface->aligned_height = r600_texture_get_nblocksy(pipe->screen,
rtex, level);
return &surface->base;
}
static void r600_surface_destroy(struct pipe_context *pipe,
struct pipe_surface *surface)
{
pipe_resource_reference(&surface->texture, NULL);
FREE(surface);
}
struct pipe_resource *r600_texture_from_handle(struct pipe_screen *screen,
const struct pipe_resource *templ,
struct winsys_handle *whandle)
{
struct r600_screen *rscreen = (struct r600_screen*)screen;
struct pb_buffer *buf = NULL;
unsigned stride = 0;
unsigned array_mode = 0;
enum radeon_bo_layout micro, macro;
struct radeon_surface surface;
int r;
/* Support only 2D textures without mipmaps */
if ((templ->target != PIPE_TEXTURE_2D && templ->target != PIPE_TEXTURE_RECT) ||
templ->depth0 != 1 || templ->last_level != 0)
return NULL;
buf = rscreen->ws->buffer_from_handle(rscreen->ws, whandle, &stride);
if (!buf)
return NULL;
rscreen->ws->buffer_get_tiling(buf, &micro, &macro,
&surface.bankw, &surface.bankh,
&surface.tile_split,
&surface.stencil_tile_split,
&surface.mtilea);
if (macro == RADEON_LAYOUT_TILED)
array_mode = V_009910_ARRAY_2D_TILED_THIN1;
else if (micro == RADEON_LAYOUT_TILED)
array_mode = V_009910_ARRAY_1D_TILED_THIN1;
else
array_mode = 0;
r = r600_init_surface(&surface, templ, array_mode);
if (r) {
return NULL;
}
return (struct pipe_resource *)r600_texture_create_object(screen, templ, array_mode,
stride, 0, buf, FALSE, &surface);
}
int r600_texture_depth_flush(struct pipe_context *ctx,
struct pipe_resource *texture, boolean just_create)
{
struct r600_resource_texture *rtex = (struct r600_resource_texture*)texture;
struct pipe_resource resource;
if (rtex->flushed_depth_texture)
goto out;
resource.target = texture->target;
resource.format = texture->format;
resource.width0 = texture->width0;
resource.height0 = texture->height0;
resource.depth0 = texture->depth0;
resource.array_size = texture->array_size;
resource.last_level = texture->last_level;
resource.nr_samples = texture->nr_samples;
resource.usage = PIPE_USAGE_DYNAMIC;
resource.bind = texture->bind | PIPE_BIND_DEPTH_STENCIL;
resource.flags = R600_RESOURCE_FLAG_TRANSFER | texture->flags;
rtex->flushed_depth_texture = (struct r600_resource_texture *)ctx->screen->resource_create(ctx->screen, &resource);
if (rtex->flushed_depth_texture == NULL) {
R600_ERR("failed to create temporary texture to hold untiled copy\n");
return -ENOMEM;
}
((struct r600_resource_texture *)rtex->flushed_depth_texture)->is_flushing_texture = TRUE;
out:
if (just_create)
return 0;
/* XXX: only do this if the depth texture has actually changed:
*/
r600_blit_uncompress_depth(ctx, rtex);
return 0;
}
/* Needs adjustment for pixelformat:
*/
static INLINE unsigned u_box_volume( const struct pipe_box *box )
@ -712,11 +496,11 @@ static INLINE unsigned u_box_volume( const struct pipe_box *box )
return box->width * box->depth * box->height;
};
struct pipe_transfer* r600_texture_get_transfer(struct pipe_context *ctx,
struct pipe_resource *texture,
unsigned level,
unsigned usage,
const struct pipe_box *box)
static struct pipe_transfer* si_texture_get_transfer(struct pipe_context *ctx,
struct pipe_resource *texture,
unsigned level,
unsigned usage,
const struct pipe_box *box)
{
struct r600_resource_texture *rtex = (struct r600_resource_texture*)texture;
struct pipe_resource resource;
@ -823,8 +607,8 @@ struct pipe_transfer* r600_texture_get_transfer(struct pipe_context *ctx,
return &trans->transfer;
}
void r600_texture_transfer_destroy(struct pipe_context *ctx,
struct pipe_transfer *transfer)
static void si_texture_transfer_destroy(struct pipe_context *ctx,
struct pipe_transfer *transfer)
{
struct r600_transfer *rtransfer = (struct r600_transfer*)transfer;
struct pipe_resource *texture = transfer->resource;
@ -846,8 +630,8 @@ void r600_texture_transfer_destroy(struct pipe_context *ctx,
FREE(transfer);
}
void* r600_texture_transfer_map(struct pipe_context *ctx,
struct pipe_transfer* transfer)
static void* si_texture_transfer_map(struct pipe_context *ctx,
struct pipe_transfer* transfer)
{
struct r600_context *rctx = (struct r600_context *)ctx;
struct r600_transfer *rtransfer = (struct r600_transfer*)transfer;
@ -878,8 +662,8 @@ void* r600_texture_transfer_map(struct pipe_context *ctx,
return map + offset;
}
void r600_texture_transfer_unmap(struct pipe_context *ctx,
struct pipe_transfer* transfer)
static void si_texture_transfer_unmap(struct pipe_context *ctx,
struct pipe_transfer* transfer)
{
struct r600_transfer *rtransfer = (struct r600_transfer*)transfer;
struct r600_context *rctx = (struct r600_context*)ctx;
@ -899,7 +683,223 @@ void r600_texture_transfer_unmap(struct pipe_context *ctx,
rctx->ws->buffer_unmap(buf);
}
void r600_init_surface_functions(struct r600_context *r600)
static const struct u_resource_vtbl r600_texture_vtbl =
{
r600_texture_get_handle, /* get_handle */
r600_texture_destroy, /* resource_destroy */
si_texture_get_transfer, /* get_transfer */
si_texture_transfer_destroy, /* transfer_destroy */
si_texture_transfer_map, /* transfer_map */
u_default_transfer_flush_region,/* transfer_flush_region */
si_texture_transfer_unmap, /* transfer_unmap */
NULL /* transfer_inline_write */
};
static struct r600_resource_texture *
r600_texture_create_object(struct pipe_screen *screen,
const struct pipe_resource *base,
unsigned array_mode,
unsigned pitch_in_bytes_override,
unsigned max_buffer_size,
struct pb_buffer *buf,
boolean alloc_bo,
struct radeon_surface *surface)
{
struct r600_resource_texture *rtex;
struct si_resource *resource;
struct r600_screen *rscreen = (struct r600_screen*)screen;
int r;
rtex = CALLOC_STRUCT(r600_resource_texture);
if (rtex == NULL)
return NULL;
resource = &rtex->resource;
resource->b.b = *base;
resource->b.vtbl = &r600_texture_vtbl;
pipe_reference_init(&resource->b.b.reference, 1);
resource->b.b.screen = screen;
rtex->pitch_override = pitch_in_bytes_override;
rtex->real_format = base->format;
/* only mark depth textures the HW can hit as depth textures */
if (util_format_is_depth_or_stencil(rtex->real_format) && permit_hardware_blit(screen, base))
rtex->depth = 1;
r600_setup_miptree(screen, rtex, array_mode);
rtex->surface = *surface;
r = r600_setup_surface(screen, rtex, array_mode, pitch_in_bytes_override);
if (r) {
FREE(rtex);
return NULL;
}
/* Now create the backing buffer. */
if (!buf && alloc_bo) {
struct pipe_resource *ptex = &rtex->resource.b.b;
unsigned base_align = r600_get_base_alignment(screen, ptex->format, array_mode);
base_align = rtex->surface.bo_alignment;
if (!si_init_resource(rscreen, resource, rtex->size, base_align, base->bind, base->usage)) {
FREE(rtex);
return NULL;
}
} else if (buf) {
resource->buf = buf;
resource->cs_buf = rscreen->ws->buffer_get_cs_handle(buf);
resource->domains = RADEON_DOMAIN_GTT | RADEON_DOMAIN_VRAM;
}
return rtex;
}
struct pipe_resource *si_texture_create(struct pipe_screen *screen,
const struct pipe_resource *templ)
{
struct r600_screen *rscreen = (struct r600_screen*)screen;
struct radeon_surface surface;
unsigned array_mode = 0;
int r;
#if 0
if (!(templ->flags & R600_RESOURCE_FLAG_TRANSFER) &&
!(templ->bind & PIPE_BIND_SCANOUT)) {
if (permit_hardware_blit(screen, templ)) {
array_mode = V_009910_ARRAY_2D_TILED_THIN1;
}
}
#endif
r = r600_init_surface(&surface, templ, array_mode);
if (r) {
return NULL;
}
r = rscreen->ws->surface_best(rscreen->ws, &surface);
if (r) {
return NULL;
}
return (struct pipe_resource *)r600_texture_create_object(screen, templ, array_mode,
0, 0, NULL, TRUE, &surface);
}
static struct pipe_surface *r600_create_surface(struct pipe_context *pipe,
struct pipe_resource *texture,
const struct pipe_surface *surf_tmpl)
{
struct r600_resource_texture *rtex = (struct r600_resource_texture*)texture;
struct r600_surface *surface = CALLOC_STRUCT(r600_surface);
unsigned level = surf_tmpl->u.tex.level;
assert(surf_tmpl->u.tex.first_layer == surf_tmpl->u.tex.last_layer);
if (surface == NULL)
return NULL;
/* XXX no offset */
/* offset = r600_texture_get_offset(rtex, level, surf_tmpl->u.tex.first_layer);*/
pipe_reference_init(&surface->base.reference, 1);
pipe_resource_reference(&surface->base.texture, texture);
surface->base.context = pipe;
surface->base.format = surf_tmpl->format;
surface->base.width = mip_minify(texture->width0, level);
surface->base.height = mip_minify(texture->height0, level);
surface->base.usage = surf_tmpl->usage;
surface->base.texture = texture;
surface->base.u.tex.first_layer = surf_tmpl->u.tex.first_layer;
surface->base.u.tex.last_layer = surf_tmpl->u.tex.last_layer;
surface->base.u.tex.level = level;
surface->aligned_height = r600_texture_get_nblocksy(pipe->screen,
rtex, level);
return &surface->base;
}
static void r600_surface_destroy(struct pipe_context *pipe,
struct pipe_surface *surface)
{
pipe_resource_reference(&surface->texture, NULL);
FREE(surface);
}
struct pipe_resource *si_texture_from_handle(struct pipe_screen *screen,
const struct pipe_resource *templ,
struct winsys_handle *whandle)
{
struct r600_screen *rscreen = (struct r600_screen*)screen;
struct pb_buffer *buf = NULL;
unsigned stride = 0;
unsigned array_mode = 0;
enum radeon_bo_layout micro, macro;
struct radeon_surface surface;
int r;
/* Support only 2D textures without mipmaps */
if ((templ->target != PIPE_TEXTURE_2D && templ->target != PIPE_TEXTURE_RECT) ||
templ->depth0 != 1 || templ->last_level != 0)
return NULL;
buf = rscreen->ws->buffer_from_handle(rscreen->ws, whandle, &stride);
if (!buf)
return NULL;
rscreen->ws->buffer_get_tiling(buf, &micro, &macro,
&surface.bankw, &surface.bankh,
&surface.tile_split,
&surface.stencil_tile_split,
&surface.mtilea);
if (macro == RADEON_LAYOUT_TILED)
array_mode = V_009910_ARRAY_2D_TILED_THIN1;
else if (micro == RADEON_LAYOUT_TILED)
array_mode = V_009910_ARRAY_1D_TILED_THIN1;
else
array_mode = 0;
r = r600_init_surface(&surface, templ, array_mode);
if (r) {
return NULL;
}
return (struct pipe_resource *)r600_texture_create_object(screen, templ, array_mode,
stride, 0, buf, FALSE, &surface);
}
int r600_texture_depth_flush(struct pipe_context *ctx,
struct pipe_resource *texture, boolean just_create)
{
struct r600_resource_texture *rtex = (struct r600_resource_texture*)texture;
struct pipe_resource resource;
if (rtex->flushed_depth_texture)
goto out;
resource.target = texture->target;
resource.format = texture->format;
resource.width0 = texture->width0;
resource.height0 = texture->height0;
resource.depth0 = texture->depth0;
resource.array_size = texture->array_size;
resource.last_level = texture->last_level;
resource.nr_samples = texture->nr_samples;
resource.usage = PIPE_USAGE_DYNAMIC;
resource.bind = texture->bind | PIPE_BIND_DEPTH_STENCIL;
resource.flags = R600_RESOURCE_FLAG_TRANSFER | texture->flags;
rtex->flushed_depth_texture = (struct r600_resource_texture *)ctx->screen->resource_create(ctx->screen, &resource);
if (rtex->flushed_depth_texture == NULL) {
R600_ERR("failed to create temporary texture to hold untiled copy\n");
return -ENOMEM;
}
((struct r600_resource_texture *)rtex->flushed_depth_texture)->is_flushing_texture = TRUE;
out:
if (just_create)
return 0;
/* XXX: only do this if the depth texture has actually changed:
*/
si_blit_uncompress_depth(ctx, rtex);
return 0;
}
void si_init_surface_functions(struct r600_context *r600)
{
r600->context.create_surface = r600_create_surface;
r600->context.surface_destroy = r600_surface_destroy;

10
src/gallium/drivers/radeonsi/radeonsi_pipe.c
View file

@ -117,7 +117,7 @@ static struct r600_fence *r600_create_fence(struct r600_context *rctx)
pipe_reference_init(&fence->reference, 1);
rscreen->fences.data[fence->index] = 0;
r600_context_emit_fence(rctx, rscreen->fences.bo, fence->index, 1);
si_context_emit_fence(rctx, rscreen->fences.bo, fence->index, 1);
/* Create a dummy BO so that fence_finish without a timeout can sleep waiting for completion */
fence->sleep_bo = si_resource_create_custom(&rctx->screen->screen, PIPE_USAGE_STAGING, 1);
@ -149,7 +149,7 @@ void radeonsi_flush(struct pipe_context *ctx, struct pipe_fence_handle **fence,
ctx->render_condition(ctx, NULL, 0);
}
r600_context_flush(rctx, flags);
si_context_flush(rctx, flags);
/* Re-enable render condition. */
if (render_cond) {
@ -206,10 +206,10 @@ static struct pipe_context *r600_create_context(struct pipe_screen *screen, void
rctx->family = rscreen->family;
rctx->chip_class = rscreen->chip_class;
r600_init_blit_functions(rctx);
si_init_blit_functions(rctx);
r600_init_query_functions(rctx);
r600_init_context_resource_functions(rctx);
r600_init_surface_functions(rctx);
si_init_surface_functions(rctx);
rctx->context.create_video_decoder = vl_create_decoder;
rctx->context.create_video_buffer = vl_video_buffer_create;
@ -249,7 +249,7 @@ static struct pipe_context *r600_create_context(struct pipe_screen *screen, void
return NULL;
}
r600_get_backend_mask(rctx); /* this emits commands and must be last */
si_get_backend_mask(rctx); /* this emits commands and must be last */
rctx->dummy_pixel_shader =
util_make_fragment_cloneinput_shader(&rctx->context, 0,

22
src/gallium/drivers/radeonsi/radeonsi_pipe.h
View file

@ -186,18 +186,18 @@ struct r600_context {
};
/* r600_blit.c */
void r600_init_blit_functions(struct r600_context *rctx);
void r600_blit_uncompress_depth(struct pipe_context *ctx, struct r600_resource_texture *texture);
void si_init_blit_functions(struct r600_context *rctx);
void si_blit_uncompress_depth(struct pipe_context *ctx, struct r600_resource_texture *texture);
void r600_blit_push_depth(struct pipe_context *ctx, struct r600_resource_texture *texture);
void r600_flush_depth_textures(struct r600_context *rctx);
void si_flush_depth_textures(struct r600_context *rctx);
/* r600_buffer.c */
bool r600_init_resource(struct r600_screen *rscreen,
struct si_resource *res,
unsigned size, unsigned alignment,
unsigned bind, unsigned usage);
struct pipe_resource *r600_buffer_create(struct pipe_screen *screen,
const struct pipe_resource *templ);
bool si_init_resource(struct r600_screen *rscreen,
struct si_resource *res,
unsigned size, unsigned alignment,
unsigned bind, unsigned usage);
struct pipe_resource *si_buffer_create(struct pipe_screen *screen,
const struct pipe_resource *templ);
void r600_upload_index_buffer(struct r600_context *rctx,
struct pipe_index_buffer *ib, unsigned count);
@ -214,9 +214,7 @@ void r600_init_context_resource_functions(struct r600_context *r600);
/* r600_texture.c */
void r600_init_screen_texture_functions(struct pipe_screen *screen);
void r600_init_surface_functions(struct r600_context *r600);
unsigned r600_texture_get_offset(struct r600_resource_texture *rtex,
unsigned level, unsigned layer);
void si_init_surface_functions(struct r600_context *r600);
/* r600_translate.c */
void r600_translate_index_buffer(struct r600_context *r600,

4
src/gallium/drivers/radeonsi/si_state_draw.c
View file

@ -354,7 +354,7 @@ static void si_update_derived_state(struct r600_context *rctx)
if (!rctx->blitter->running) {
if (rctx->have_depth_fb || rctx->have_depth_texture)
r600_flush_depth_textures(rctx);
si_flush_depth_textures(rctx);
}
if ((rctx->ps_shader->shader.fs_write_all &&
@ -551,7 +551,7 @@ void si_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *info)
/* Emit states. */
rctx->pm4_dirty_cdwords += si_pm4_dirty_dw(rctx);
r600_need_cs_space(rctx, 0, TRUE);
si_need_cs_space(rctx, 0, TRUE);
si_pm4_emit_dirty(rctx);
rctx->pm4_dirty_cdwords = 0;