Commit graph

90923 commits

Author SHA1 Message Date
Emil Velikov
2c4c47dcb7 swr: automake: add gen_common.py to the tarball
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
2017-04-05 13:16:28 +01:00
Emil Velikov
e664cfc5a7 intel: genxml: automake: include gen_bits_header.py in the tarball
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
2017-04-05 13:16:28 +01:00
Emil Velikov
e180680980 intel: genxml: automake: polish automake rules
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
2017-04-05 13:16:28 +01:00
Emil Velikov
e2adec3a17 amd/addrlib: automake: add all headers to the tarball
Fixes: 7f160efcde ("amd/addrlib: import gfx9 support")
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
2017-04-05 13:16:28 +01:00
Nicolai Hähnle
570e50af4b radeonsi: enable ARB_sparse_buffer
v2:
- fill in DRM version requirement
- disable on SI due to CP DMA faults

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2017-04-05 10:44:32 +02:00
Nicolai Hähnle
aee473eb01 radeonsi: disable SDMA clears and copies for sparse buffers
VM faults cannot be disabled for SDMA on <= VI.

We could still use SDMA by asking the winsys about which parts of the
buffers are committed. This is left as a potential future improvement.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2017-04-05 10:37:19 +02:00
Nicolai Hähnle
0a685ce9a7 gallium/radeon: implement pipe->resource_commit
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2017-04-05 10:37:19 +02:00
Nicolai Hähnle
e077c5fe65 gallium/radeon: transfers and invalidation for sparse buffers
Sparse buffers can never be mapped by the CPU.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2017-04-05 10:37:19 +02:00
Nicolai Hähnle
5969a373a1 gallium/radeon: implement sparse buffer creation
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2017-04-05 10:37:19 +02:00
Nicolai Hähnle
47e59a7e36 winsys/amdgpu: sparse buffer debugging helpers
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2017-04-05 10:37:19 +02:00
Nicolai Hähnle
0baee15596 winsys/amdgpu: take fences when freeing a backing buffer
We never add fences to backing buffers during submit. When we free a
backing buffer, it must inherit the sparse buffer's fences, so that it
doesn't get re-used prematurely via the cache.

v2:
- remove pipe_mutex_*

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2017-04-05 10:37:18 +02:00
Nicolai Hähnle
79dae12b41 winsys/amdgpu: add sparse buffers to CS
... and implement the corresponding fence handling.

v2:
- add missing bit in amdgpu_bo_is_referenced_by_cs_with_usage
- remove pipe_mutex_*

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2017-04-05 10:37:18 +02:00
Nicolai Hähnle
667da4eaed winsys/amdgpu: sparse buffer creation / destruction / commitment
This is the bulk of the buffer allocation logic. It is fairly simple and
stupid. We'll probably want to use e.g. interval trees at some point to
keep track of commitments, but Mesa doesn't have an implementation of those
yet.

v2:
- remove pipe_mutex_*
- fix total_backing_pages accounting
- simplify by using the new VA_OP_CLEAR/REPLACE kernel interface

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2017-04-05 10:37:18 +02:00
Nicolai Hähnle
e348248647 winsys/amdgpu: add sparse buffer data structures
v2:
- remove pipe_mutex_*
- use a simple page commitment array

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2017-04-05 10:37:18 +02:00
Nicolai Hähnle
f3e514361c winsys/amdgpu: extend amdgpu_add_fence to allow adding multiple fences
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2017-04-05 10:37:18 +02:00
Nicolai Hähnle
ae4f442304 winsys/amdgpu: build handles and flags list late on submit thread
This probably has only minor performance effects, but it simplifies some
subsequent code slightly.

Ideally, it could also be used to simplify the handling of slab buffers
in the same way, but unfortunately that's not possible as long as we need
indices for relocations.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2017-04-05 10:37:17 +02:00
Nicolai Hähnle
0e476f6c03 winsys/amdgpu: share common code in amdgpu_add_fence_dependencies
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2017-04-05 10:37:17 +02:00
Nicolai Hähnle
1c125fdef0 winsys/amdgpu: extract amdgpu_do_add_real_buffer
We will use it for delayed adding of sparse buffers' backing buffers.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2017-04-05 10:37:17 +02:00
Nicolai Hähnle
a338f427ac winsys/radeon: sparse buffers will not be supported
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2017-04-05 10:37:17 +02:00
Nicolai Hähnle
c2637a17d9 radeon/winsys: add sparse buffer interface
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2017-04-05 10:37:17 +02:00
Nicolai Hähnle
d9bc4d8305 st/mesa: plumbing for sparse buffers
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2017-04-05 10:37:16 +02:00
Nicolai Hähnle
2599b23f7c st/mesa: enable ARB_sparse_buffer when supported
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2017-04-05 10:37:16 +02:00
Nicolai Hähnle
634266c952 trace: add resource_commit pass-through
v2: fix return type to bool (Marek)

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2017-04-05 10:37:16 +02:00
Nicolai Hähnle
0e1c75acae ddebug: add resource_commit pass-through
v2: fix return type to bool (Marek)

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2017-04-05 10:37:16 +02:00
Nicolai Hähnle
d6e6fa01a5 gallium: add sparse buffer interface and capability
v2:
- explain the resource_commit interface in more detail

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2017-04-05 10:37:04 +02:00
Nicolai Hähnle
4e6feacf6a mesa: implement sparse buffer commitment
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2017-04-05 10:31:02 +02:00
Nicolai Hähnle
d6fcbe1c2a mesa: implement sparse storage buffer allocation
v2:
- spec quote and style (Ian)

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2017-04-05 10:31:01 +02:00
Nicolai Hähnle
94227684c4 mesa: implement SPARSE_BUFFER_PAGE_SIZE_ARB
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2017-04-05 10:31:01 +02:00
Nicolai Hähnle
d085c7ce7c mesa: Add GL_ARB_sparse_buffer boilerplate
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2017-04-05 10:31:01 +02:00
Nicolai Hähnle
a0970de839 configure.ac: require libdrm_amdgpu 2.4.77
The sparse buffer implementation requires amdgpu_bo_va_op_raw.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2017-04-05 10:30:42 +02:00
Matt Turner
d5ee55f028 mesa: Replace program locks with atomic inc/dec.
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
2017-04-05 14:54:49 +10:00
Jason Ekstrand
060a6434ec anv: Advertise larger heap sizes
Instead of just advertising the aperture size, we do something more
intelligent.  On systems with a full 48-bit PPGTT, we can address 100%
of the available system RAM from the GPU.  In order to keep clients from
burning 100% of your available RAM for graphics resources, we have a
nice little heuristic (which has received exactly zero tuning) to keep
things under a reasonable level of control.

Reviewed-by: Kristian H. Kristensen <krh@bitplanet.net>
2017-04-04 18:33:52 -07:00
Jason Ekstrand
651ec926fc anv: Add support for 48-bit addresses
This commit adds support for using the full 48-bit address space on
Broadwell and newer hardware.  Thanks to certain limitations, not all
objects can be placed above the 32-bit boundary.  In particular, general
and state base address need to live within 32 bits.  (See also
Wa32bitGeneralStateOffset and Wa32bitInstructionBaseOffset.)  In order
to handle this, we add a supports_48bit_address field to anv_bo and only
set EXEC_OBJECT_SUPPORTS_48B_ADDRESS if that bit is set.  We set the bit
for all client-allocated memory objects but leave it false for
driver-allocated objects.  While this is more conservative than needed,
all driver allocations should easily fit in the first 32 bits of address
space and keeps things simple because we don't have to think about
whether or not any given one of our allocation data structures will be
used in a 48-bit-unsafe way.

Reviewed-by: Kristian H. Kristensen <krh@bitplanet.net>
2017-04-04 18:33:52 -07:00
Jason Ekstrand
439da38d18 anv: Replace anv_bo::is_winsys_bo with a uint32_t flags
Reviewed-by: Kristian H. Kristensen <krh@bitplanet.net>
2017-04-04 18:33:52 -07:00
Jason Ekstrand
f938354362 i965/blorp: Align vertex buffers to 64B
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Cc: "13.0 17.0" <mesa-stable@lists.freedesktop.org>
2017-04-04 18:33:52 -07:00
Jason Ekstrand
5d1ba2cb04 anv/blorp: Align vertex buffers to 64B
This fixes issues seen when adding support for full 48-bit addresses.
The 48-bit addresses themselves have nothing to do with it other than
that it caused the kernel to place buffers slightly differently so they
interacted differently with the caches.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Cc: "13.0 17.0" <mesa-stable@lists.freedesktop.org>
2017-04-04 18:33:52 -07:00
Jason Ekstrand
c964f0e485 anv: Query the kernel for reset status
When a client causes a GPU hang (or experiences issues due to a hang in
another client) we want to let it know as soon as possible.  In
particular, if it submits work with a fence and calls vkWaitForFences or
vkQueueQaitIdle and it returns VK_SUCCESS, then the client should be
able to trust the results of that rendering.  In order to provide this
guarantee, we have to ask the kernel for context status in a few key
locations.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2017-04-04 18:33:52 -07:00
Jason Ekstrand
82573d0f75 anv: Check for device loss at the end of WaitForFences
It's possible that the device could have been lost while we were
waiting.  We should let the user know if this has happened.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2017-04-04 18:33:51 -07:00
Jason Ekstrand
c6f69eea6a anv/pipeline: Properly handle unset gl_Layer and gl_ViewportIndex
When the shader does not set one of these values, they are supposed to
get a default value of 0.  We have hardware bits in 3DSTATE_CLIP for
this but haven't been setting them.  This fixes the intermittent failure
of dEQP-VK.geometry.layered.3d.render_to_default_layer.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Cc: "13.0 17.0" <mesa-stable@lists.freedesktop.org>
2017-04-04 18:33:51 -07:00
Jason Ekstrand
3503b2714b i965/fs: Always provide a default LOD of 0 for TXS and TXL
We already provide a default LOD for textureQueryLevels and texture() on
non-fragment stages.  However, there are more cases where one is needed
such as textureSize(gsampler2DMS*) in SPIR-V.  Instead of trying to list
out all of the cases one at a time, just provide the default for all TXS
and TXL operations.  This fixes a shader validation error in the new
Sascha deferredmultisampling demo which uses textureSize(gsampler2DMS).

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=100391
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
Cc: "13.0 17.0" <mesa-stable@lists.freedesktop.org>
2017-04-04 18:33:35 -07:00
Kenneth Graunke
c5bf7cb529 mesa: Require mipmap completeness for glCopyImageSubData(), sometimes.
This patch makes glCopyImageSubData require mipmap completeness when the
texture object's built-in sampler object has a mipmapping MinFilter.

Fixes (on i965):
dEQP-GLES31.functional.debug.negative_coverage.*.buffer.copy_image_sub_data

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
2017-04-04 17:35:18 -07:00
Vinson Lee
c161a10462 libgl-xlib: Link with libunwind.
Fix linking error.

  CXXLD    libGL.la
../../../../src/gallium/auxiliary/.libs/libgallium.a(u_debug_stack.o): In function `debug_backtrace_capture':
src/gallium/auxiliary/util/u_debug_stack.c:59: undefined reference to `_Ux86_64_getcontext'
src/gallium/auxiliary/util/u_debug_stack.c:60: undefined reference to `_ULx86_64_init_local'
src/gallium/auxiliary/util/u_debug_stack.c:62: undefined reference to `_ULx86_64_step'
src/gallium/auxiliary/util/u_debug_stack.c:71: undefined reference to `_ULx86_64_get_proc_info'
src/gallium/auxiliary/util/u_debug_stack.c:73: undefined reference to `_ULx86_64_get_proc_name'
src/gallium/auxiliary/util/u_debug_stack.c:65: undefined reference to `_ULx86_64_step'

Fixes: 70c272004f ("gallium/util: libunwind support")
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=100562
Signed-off-by: Vinson Lee <vlee@freedesktop.org>
Reviewed-by: Rob Clark <robdclark@gmail.com>
2017-04-04 16:47:41 -07:00
Jason Ekstrand
1fde054b8f intel/isl: Refactor and clerify gen8 alignment calculations
Adding the actual table from the docs makes it clearer exactly what the
restrictions are.  In particular, it becomes clear that compressed
textures ignore the alignment parameters in RENDER_SURFACE_STATE.

Reviewed-by: Chad Versace <chadversary@chromium.org>
2017-04-04 14:51:57 -07:00
Francisco Jerez
0de17f52a5 drirc: Set glsl_zero_init for Kerbal Space Program.
This fixes the stripes of garbage rendered on the floor of the vehicle
assembly building among other rendering issues.  The reason for the
misrendering seems to be that some of the GLSL shaders used by the
application use variables before initializing them, incorrectly
assuming that they will be implicitly set to zero by the
implementation.

Acked-by: Matt Turner <mattst88@gmail.com>
2017-04-04 14:13:03 -07:00
Lionel Landwerlin
e8d9b76f63 intel: tools: add aubinator_error_decode tool
This is pretty much the same tool as what i-g-t has, only with a more
fancy decoding of the instructions/registers. It also doesn't support
anything before gen4.

v2 (from Matt): Drop authors
                Remove undefined automake variable

v3: Fix incorrect offsets for dword > 1 (Jordan)

v4: Fix decompression error with large blobs (Jordan)

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Matt Turner <mattst88@gmail.com>
2017-04-04 21:22:26 +01:00
Lionel Landwerlin
567d77885e intel: genxml: add RING_BUFFER_CTL registers
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
2017-04-04 21:22:26 +01:00
Lionel Landwerlin
6f260ff049 intel: genxml: add FAULT_REG register
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
2017-04-04 21:22:26 +01:00
Lionel Landwerlin
ca2771fa18 intel: genxml: add gen7 ERR_INT register
v2: add register to gen7.5 (Matt)

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
2017-04-04 21:22:26 +01:00
Lionel Landwerlin
84613bf6d5 intel: genxml: add ACTHD registers
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
2017-04-04 21:22:26 +01:00
Lionel Landwerlin
0f195f22aa intel: genxml: add GFX_ARB_ERROR_RPT register
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
2017-04-04 21:22:26 +01:00