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i965/blorp: Align vertex buffers to 64B

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Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Cc: "13.0 17.0" <mesa-stable@lists.freedesktop.org>
This commit is contained in:
Jason Ekstrand 2017-03-31 15:23:35 -07:00
parent 5d1ba2cb04
commit f938354362
1 changed files with 13 additions and 1 deletions
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14
src/mesa/drivers/dri/i965/genX_blorp_exec.c
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@ -122,8 +122,20 @@ blorp_alloc_vertex_buffer(struct blorp_batch *batch, uint32_t size,
assert(batch->blorp->driver_ctx == batch->driver_batch);
struct brw_context *brw = batch->driver_batch;
/* From the Skylake PRM, 3DSTATE_VERTEX_BUFFERS:
*
* "The VF cache needs to be invalidated before binding and then using
* Vertex Buffers that overlap with any previously bound Vertex Buffer
* (at a 64B granularity) since the last invalidation. A VF cache
* invalidate is performed by setting the "VF Cache Invalidation Enable"
* bit in PIPE_CONTROL."
*
* This restriction first appears in the Skylake PRM but the internal docs
* also list it as being an issue on Broadwell. In order to avoid this
* problem, we align all vertex buffer allocations to 64 bytes.
*/
uint32_t offset;
void *data = brw_state_batch(brw, size, 32, &offset);
void *data = brw_state_batch(brw, size, 64, &offset);
*addr = (struct blorp_address) {
.buffer = brw->batch.bo,