Commit graph

69401 commits

Author SHA1 Message Date
Eric Anholt
e214a59635 vc4: Separate out a bit of code for submitting jobs to the kernel.
I want to be able to have multiple jobs being set up at the same time (for
example, a render job to do a little fixup blit in the course of doing a
render to the main FBO).
2015-04-13 23:20:45 -07:00
Eric Anholt
44b63cf5c0 vc4: When asked to sample from a raster texture, make a shadow tiled copy.
So, it turns out my simulator doesn't *quite* match the hardware.  And the
errata about raster textures tells you most of what's wrong, but there's
still stuff wrong after that.  Instead, if we're asked to sample from
raster, we'll just blit it to a tiled temporary.

Raster textures should only be screen scanout, and word is that it's
faster to copy to tiled using the tiling engine first than to texture from
an entire raster texture, anyway.
2015-04-13 22:34:06 -07:00
Eric Anholt
d04b07f8e2 vc4: Fix off-by-one in branch target validation. 2015-04-13 22:34:06 -07:00
Eric Anholt
7fa2f2e366 vc4: Use NIR-level lowering for idiv.
This fixes the idiv tests in piglit.
2015-04-13 21:36:40 -07:00
Eric Anholt
84ebaff1b7 vc4: Add a bunch of type conversions.
These are required to get piglit's idiv tests working.  The
unsigned<->float conversions are wrong, but are good enough to get
piglit's small ranges of values working.
2015-04-13 21:36:40 -07:00
Dave Airlie
cc5860e407 st/mesa: align cube map arrays layers
We create textures internally for texsubimage, and we use
the values from sub image to create a new texture, however
we don't align these to valid sizes, and cube map arrays
must have an array size aligned to 6.

This fixes texsubimage cube_map_array on CAYMAN at least,
(it was causing  GPU hang and bad values), it probably
also fixes it on radeonsi and evergreen.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=89957
Tested-by: Tom Stellard <thomas.stellard@amd.com>
Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2015-04-14 08:04:41 +10:00
Dave Airlie
5ed79312ed st/mesa: convert sub image for cube map arrays to 2d arrays for upload
Since we can subimage upload a number of cube map array layers,
that aren't a complete cube map array, we should specify things
as a 2D array and blit from that.

Suggested by Ilia Mirkin as an alternate fix for texsubimage
cube map array issues.

seems to work just as well.

Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2015-04-14 08:04:21 +10:00
Mathias Froehlich
1e1d5456ba i965: Flush batchbuffer containing the query on glQueryCounter.
This change fixes a regression with timer queries introduced with
commit 3eb6258. There the pending batchbuffer is flushed
only if glEndQuery is executed. This present change adds such
a flush to glQueryCounter which also schedules a value query
just like glEndQuery does. The patch fixes GPU timer queries
going mad from within osgviewer.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Mathias Froehlich <Mathias.Froehlich@web.de>
Cc: mesa-stable@lists.freedesktop.org
2015-04-13 20:30:23 +02:00
Eric Anholt
adae027260 vc4: Use the blit interface for updating shadow textures.
This lets us plug in a better blit implementation and have it impact the
shadow update, too.
2015-04-13 10:39:24 -07:00
Eric Anholt
39b6f7e76c vc4: Remove dead fields from vc4_surface. 2015-04-13 10:39:24 -07:00
Eric Anholt
5100221ff7 vc4: Skip sending down the clear colors if not clearing. 2015-04-13 10:39:24 -07:00
Eric Anholt
725620f21d vc4: Sync with kernel changes to relax BCL versus RCL validation.
There was no reason to tie the two packets' values together.
2015-04-13 10:39:23 -07:00
Eric Anholt
cb88d2cfcb vc4: Fix another space allocation mistake.
We're over-allocating our BCL in vc4_draw.c, so this never mattered.
However, new RCL-only blit support might end up here without having set up
any BCL contents.
2015-04-13 10:39:02 -07:00
Eric Anholt
8eb9304ee7 vc4: Add missed accounting for the size of the semaphore.
This wouldn't have mattered except in the worst case scenario RCL setup.
2015-04-13 10:33:30 -07:00
Matt Turner
89b140dfae swrast: Mark MAX_GLUINT literal with u suffix.
Coverity is confused by the "float < int / 2" expression and suggests
casting MAX_GLUINT to unsigned, which I believe it was supposed to have
been already.

Reviewed-by: Brian Paul <brianp@vmware.com>
2015-04-13 09:03:02 -07:00
Matt Turner
1c9db39d54 i965: Don't bother freeing NULL.
Commit e16c5c90 was replacing 'region' with 'mt', leaving this
nonsensical code.

Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
2015-04-13 09:03:02 -07:00
Chad Versace
a76dc15b2b i965: Lift some restrictions on dma_buf EGLImages
Allow glEGLImageTargetRenderbufferStorageOES and
glEGLImageTargetTexture2DOES for dma_buf EGLImages if the image is
a single RGBA8 unorm plane. This is safe, despite fast color clears,
because i965 disables allocation of auxiliary buffers for EGLImages.

Chrome OS needs this, because its compositor uses dma_buf EGLImages for
its scanout buffers.

Testing:
  - Tested on Ivybridge Chromebook Pixel with WebGL Aquarium and
    YouTube.
  - No Piglit regressions on Broadwell with `piglit run -p gbm
    tests/quick.py`, with my Piglit patches that update the
    EGL_EXT_image_dma_buf_import tests.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
2015-04-13 07:36:32 -07:00
Chad Versace
2943b15ce7 i965: Disable aux buffers for EGLImage-backed miptrees
EGL does not yet have extensions to manage the flushing and invalidating
of driver-internal aux buffers. So we must disable aux buffers of
dma_buf-backed EGLImages in order to safely render into them.

This patch is obviously needed for renderbufers. It's also needed for
textures because the user can attach the texture to a framebuffer and
because the driver sometimes renders to textures for internal reasons.

Testing:
  - Tested on Ivybridge Chromebook Pixel with WebGL Aquarium and
    YouTube.
  - No Piglit regressions on Broadwell with `piglit run -p gbm
    tests/quick.py`.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
2015-04-13 07:36:32 -07:00
Chad Versace
bf504b6127 i965: Change intel_miptree_create_for_bo() signature
Add parameter 'bool disable_aux_buffers'.

This is a refactor patch. The patch changes no behavior because the new
parameter is false in every call.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
2015-04-13 07:36:32 -07:00
Chad Versace
d3b042f359 i965: Add field intel_mipmap_tree::disable_aux_buffers
The new field disables allocation of auxiliary buffers, such as the HiZ
buffer and MCS buffer. This is useful for sharing the miptree bo with an
external client that doesn't understand auxiliary buffers.

We need this field to safely render to a buffer that was imported with
EGL_EXT_image_dma_buf_import, because EGL does not yet have extensions
to manage flushing and invalidating auxiliary buffers.

Nothing yet enables this field. That's left to follow-up patches.

Testing:
  - Tested on Ivybridge Chromebook Pixel with WebGL Aquarium and
    YouTube.
  - No Piglit regressions on Broadwell with `piglit run -p gbm
    tests/quick.py`.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
2015-04-13 07:36:29 -07:00
Chad Versace
e1338f267f i965: Refactor brw_is_hiz_depth_format()
Every caller of this function uses it to determine if the current
miptree needs a hiz buffer to be allocated. Strangely, the function
doesn't take a miptree argument. So, this function effectively decides
if and when a miptree's hiz buffer gets allocated without inspecting the
miptree itself.  Luckily, the driver behaves correctly despite the
brw_is_hiz_depth_format's quirk.

I will soon make some changes to the miptree that will require
inspecting the miptree to determine if it needs a hiz buffer. So this
patch renames
    brw_is_hiz_depth_format -> intel_miptree_wants_hiz_buffer
and gives it a miptree parameter.

This patch shouldn't change any behavior.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
2015-04-13 07:32:02 -07:00
Chad Versace
5776d65114 i965: Declare intel_miptree_create_layout() as static
It's not used outside intel_mipmap_tree.c.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
2015-04-13 07:32:02 -07:00
Chad Versace
1ef4bf7191 i965: Declare intel_miptree_alloc_mcs() as static
It's not used outside of intel_mipmap_tree.c, nor should it ever be.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
2015-04-13 07:32:02 -07:00
Jose Fonseca
36ceda4ece docs: Improve LLVM_USE_CRT_xxx instructions. 2015-04-13 13:08:13 +01:00
Jose Fonseca
fa1b3e1501 glx: Include util/macros.h instead of redefining PRINTFLIKE.
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
2015-04-13 12:03:33 +01:00
Jose Fonseca
978753e843 util/ralloc: Fix extern "C" usage.
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2015-04-13 12:03:26 +01:00
Jose Fonseca
85dd46d90c mesa: Remove pointless USE_EXTERNAL_DXTN_LIB macro.
I'm not sure what was the original intention, but currently
USE_EXTERNAL_DXTN_LIB always ends up defined, one way or another.

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
2015-04-13 12:02:52 +01:00
Emil Velikov
5ddeab8a06 docs: add news item and link release notes for mesa 10.5.3
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
2015-04-12 23:16:42 +01:00
Emil Velikov
a94f8e712f docs: Add 256 sums for the 10.5.3 release
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
(cherry picked from commit 65776421fe)
2015-04-12 23:14:31 +01:00
Emil Velikov
794b9bf26a Add release notes for the 10.5.3 release
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
(cherry picked from commit c4b8bff6e2)
2015-04-12 23:14:28 +01:00
Emil Velikov
61c6cc4a4a docs: remove the --with-max-{width,height} note
Missed out with commit d99135b2e9b(configure: nuke
--with-max-{width,height})

Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
2015-04-12 23:14:07 +01:00
Emil Velikov
0e742b1cb3 configure.ac: remove deprecated --with-libclc-path
The option was deprecated with commit 959e83d6507(clover: Adapt libclc's
INCLUDEDIR and LIBEXECDIR to make use of the new introduced libclc.pc.)
back in 2012 with mesa 9.2.

Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
2015-04-12 23:12:03 +01:00
Kenneth Graunke
b6354d9bb0 i965/nir: Make INTEL_DEBUG=ann work with NIR.
Now that we store a copy of the NIR shader, and don't immediately free
it, we can use it in annotations as well.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
2015-04-11 12:35:47 -07:00
Kenneth Graunke
89c1feb78d i965: Create NIR during LinkShader() and ProgramStringNotify().
Previously, we translated into NIR and did all the optimizations and
lowering as part of running fs_visitor.  This meant that we did all of
that work twice for fragment shaders - once for SIMD8, and again for
SIMD16.  We also had to redo it every time we hit a state based
recompile.

We now generate NIR once at link time.  ARB programs don't have linking,
so we instead generate it at ProgramStringNotify time.

Mesa's fixed function vertex program handling doesn't bother to inform
the driver about new programs at all (which is rather mean), so we
generate NIR at the last minute, if it hasn't happened already.

shader-db runs ~9.4% faster on my i7-5600U, with a release build.

v2: Check NirOptions != NULL in ProgramStringNotify().  Don't bother
    using _mesa_program_enum_to_shader_stage as we already know it.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
2015-04-11 12:35:33 -07:00
Kenneth Graunke
b3e286c457 nir: Store num_direct_uniforms in the nir_shader.
Storing this here is pretty sketchy - I don't know if any driver other
than i965 will want to use it.  But this will make it a lot easier to
generate NIR code at link time.  We'll probably rework it anyway.

(Ian suggested making nir_assign_var_locations_scalar_direct_first
 simply modify the nir_shader's fields, rather than passing pointers
 to them.  If this stays long term, we should do that.  But Jason and
 I suspect we'll be reworking this area again in the near future.)

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
2015-04-11 11:39:48 -07:00
Kenneth Graunke
f41f07f685 i965: Move lower_output_reads to brw_link_shader().
This makes it so emit_nir_code() doesn't modify the GLSL IR.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
2015-04-11 11:38:14 -07:00
Matt Turner
8e414cbdec glsl: Mark path as unreachable. 2015-04-11 10:23:05 -07:00
Matt Turner
ea0c35faf8 i965: Remove useless null check.
If it were null, we'd have just derefernced it two lines above.
2015-04-11 09:59:47 -07:00
Matt Turner
024ecc783b i965/fs/nir: Mark fallthrough. 2015-04-11 09:59:47 -07:00
Matt Turner
1ac230975e i965: Remove useless reg_offset >= 0 tests.
Commit eb9bd3a1 changed the type of this field to uint16_t.
2015-04-11 09:59:46 -07:00
Rob Clark
b98c0262d1 freedreno/ir3/nir: couple little fixes
Signed-off-by: Rob Clark <robclark@freedesktop.org>
2015-04-11 11:41:03 -04:00
Rob Clark
1b936bb9f8 freedreno/ir3/nir: handle system values
Signed-off-by: Rob Clark <robclark@freedesktop.org>
2015-04-11 11:40:57 -04:00
Rob Clark
715b2e0dbb freedreno/ir3/nir: handle txs and query_levels tex ops
These correspond to the tgsi TXQ opcode

(plus sneak in a fix for two-sided color)

Signed-off-by: Rob Clark <robclark@freedesktop.org>
2015-04-11 11:40:43 -04:00
Rob Clark
97e8fc3fdd freedreno/ir3/nir: split out tex helpers
We'll need these in one or two other spots.

Signed-off-by: Rob Clark <robclark@freedesktop.org>
2015-04-11 11:40:36 -04:00
Rob Clark
6e8160d6e3 freedreno/ir3/nir: simplify emit_tex()
Just build up arrays for src0/src1, and use create_collect()..

Also add back missing .3d flag for 3d/cube textures.

Signed-off-by: Rob Clark <robclark@freedesktop.org>
2015-04-11 11:40:28 -04:00
Rob Clark
d5357c16cc freedreno/ir3/cp: handle indirect properly
I noticed some cases where we where trying to copy-propagate indirect
src's into places they cannot go, like 2nd src for cat3 (mad, etc).
Expand out valid_flags() to be aware of relativ flag, and fix up a few
related spots.

Signed-off-by: Rob Clark <robclark@freedesktop.org>
2015-04-11 11:40:21 -04:00
Rob Clark
49be76166b freedreno/ir3/sched: avoid getting stuck on addr conflicts
When we get in a scenario where we cannot schedule any more instructions
due to address register conflict, clone the instruction that writes the
address register, and switch the remaining unscheduled users for the
current address register over to the new clone.

This is simpler and more robust than the previous attempt (which tried
and sometimes failed to ensure all other dependencies of users of the
address register were scheduled first).. hint it would try to schedule
instructions that were not actually needed for any output value.

We probably need to do the same with predicate register, although so far
it isn't so heavily used so we aren't running into problems with it
(yet).

Signed-off-by: Rob Clark <robclark@freedesktop.org>
2015-04-11 11:40:15 -04:00
Rob Clark
4cf4006674 freedreno/ir3/nir: add variable-indexing support
A bit fugly.. try and make this cleaner..  note if we hoist all the
get_addr() out of the loop we can drop the hashtable and just use
create_addr()..

Signed-off-by: Rob Clark <robclark@freedesktop.org>
2015-04-11 11:40:09 -04:00
Rob Clark
972ce757d7 freedreno/ir3/asm: change assert to warning
It probably *should* be an assert, but for now TGSI f/e isn't very good
about dealing w/ CONST vs ABS/NEG.  So for debug builds, print a warning
instead of crashing with an assert for now.

Signed-off-by: Rob Clark <robclark@freedesktop.org>
2015-04-11 11:40:03 -04:00
Rob Clark
09cbd97a47 freedreno/ir3/nir: set first_driver_param
Without this, a3xx breaks.. a4xx would too if it had already implemented
support for passing driver params.

Signed-off-by: Rob Clark <robclark@freedesktop.org>
2015-04-11 11:39:56 -04:00