Commit graph

150743 commits

Author SHA1 Message Date
Andrii Simiklit
ddf2778269 glsl: add member's location layout qualifier rules for arrayed in/out blocks
From Section 4.4.1 (Input Layout Qualifiers) of the GLSL 4.50 spec:

     "For some blocks declared as arrays, the location can only be applied
     at the block level: When a block is declared as an array where
     additional locations are needed for each member for each block array
     element, it is a compile-time error to specify locations on the block
     members. That is, when locations would be under specified by applying
     them on block members, they are not allowed on block members. For
     arrayed interfaces (those generally having an extra level of
     arrayness due to interface expansion), the outer array is stripped
     before applying this rule"

From Section 1.2.1 (Changes from Revision 6 of GLSL Version) of the GLSL 4.50 spec:

     "Private Bug 15678: Don’t allow location = on block members where
      the block needs an array of locations"

From Section 4.4.1 (Input Layout Qualifiers) of the GLSL ES 3.20 spec

     "If an input is declared as an array of blocks, excluding per-vertex-arrays
      as required for tessellation, it is an error to declare a member of
      the block with a location qualifier"

From Section 1.1.3 (Changes from GLSL ES 3.2 revision 3) of the GLSL ES 3.20 spec:

     "Arrayed blocks cannot have layout location qualifiers on members"

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Signed-off-by: Andrii Simiklit <andrii.simiklit@globallogic.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11522>
2022-03-03 05:42:45 +00:00
Mike Blumenkrantz
0313110c92 zink: ci updates
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15227>
2022-03-03 05:21:40 +00:00
Mike Blumenkrantz
712ce86bd1 zink: split primitives generated queries if xfb/gs states change
if one of these states change then it affects which result needs to be
used for that query, so split it up over multiple query ids to make sure
the correct result is obtained

fixes (lavapipe):
GTF-GL46.gtf40.GL3Tests.transform_feedback2.transform_feedback2_pause_resume
GTF-GL46.gtf40.GL3Tests.transform_feedback2.transform_feedback2_states

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15227>
2022-03-03 05:21:40 +00:00
Mike Blumenkrantz
0cb3ae949c zink: split out query suspending into util function
no functional changes

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15227>
2022-03-03 05:21:40 +00:00
Mike Blumenkrantz
5aecec48ee zink: update query states before starting renderpass during draw
this gives some leeway for doing transfer ops without crashing the renderpass

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15227>
2022-03-03 05:21:40 +00:00
Ilia Mirkin
965ab44c50 nvc0: disable EXT_texture_sRGB_RG8
Looks like the green component doesn't get srgb-decoding, and no obvious
way to force it. It works fine on nv50 though.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15211>
2022-03-03 04:37:12 +00:00
Ilia Mirkin
897a7fbbf1 mesa: enable GL_EXT_texture_sRGB_RG8 on desktop
Looks like an extension number was assigned in late 2020. This makes it
possible to hook up this format to teximage-colors without teaching it
about ES.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15211>
2022-03-03 04:37:12 +00:00
Mike Blumenkrantz
af5f49f663 zink: remove loop from generated tcs
this is already using per-vertex io, no need to add conditionals to verify

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15225>
2022-03-03 02:58:43 +00:00
Rob Clark
7e63fa2bb1 freedreno/registers: Add a couple regs we need for kernel
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15221>
2022-03-03 02:19:47 +00:00
Dave Airlie
34379a937f gallivm/llvmpipe: add support for NIR to the linear/aos paths.
When the AOS/linear code was added it only worked with TGSI which
meant nothing in mesa upstream was really using it.

This adds support to analyse NIR shaders, and adds aos support
to the backend.

AOS support is limited to mov,vec,fmul,tex sampling in order to
accelerate mostly compositing operations. I've tested weston uses
the fast path. gnome-shell can't use it yet as we can't optimise
the depth test paths.

Acked-by: Jose Fonseca <jfonseca@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15140>
2022-03-03 01:39:39 +00:00
Dave Airlie
6efd489ac9 gallivm/nir: split load_const out into backend helper.
This just makes adding aos support easier.

Acked-by: Jose Fonseca <jfonseca@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15140>
2022-03-03 01:39:39 +00:00
Dave Airlie
65c7ca617f llvmpipe/linear: fix disk caching.
Acked-by: Jose Fonseca <jfonseca@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15140>
2022-03-03 01:39:39 +00:00
Mike Blumenkrantz
503362f008 zink: switch to u_foreach_bit for ntv image access decorations
no functional changes

Reviewed-by: Jason Ekstrand <jason.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15217>
2022-03-03 01:28:13 +00:00
Mike Blumenkrantz
fcdcfd9967 zink: emit Aliased decorations for any image that isn't explicitly marked restrict
these might be aliased

fixes:
arb_shader_image_load_store-restrict

fixes #6090

Reviewed-by: Jason Ekstrand <jason.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15217>
2022-03-03 01:28:13 +00:00
Mike Blumenkrantz
351378ae80 zink: remove a bunch of flakes
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15219>
2022-03-03 01:14:20 +00:00
Dave Airlie
e1e9a44a69 lavapipe: always set read/write on ssbo/images.
This fixes a regressions with overlap in llvmpipe, this is pessimistic
we should write code to make it work properly.

Acked-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15219>
2022-03-03 01:14:20 +00:00
Alyssa Rosenzweig
b48236ea3e pan/bi: Add arithmetic flag to RSHIFT ops
Models ops like ARSHIFT_OR.i32 on Valhall without adding piles of new
instructions to the IR.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15216>
2022-03-03 00:41:44 +00:00
Alyssa Rosenzweig
0b0e74ae82 pan/bi: Extend LD_TILE with a register format
Required for Valhall. NIR has the information anyway, pass it along.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15216>
2022-03-03 00:41:44 +00:00
Alyssa Rosenzweig
74107abfc6 pan/bi: Add BRANCHZI instruction
Technically this is just JUMP on Valhall, but the semantic is an indirect branch
based on comparing with zero. It can also be used as a conservative branch (like
BRANCHC), but this isn't modeled.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15216>
2022-03-03 00:41:44 +00:00
Alyssa Rosenzweig
3dc2095b07 pan/bi: Model LD_BUFFER instructions
We'll use these to read from UBOs on Valhall.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15216>
2022-03-03 00:41:44 +00:00
Alyssa Rosenzweig
5796777889 pan/bi: Model offset for LOAD/STORE
Needed to model the immediate offset on Valhall.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15216>
2022-03-03 00:41:43 +00:00
Alyssa Rosenzweig
039bb4e68c pan/bi: Model pos/vary segments in STORE instructions
For Bifrost, we model load/store segments, for example for thread local storage.
We need something similar on Valhall -- access modifiers. There are four access
modifiers on Valhall, controlling memory subsystem optimizations for the access:

none: Nothing may be assumed. Corresponds to "global".

istream: Internally streaming within the GPU. Corresponds to "pos", as it's
used for position stores.

estream: Externally streaming outside the GPU. Corresponds to "vary", as it's
used for varying stores.

force: Force access in discarded threads. Corresponds to "tl", as it's required
for correct behaviour of helper invocations that use the stack.

If these access modifiers end up being useful outside these fixed purposes, we
may need to rework this part of the IR. For now, this should suffice.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15216>
2022-03-03 00:41:43 +00:00
Alyssa Rosenzweig
aaa39f0e60 pan/bi: Model LEA_BUF_IMM in the IR
Required for varying stores in malloced IDVS jobs on Valhall.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15216>
2022-03-03 00:41:43 +00:00
Alyssa Rosenzweig
eba9ef4c25 pan/bi: Add LD_VAR_BUF_IMM.f16/f32 instructions
For use on Valhall with memory-allocated IDVS jobs.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15216>
2022-03-03 00:41:43 +00:00
Alyssa Rosenzweig
48a398bf5b pan/bi: Generalize I->table for Valhall
Can be reused for resource tables in a natural way.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15216>
2022-03-03 00:41:43 +00:00
Alyssa Rosenzweig
20891e75c2 pan/bi: Extend BLEND to take a register format
Needed on Valhall.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15216>
2022-03-03 00:41:43 +00:00
Alyssa Rosenzweig
3c817ed511 pan/bi: Model Valhall texture instructions
These act like a TEXC+immediate.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15216>
2022-03-03 00:41:43 +00:00
Alyssa Rosenzweig
234d3efb9b pan/va: Add memory access modifier to LOADs
Might be required for correct spilling in some circumstances.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15216>
2022-03-03 00:41:43 +00:00
Alyssa Rosenzweig
79aa4af078 pan/va: Remap "store segment" to "memory access"
For now, the difference does not matter. However it's better to model the actual
hardware behaviour, rather than isomorphic driver behaviour, when we can do so.
So fix the names.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15216>
2022-03-03 00:41:43 +00:00
Alyssa Rosenzweig
254a641290 pan/va: Fix LEA_BUF_IMM definition
Technically the table is folded, too; the 0xD refers to table 61. But this
instruction is more general than previously thought.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15216>
2022-03-03 00:41:43 +00:00
Alyssa Rosenzweig
7c798fbb9f pan/va: Fix definitions of LD_VAR_BUF_IMM
So close! However, LD_VAR_IMM is something else -- Bifrost-style varying
interpolation, without a hardware buffer. For ES3, we'll need to support both.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15216>
2022-03-03 00:41:43 +00:00
Alyssa Rosenzweig
c62836661e pan/va: Add TEX_GATHER instruction
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15216>
2022-03-03 00:41:43 +00:00
Alyssa Rosenzweig
65cb3af38a pan/va: Add TEX_DUAL instruction
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15216>
2022-03-03 00:41:43 +00:00
Alyssa Rosenzweig
47b70ca584 pan/va: Add modifiers required for gathers
Mostly isomorphic to Bifrost-style gathers.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15216>
2022-03-03 00:41:43 +00:00
Alyssa Rosenzweig
431e7e54a6 pan/va: Handle force_enum differing from name
Needed for secondary register width, for dual texturing.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15216>
2022-03-03 00:41:43 +00:00
Ian Romanick
0a6c6dcb00 i915g: Emit better code for SEQ(x, 0) and SNE(x, 0)
total instructions in shared programs: 789000 -> 788481 (-0.07%)
instructions in affected programs: 16179 -> 15660 (-3.21%)
helped: 157
HURT: 0
helped stats (abs) min: 3 max: 12 x̄: 3.31 x̃: 3
helped stats (rel) min: 1.56% max: 14.29% x̄: 4.24% x̃: 2.56%
95% mean confidence interval for instructions value: -3.51 -3.10
95% mean confidence interval for instructions %-change: -4.70% -3.78%
Instructions are helped.

LOST:   0
GAINED: 3

v2: Drop setting src1 to zero.  Suggested by Emma.

Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15210>
2022-03-03 00:07:58 +00:00
Ian Romanick
374da6fc41 i915g: Handle constants composed exclusively of 0 or ±1 specially
This can avoid some cases where a constant has to be loaded into a
temporary register.

v2: Update i915-g33-fails.txt.

total instructions in shared programs: 788625 -> 782376 (-0.79%)
instructions in affected programs: 166269 -> 160020 (-3.76%)
helped: 1578
HURT: 0
helped stats (abs) min: 3 max: 21 x̄: 3.96 x̃: 3
helped stats (rel) min: 1.56% max: 33.33% x̄: 4.82% x̃: 3.45%
95% mean confidence interval for instructions value: -4.06 -3.86
95% mean confidence interval for instructions %-change: -5.00% -4.64%
Instructions are helped.

LOST:   0
GAINED: 35

Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15210>
2022-03-03 00:07:58 +00:00
Ian Romanick
06eb9fb125 nir/algebraic: Optimize some cases of (sXX(a, b) != 0.0)
I noticed the SGE case while looking at the output of
shaders/closed/steam/trine-2/fp-3.shader_test on i915g.  These are
especially bad on i915 that needs two instructions to implement SNE.

An alternative would be to duplicate the sne(sXX(a, b), 0.0) rules in an
algebraic pass that occurs after bool_to_float.  Doing the work earlier
seems preferable.

i915
total instructions in shared programs: 788274 -> 788223 (<.01%)
instructions in affected programs: 666 -> 615 (-7.66%)
helped: 5
HURT: 0
helped stats (abs) min: 9 max: 12 x̄: 10.20 x̃: 9
helped stats (rel) min: 5.00% max: 11.11% x̄: 8.12% x̃: 8.16%
95% mean confidence interval for instructions value: -12.24 -8.16
95% mean confidence interval for instructions %-change: -10.81% -5.43%
Instructions are helped.

LOST:   0
GAINED: 2

The two gained shaders are assembly fragment programs in Euro Truck
Simulator 2.

Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15210>
2022-03-03 00:07:58 +00:00
Ian Romanick
7d055c93e0 i915g/ci: update piglit fails
I believe these were fixed by !14573.

Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15210>
2022-03-03 00:07:58 +00:00
Emma Anholt
d506d910e4 nir: Switch to using nir_vec_scalars() for things that used nir_channel().
This should reduce follow-on optimization work to copy-propagate and
dead-code away the movs generated in construction of vectors.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14865>
2022-03-02 22:28:58 +00:00
Emma Anholt
16c064dfaf nir: Add a helper for setting up a nir_ssa_scalar struct.
Trivial, but will help users avoid some struct constructions that can be
awkward in C.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14865>
2022-03-02 22:28:58 +00:00
Emma Anholt
d95f9d189a nir: Introduce a nir_vec_scalars() helper using nir_ssa_scalar.
Many users of nir_vec() do so by nir_channel()-ing a new ssa defs as movs
from other vectors to put the new vector together, which then just have to
get copy-propagated into the ALU srcs and DCEed away the temporary movs.
If they instead take nir_ssa_scalar, we can avoid that extra work.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14865>
2022-03-02 22:28:58 +00:00
Dave Airlie
48b3ef625e vulkan/wsi: handle queue families properly for non-concurrent sharing mode.
"queueFamilyIndexCount is the number of queue families having access to the image(s) of the
swapchain when imageSharingMode is VK_SHARING_MODE_CONCURRENT.
pQueueFamilyIndices is a pointer to an array of queue family indices having access to the
images(s) of the swapchain when imageSharingMode is VK_SHARING_MODE_CONCURRENT."

If the type isn't concurrent, don't attempt to access the arrays.

dEQP-VK.wsi.xlib.swapchain.create.exclusive_nonzero_queues on lavapipe.

Fixes: 5b13d74583 ("vulkan/wsi/drm: Break create_native_image in pieces")
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15101>
2022-03-02 20:47:16 +00:00
Emma Anholt
221ce1b35a ci/freedreno: Consolidate some information about an a630 flake.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15197>
2022-03-02 19:53:26 +00:00
Emma Anholt
a64408dcd5 ir3: Don't assert on not finding the VS output for an FS input.
It should return undefined data, not terminate the program.  Fixes some
piglit tests poking at the UB handling.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15197>
2022-03-02 19:53:26 +00:00
Rhys Perry
feb7e30e2d radv: include disable_aniso_single_level and adjust_frag_coord_z in key
Fixes potential pipeline caching bug.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15175>
2022-03-02 19:05:28 +00:00
Emma Anholt
2de15273d5 freedreno: Improve robustness behavior for VBs with offset > size.
We were just emitting the bad reloc (either an assert fail on a debug
build or for a release build likely a GPU hang from the resulting fault).
Given that the GLES 3.2 spec's robust context requirement says we should
return undefined data but not terminate for element indices outside of the
VB, ignoring the offset in this case seems like a better behavior to have
in all cases.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15198>
2022-03-02 17:31:49 +00:00
Emma Anholt
92945825f5 freedreno: Fix start_slot handling in set_vertex_buffers.
mesa/st only ever provides a 0 for this value, but let's be ready if it
ever does something else.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15198>
2022-03-02 17:31:49 +00:00
Emma Anholt
35ddb65ea6 freedreno: Use the resource size rather than BO size for VFD_FETCH[].SIZE.
We should be using the API size to clamp, rather than what we allocated
the BO into.

Fixes: #13
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15198>
2022-03-02 17:31:49 +00:00
Erik Faye-Lund
b21e7e1ef7 docs: match build-flags markup with meson docs
In meson.rst, we document build-flags with double backticks, which puts
it inside a code-tag in the rendered HTML instead of a cite-tag like we
currently do.

Acked-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15213>
2022-03-02 14:36:42 +00:00