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pan/bi: Model offset for LOAD/STORE
Needed to model the immediate offset on Valhall. Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15216>
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039bb4e68c
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5796777889
5 changed files with 25 additions and 7 deletions
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@ -7085,6 +7085,7 @@
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<reserved/>
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<opt>tl</opt>
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</mod>
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<immediate name="byte_offset" size="16" pseudo="true"/>
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</ins>
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<ins name="+LOAD.i16" staging="w=1" message="load">
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@ -7144,6 +7145,7 @@
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<eq left="extend" right="#zext"/>
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</derived>
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</encoding>
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<immediate name="byte_offset" size="16" pseudo="true"/>
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</ins>
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<ins name="+LOAD.i24" staging="w=1" mask="0xffe00" exact="0x65000" message="load">
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@ -7159,6 +7161,7 @@
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<reserved/>
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<opt>tl</opt>
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</mod>
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<immediate name="byte_offset" size="16" pseudo="true"/>
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</ins>
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<ins name="+LOAD.i32" staging="w=1" message="load">
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@ -7196,6 +7199,7 @@
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<eq left="extend" right="#zext"/>
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</derived>
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</encoding>
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<immediate name="byte_offset" size="16" pseudo="true"/>
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</ins>
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<ins name="+LOAD.i48" staging="w=2" mask="0xffe00" exact="0x65200" message="load">
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@ -7211,6 +7215,7 @@
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<reserved/>
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<opt>tl</opt>
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</mod>
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<immediate name="byte_offset" size="16" pseudo="true"/>
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</ins>
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<ins name="+LOAD.i64" staging="w=2" mask="0xffe00" exact="0x60e00" message="load">
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@ -7226,6 +7231,7 @@
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<reserved/>
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<opt>tl</opt>
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</mod>
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<immediate name="byte_offset" size="16" pseudo="true"/>
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</ins>
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<ins name="+LOAD.i8" staging="w=1" message="load">
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@ -7310,6 +7316,7 @@
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<eq left="extend" right="#zext"/>
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</derived>
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</encoding>
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<immediate name="byte_offset" size="16" pseudo="true"/>
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</ins>
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<ins name="+LOAD.i96" staging="w=3" mask="0xffe00" exact="0x65400" message="load">
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@ -7325,6 +7332,7 @@
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<reserved/>
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<opt>tl</opt>
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</mod>
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<immediate name="byte_offset" size="16" pseudo="true"/>
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</ins>
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<ins name="+LOGB.f32" mask="0xfffe0" exact="0x3d9a0">
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@ -7539,6 +7547,7 @@
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<reserved/>
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<opt>tl</opt>
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</mod>
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<immediate name="byte_offset" size="16" pseudo="true"/>
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</ins>
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<ins name="+STORE.i16" staging="r=1" mask="0xffe00" exact="0x62800" message="store" dests="0">
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@ -7554,6 +7563,7 @@
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<reserved/>
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<opt>tl</opt>
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</mod>
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<immediate name="byte_offset" size="16" pseudo="true"/>
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</ins>
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<ins name="+STORE.i24" staging="r=1" mask="0xffe00" exact="0x65800" message="store" dests="0">
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@ -7569,6 +7579,7 @@
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<reserved/>
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<opt>tl</opt>
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</mod>
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<immediate name="byte_offset" size="16" pseudo="true"/>
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</ins>
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<ins name="+STORE.i32" staging="r=1" mask="0xffe00" exact="0x62c00" message="store" dests="0">
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@ -7584,6 +7595,7 @@
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<reserved/>
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<opt>tl</opt>
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</mod>
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<immediate name="byte_offset" size="16" pseudo="true"/>
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</ins>
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<ins name="+STORE.i48" staging="r=2" mask="0xffe00" exact="0x65a00" message="store" dests="0">
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@ -7599,6 +7611,7 @@
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<reserved/>
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<opt>tl</opt>
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</mod>
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<immediate name="byte_offset" size="16" pseudo="true"/>
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</ins>
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<ins name="+STORE.i64" staging="r=2" mask="0xffe00" exact="0x62e00" message="store" dests="0">
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@ -7614,6 +7627,7 @@
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<reserved/>
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<opt>tl</opt>
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</mod>
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<immediate name="byte_offset" size="16" pseudo="true"/>
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</ins>
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<ins name="+STORE.i8" staging="r=1" mask="0xffe00" exact="0x62000" message="store" dests="0">
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@ -7629,6 +7643,7 @@
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<reserved/>
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<opt>tl</opt>
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</mod>
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<immediate name="byte_offset" size="16" pseudo="true"/>
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</ins>
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<ins name="+STORE.i96" staging="r=3" mask="0xffe00" exact="0x65c00" message="store" dests="0">
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@ -7644,6 +7659,7 @@
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<reserved/>
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<opt>tl</opt>
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</mod>
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<immediate name="byte_offset" size="16" pseudo="true"/>
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</ins>
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<ins name="+ST_CVT" staging="r=format" mask="0xff800" exact="0xc9800" message="store" dests="0">
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@ -492,7 +492,7 @@ bi_spill_register(bi_context *ctx, bi_index index, uint32_t offset)
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b.cursor = bi_after_instr(I);
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bi_index loc = bi_imm_u32(offset + 4 * extra);
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bi_store(&b, bits, tmp, loc, bi_zero(), BI_SEG_TL);
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bi_store(&b, bits, tmp, loc, bi_zero(), BI_SEG_TL, 0);
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ctx->spills++;
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channels = MAX2(channels, extra + count);
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@ -506,7 +506,8 @@ bi_spill_register(bi_context *ctx, bi_index index, uint32_t offset)
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bi_rewrite_index_src_single(I, index, tmp);
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bi_instr *ld = bi_load_to(&b, bits, tmp,
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bi_imm_u32(offset), bi_zero(), BI_SEG_TL);
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bi_imm_u32(offset), bi_zero(), BI_SEG_TL,
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0);
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ld->no_spill = true;
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ctx->fills++;
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}
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@ -423,7 +423,7 @@ bi_load_sysval_to(bi_builder *b, bi_index dest, int sysval,
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return bi_load_to(b, nr_components * 32, dest,
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bi_imm_u32(idx),
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bi_imm_u32(sysval_ubo), BI_SEG_UBO);
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bi_imm_u32(sysval_ubo), BI_SEG_UBO, 0);
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}
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static void
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@ -792,7 +792,7 @@ bi_emit_load_ubo(bi_builder *b, nir_intrinsic_instr *instr)
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bi_dest_index(&instr->dest), offset_is_const ?
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bi_imm_u32(const_offset) : dyn_offset,
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kernel_input ? bi_zero() : bi_src_index(&instr->src[0]),
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BI_SEG_UBO);
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BI_SEG_UBO, 0);
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}
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static bi_index
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@ -808,7 +808,7 @@ bi_emit_load(bi_builder *b, nir_intrinsic_instr *instr, enum bi_seg seg)
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bi_load_to(b, instr->num_components * nir_dest_bit_size(instr->dest),
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bi_dest_index(&instr->dest),
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bi_src_index(&instr->src[0]), bi_addr_high(&instr->src[0]),
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seg);
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seg, 0);
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}
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static void
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@ -821,7 +821,7 @@ bi_emit_store(bi_builder *b, nir_intrinsic_instr *instr, enum bi_seg seg)
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bi_store(b, instr->num_components * nir_src_bit_size(instr->src[0]),
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bi_src_index(&instr->src[0]),
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bi_src_index(&instr->src[1]), bi_addr_high(&instr->src[1]),
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seg);
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seg, 0);
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}
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/* Exchanges the staging register with memory */
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@ -428,6 +428,7 @@ typedef struct {
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uint32_t fill;
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uint32_t index;
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uint32_t attribute_index;
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int32_t byte_offset;
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int32_t branch_offset;
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struct {
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@ -69,7 +69,7 @@ TEST_F(SchedulerPredicates, FMA)
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TEST_F(SchedulerPredicates, LOAD)
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{
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bi_instr *load = bi_load_i128_to(b, TMP(), TMP(), TMP(), BI_SEG_UBO);
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bi_instr *load = bi_load_i128_to(b, TMP(), TMP(), TMP(), BI_SEG_UBO, 0);
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ASSERT_FALSE(bi_can_fma(load));
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ASSERT_TRUE(bi_can_add(load));
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ASSERT_TRUE(bi_must_message(load));
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