fdo-mirrors/mesa
1
0
Fork 0
mirror of https://gitlab.freedesktop.org/mesa/mesa.git synced 2026-05-02 05:48:07 +02:00
Code Issues Projects Releases Packages Wiki Activity Actions 1

pan/bi: Add LD_VAR_BUF_IMM.f16/f32 instructions

Browse source 
For use on Valhall with memory-allocated IDVS jobs.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15216>
This commit is contained in:
Alyssa Rosenzweig 2021-12-07 18:55:57 -05:00 • committed by Marge Bot
parent 48a398bf5b
commit eba9ef4c25
1 changed files with 60 additions and 0 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

60
src/panfrost/bifrost/ISA.xml
View file

@ -8505,4 +8505,64 @@
<mod name="neg2" size="1" opt="neg"/>
</ins>
<ins name="+LD_VAR_BUF_IMM.f32" staging="w=format" message="varying" pseudo="true">
<src start="0"/>
<immediate name="index" start="3" size="5"/>
<mod name="vecsize" start="8" size="2">
<opt>none</opt>
<opt>v2</opt>
<opt>v3</opt>
<opt>v4</opt>
</mod>
<mod name="update" size="2">
<opt>store</opt>
<opt>retrieve</opt>
<opt>conditional</opt>
<opt>clobber</opt>
</mod>
<mod name="register_format" size="2">
<opt>f32</opt>
<opt>f16</opt>
<opt>u32</opt>
<opt>u16</opt>
</mod>
<mod name="sample" size="3">
<opt>center</opt>
<opt>centroid</opt>
<opt>sample</opt>
<opt>explicit</opt>
<opt>none</opt>
</mod>
</ins>
<ins name="+LD_VAR_BUF_IMM.f16" staging="w=format" message="varying" pseudo="true">
<src start="0"/>
<immediate name="index" start="3" size="5"/>
<mod name="vecsize" start="8" size="2">
<opt>none</opt>
<opt>v2</opt>
<opt>v3</opt>
<opt>v4</opt>
</mod>
<mod name="update" size="2">
<opt>store</opt>
<opt>retrieve</opt>
<opt>conditional</opt>
<opt>clobber</opt>
</mod>
<mod name="register_format" size="2">
<opt>f32</opt>
<opt>f16</opt>
<opt>u32</opt>
<opt>u16</opt>
</mod>
<mod name="sample" size="3">
<opt>center</opt>
<opt>centroid</opt>
<opt>sample</opt>
<opt>explicit</opt>
<opt>none</opt>
</mod>
</ins>
</bifrost>