Commit graph

66534 commits

Author SHA1 Message Date
Kenneth Graunke
2b6e703863 i915g: we also have more than 0 viewports!
See 546d6c8d for the corresponding fix in freedreno.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Stephane Marchesin <stephane.marchesin@gmail.com>
Cc: "10.3" <mesa-stable@lists.freedesktop.org>
2014-11-12 20:59:28 -08:00
Eric Anholt
b3d269f5ae vc4: Avoid reusing a pointer from c->outputs[] after add_output().
add_output() can resize the qreg array, so we might use a stale pointer.
2014-11-12 18:24:10 -08:00
Eric Anholt
acc1cca7ae vc4: Fix assumption of TGSI OUT[0] being POSITION in the VS.
All the shaders we've received so far had this be the case, but with
nir-to-tgsi that changed.

I might decide to make nir-to-tgsi keep the outputs in the same order, for
debugging sanity, but I'm not sure.
2014-11-12 18:23:40 -08:00
Ilia Mirkin
22543dd8a1 nvc0: remove unused mm_VRAM_fe0
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
2014-11-12 15:24:15 -05:00
José Fonseca
9247509a8d st/glx: Implement GLX_EXT_create_context_es2_profile.
apitrace now supports it, and it makes it much easier to test
tracing/replaying on OpenGL ES contexts since
GLX_EXT_create_context_{es2,es}_profile are widely available.

Reviewed-by: Brian Paul <brianp@vmware.com>
2014-11-12 19:03:50 +00:00
Tom Stellard
0cae7ea271 Revert "clover: Fix build after llvm r221375"
This reverts commit cd93d82ba9.

llvm r221375 was reverted, so this commit needs to be too.
2014-11-12 12:30:08 -05:00
José Fonseca
977b18e486 gallivm: Fix build with LLVM 3.6 (r221751).
Tested with LLVM 3.3, 3.4, 3.5, and 3.6.

Trivial.
2014-11-12 11:08:07 +00:00
Matt Turner
7a82961b71 i965/cfg: Remove if_block/else_block.
I used these in the SEL peephole, but they require extra tracking and
fix ups. The SEL peephole can pretty easily find the blocks it needs
without these.

Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
2014-11-11 09:41:06 -08:00
Matt Turner
4001181ba3 i965/fs: Don't use if_block/else_block in SEL peephole.
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
2014-11-11 09:41:06 -08:00
Chia-I Wu
20a061d2b4 ilo: clean up gen6_3DSTATE_SF()
Make the helpers fill out valid Gen7 3DSTATE_SF and 3STATE_SBE.  This
prevents the helpers from having to do

  dw[0] = GEN7_SBE_DW1_x; // setting DW1 value to dw[0]!?

and simplifies gen7_3DSTATE_{SF,SBE}().

Signed-off-by: Chia-I Wu <olvaffe@gmail.com>
2014-11-11 16:04:18 +08:00
Chia-I Wu
239dca78b1 ilo: clean up gen7_3DSTATE_STREAMOUT()
Render stream and render enable are independent from so enable.  Having a
single return point makes it easier to see that.

Signed-off-by: Chia-I Wu <olvaffe@gmail.com>
2014-11-11 13:52:26 +08:00
Chia-I Wu
eab595d573 ilo: rework gen7_3DSTATE_SO_DECL_LIST()
Started to make pipe_stream_output_info mandatory, but ended up adding support
for stream id and making a workaround Gen7-specific.

Signed-off-by: Chia-I Wu <olvaffe@gmail.com>
2014-11-11 13:52:26 +08:00
Chia-I Wu
c637075ea2 ilo: add 3DSTATE_SO_BUFFER variants
Add gen7_disable_3DSTATE_SO_BUFFER() to disable SO buffers.

Signed-off-by: Chia-I Wu <olvaffe@gmail.com>
2014-11-11 13:52:25 +08:00
Chia-I Wu
2ff88ce4be ilo: add gen6_3dstate_constant()
It replaces gen6_fill_3dstate_constant().  gen6_3DSTATE_CONSTANT_{VS,GS,PS}
are made wrappers of the new function.

Signed-off-by: Chia-I Wu <olvaffe@gmail.com>
2014-11-11 13:52:25 +08:00
Chia-I Wu
31372f2d2c ilo: add variants of 3DSTATE_{HS,DS}
Rename them to gen7_disable_3DSTATE_{HS,DS}() to reflect the fact.

Signed-off-by: Chia-I Wu <olvaffe@gmail.com>
2014-11-11 13:52:25 +08:00
Chia-I Wu
421b565b3b ilo: add variants of 3DSTATE_GS
Add gen6_so_3DSTATE_GS(), gen6_disable_3DSTATE_GS(), and
gen7_disable_3DSTATE_GS() to do SO on GEN6 or to disable GS.

Signed-off-by: Chia-I Wu <olvaffe@gmail.com>
2014-11-11 13:52:22 +08:00
Chia-I Wu
63ded78e1c ilo: add variants of 3DSTATE_VS
Add gen6_disable_3DSTATE_VS() to disable VS.

Signed-off-by: Chia-I Wu <olvaffe@gmail.com>
2014-11-11 13:51:36 +08:00
Chia-I Wu
9087239df8 ilo: add variants of 3DSTATE_PS
Add gen7_disable_3DSTATE_PS() to disable PS.

Signed-off-by: Chia-I Wu <olvaffe@gmail.com>
2014-11-11 13:51:31 +08:00
Chia-I Wu
8ebb86325b ilo: add variants of 3DSTATE_WM
Add gen6_hiz_3DSTATE_WM() and gen7_hiz_3DSTATE_WM() for HiZ ops without
dispatching.

Signed-off-by: Chia-I Wu <olvaffe@gmail.com>
2014-11-11 13:51:28 +08:00
Chia-I Wu
703ae84ac2 ilo: add variants of 3DSTATE_CLIP
Add gen6_disable_3DSTATE_CLIP to disable clipping.

Signed-off-by: Chia-I Wu <olvaffe@gmail.com>
2014-11-11 13:51:21 +08:00
Chia-I Wu
8abf4976c6 ilo: prefix 3DSTATE_VF with gen75
3DSTATE_VF is Gen7.5+ only.

Signed-off-by: Chia-I Wu <olvaffe@gmail.com>
2014-11-11 09:11:56 +08:00
Michael Varga
9d6253cf82 st/va: MPEG4 call vlVaDecoderFixMPEG4Startcode()
If the VOP and GOV headers were truncated they will be regenerated.

Signed-off-by: Michael Varga <Michael.Varga@amd.com>
2014-11-10 10:24:07 -05:00
Michael Varga
d335f5ffa6 st/va: MPEG4 generate GOV and VOP header
Also, Implemented a small locally used interface for writing bits to a buffer.

Signed-off-by: Michael Varga <Michael.Varga@amd.com>
2014-11-10 10:24:07 -05:00
Michael Varga
fa9e461967 st/va: MPEG4 populate the SPS structure
Signed-off-by: Michael Varga <Michael.Varga@amd.com>
2014-11-10 10:24:07 -05:00
Michael Varga
92350a65c4 st/va: MPEG4 populate the iq matrix buffers
Signed-off-by: Michael Varga <Michael.Varga@amd.com>
2014-11-10 10:24:07 -05:00
Michael Varga
9f1ee1b5c9 st/va: MPEG4 populate the PPS structure
Signed-off-by: Michael Varga <Michael.Varga@amd.com>
2014-11-10 10:24:07 -05:00
Michael Varga
c24ee2cf43 st/va: refactored handleVASliceDataBufferType
This patch cleans the function handleVASliceDataBufferType() for better
readability.

Signed-off-by: Michael Varga <Michael.Varga@amd.com>
2014-11-10 10:24:07 -05:00
Ian Romanick
46a2323c3f mesa: Remove _mesa_max_buffer_index
It appears to be completely unused since f9be8543 (February 2012).

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-11-10 05:38:03 -08:00
Ian Romanick
8e4a6481e8 mesa: Uniform logging is very, very unlikely
Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
2014-11-10 04:25:40 -08:00
Ian Romanick
9cdf66657a glsl: Swap the order of glsl_type::name and ::length
On x86-64 this saves 8 bytes of padding in the structure, and this
reduces the size of the structure to 32 bytes.

v2: Fix constructor so that GCC won't warn about the order of
initialization.

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
2014-11-10 04:25:40 -08:00
Ian Romanick
3711abd780 glsl: Store glsl_type::vector_elements and ::matrix_columns as uint8_t
Due to the total number of bits used in the bitfield, this does not
increase the size of the structure.

It does, however, reduce the number of instructions required each time
one of these fields is accessed.  To access ::matrix_columns with the
bitfield, three instructions were required:

    movzbl 0x9(%rdx),%eax
    shr    %al
    and    $0x7,%eax

As a uint8_t, only one instruction is required.

    movzbl 0xa(%rdx),%eax

These fields are accessed *a lot*.

Valgrind callgrind results for a trace of Tesseract:

                 _mesa_Uniform4fv  _mesa_Uniform4f  _mesa_Uniform1i
Before (64-bit):       48,103,497       16,556,096          676,447
After  (64-bit):       45,722,616       15,737,964          670,607

                 _mesa_Uniform4fv  _mesa_Uniform4f  _mesa_Uniform1i
Before (32-bit):       61,472,611       21,051,222          821,361
After  (32-bit):       57,987,421       19,872,226          811,609

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
2014-11-10 04:25:40 -08:00
Ian Romanick
378d92c74e mesa: Don't check for API_OPENGLES in _mesa_uniform_matrix
There are no uniforms in OpenGL ES 1.x, so we can't even get to this
code in that API.

Also, reorder the checks.  First check that transpose is true, then
check whether or not that is legal in the current API.  transpose should
never be true in an ES2 context, so this gets one check (the more
expensive one) out of the main path.

Valgrind callgrind results for a trace of Tesseract:

                 _mesa_UniformMatrix4fv  _mesa_UniformMatrix3fv
Before (64-bit):             96,119,025              24,240,510
After  (64-bit):             90,726,569              22,926,662

                 _mesa_UniformMatrix4fv  _mesa_UniformMatrix3fv
Before (32-bit):            132,434,452              29,051,808
After  (32-bit):            126,658,112              27,989,316

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
2014-11-10 04:25:40 -08:00
Ian Romanick
91a2fa1490 mesa: Rework array error checks in validate_uniform_parameters
Before ARB_explicit_uniform_location, Mesa's location encoding allowed
locations for non-array types that had non-zero array indices.
Basically, part of the location was the uniform and part was the array
index.  This meant that some checks had to occur for arrays and
non-arrays.  This is no longer possible, we the checks can be split up.

Valgrind callgrind results for a trace of Tesseract:

                 _mesa_Uniform4fv  _mesa_Uniform4f  _mesa_Uniform1i
Before (64-bit):       50,499,557      17,487,316           686,227
After  (64-bit):       50,023,791      17,274,432           684,293

                 _mesa_Uniform4fv  _mesa_Uniform4f  _mesa_Uniform1i
Before (32-bit):       62,968,039       21,732,380          828,147
After  (32-bit):       62,373,967       21,490,756          826,223

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
2014-11-10 04:25:40 -08:00
Ian Romanick
366540e9af mesa: Get some gl_shader_program::LinkStatus checking out of the main path
I really wanted to remove 'shProg != NULL' as well, but that would have
required adding a dummy program as the default program.  That seemed
like more churn than removing one test was worth.

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
2014-11-10 04:25:39 -08:00
Ian Romanick
3f5ebb98b7 mesa: Rework location == -1 error checking
Only one caller wanted to generate an error when location == -1, so move
the error generation to that caller.  There will be more callers in the
future that do not want to generate errors.

Move the location == -1 check later in validate_uniform_parameters.  As
currently implemented, glUniform1iv(-1, -1, data) would not generate an
error, but it should due to count being < 0.

The location that I have moved it to will make more sense with the next
commit.

Valgrind callgrind results for a trace of Tesseract:

                 _mesa_Uniform4fv  _mesa_Uniform4f  _mesa_Uniform1i
Before (64-bit):       51,241,217      17,740,162           689,181
After  (64-bit):       50,499,557      17,487,316           686,227

                 _mesa_Uniform4fv  _mesa_Uniform4f  _mesa_Uniform1i
Before (32-bit):       63,940,605       21,987,918          831,065
After  (32-bit):       62,968,039       21,732,380          828,147

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
2014-11-10 04:25:39 -08:00
Ian Romanick
23dcbf623f mesa: Minor clean ups in _mesa_uniform
Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
2014-11-10 04:25:39 -08:00
Ian Romanick
9c38d4db52 mesa: Remove GLSL_TYPE_SAMPLER check
Noting the assertion just a few lines earlier, returnType cannot be
GLSL_TYPE_SAMPLER.

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
2014-11-10 04:25:39 -08:00
Ian Romanick
5b9cf337b4 mesa/main: Pass the data that _mesa_uniform actually wants
The GL_ enums were previously used because glsl_types.h couldn't be used
in C code.  That was fixed some time ago (and uniforms.c already
includes glsl_types.h), so this is no longer necessary.

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
2014-11-10 04:25:39 -08:00
Chia-I Wu
d388d8576f ilo: derive fb blending caps at bind time
Derive whether a RT supports blending, logicop, and the like when
set_framebuffer_state() is called.  This enables us to simplify
gen6_BLEND_STATE().

Signed-off-by: Chia-I Wu <olvaffe@gmail.com>
2014-11-10 15:46:31 +08:00
Chia-I Wu
55d70e0669 ilo: remove inlined state functions
We had some inlined state functions for dispatching.  They were not needed
with the new top/bottom split.

Signed-off-by: Chia-I Wu <olvaffe@gmail.com>
2014-11-10 15:46:19 +08:00
Chia-I Wu
c88c49baf4 ilo: use top/bottom split for state functions
Follow the builder and split state functions into top (vertex processing) and
bottom (pixel processing).

Signed-off-by: Chia-I Wu <olvaffe@gmail.com>
2014-11-10 13:14:04 +08:00
Kenneth Graunke
f3b709c0ac i965: Advertise a line width of 40.0 on Cherryview and Skylake.
According to the documentation, line widths higher than 40.0 may have
quality problems.  That's already 20 times larger than we've been
exposing, so it seems totally sufficient.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>
2014-11-08 22:24:08 -08:00
Kenneth Graunke
6dab04d7e3 i965: Advertise larger line widths.
We've artificially been limiting this to 5 for no particular reason.

On Gen4-5, the limit is [0, 7.5] with a granularity of 0.5 (U3.1).
On Gen6+, the limit is [0, 7.9921875].  Since it's a U3.7, the
granularity should be 0.125 (1/8).

This patch conservatively advertises one granularity smaller than the
hardware's maximum value, just in case there's a problem using the
largest possible value.  On Gen4-5, this is 7.5 - 0.5 = 7.0.  On Gen6+,
this is 8.0 - 0.125 = 7.875.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>
2014-11-08 22:22:54 -08:00
Kenneth Graunke
61838fd9ad i965: Use ctx->Const.MaxLineWidth when clamping ctx->Line.Width.
Rather than hardcoding platform values in every code path, just use the
maximum value we set.

Currently, ctx->Const.LineWidth == 5, which is smaller than the hardware
limit.  But applications shouldn't be using a value larger than we
support anyway.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>
2014-11-08 22:22:53 -08:00
Kenneth Graunke
87927ed1f0 i965: Set Line Width correctly on Cherryview and Skylake.
Line Width moved to DW1 bits 29:12.  It's actually now a U11.7.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>
2014-11-08 22:22:18 -08:00
Emil Velikov
a6d8413d7c docs: add news item and link release notes for mesa 10.3.3
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
2014-11-08 17:22:15 +00:00
Emil Velikov
caa0fb4709 docs: Add sha256 sums for the 10.3.3 release
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
(cherry picked from commit 9cc26056ee)
2014-11-08 17:22:15 +00:00
Emil Velikov
0d5da6d9a8 Add release notes for the 10.3.3 release
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
(cherry picked from commit 1a9cc5f50d)
2014-11-08 17:22:15 +00:00
José Fonseca
b238c756da util/format: Fix clamping to 32bit integers.
Use clamping constants that guarantee no integer overflows.

As spotted by Chris Forbes.

This causes the code to change as:

-         value |= (uint32_t)CLAMP(src[0], 0.0f, 4294967295.0f);
+         value |= (uint32_t)CLAMP(src[0], 0.0f, 4294967040.0f);

-         value |= (uint32_t)((int32_t)CLAMP(src[0], -2147483648.0f, 2147483647.0f));
+         value |= (uint32_t)((int32_t)CLAMP(src[0], -2147483648.0f, 2147483520.0f));

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
2014-11-08 10:32:39 +00:00
José Fonseca
d268eac3a9 util/format: Generate floating point constants for clamping.
This commit causes the generated C code to change as

            union util_format_r32g32b32a32_sscaled pixel;
  -         pixel.chan.r = (int32_t)CLAMP(src[0], -2147483648, 2147483647);
  -         pixel.chan.g = (int32_t)CLAMP(src[1], -2147483648, 2147483647);
  -         pixel.chan.b = (int32_t)CLAMP(src[2], -2147483648, 2147483647);
  -         pixel.chan.a = (int32_t)CLAMP(src[3], -2147483648, 2147483647);
  +         pixel.chan.r = (int32_t)CLAMP(src[0], -2147483648.0f, 2147483647.0f);
  +         pixel.chan.g = (int32_t)CLAMP(src[1], -2147483648.0f, 2147483647.0f);
  +         pixel.chan.b = (int32_t)CLAMP(src[2], -2147483648.0f, 2147483647.0f);
  +         pixel.chan.a = (int32_t)CLAMP(src[3], -2147483648.0f, 2147483647.0f);
            memcpy(dst, &pixel, sizeof pixel);

which surprisingly makes a difference for MSVC.

Thanks to Juraj Svec for diagnosing this and drafting a fix.

Fixes https://bugs.freedesktop.org/show_bug.cgi?id=29661
2014-11-08 10:32:39 +00:00