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i965: Set Line Width correctly on Cherryview and Skylake.

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Line Width moved to DW1 bits 29:12.  It's actually now a U11.7.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>
This commit is contained in:
Kenneth Graunke 2014-11-03 16:10:55 -08:00
parent a6d8413d7c
commit 87927ed1f0
2 changed files with 6 additions and 1 deletions
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1
src/mesa/drivers/dri/i965/brw_defines.h
View file

@ -1805,6 +1805,7 @@ enum brw_message_target {
# define GEN6_SF_SWIZZLE_ENABLE (1 << 21)
# define GEN6_SF_POINT_SPRITE_UPPERLEFT (0 << 20)
# define GEN6_SF_POINT_SPRITE_LOWERLEFT (1 << 20)
# define GEN9_SF_LINE_WIDTH_SHIFT 12 /* U11.7 */
# define GEN6_SF_URB_ENTRY_READ_LENGTH_SHIFT 11
# define GEN6_SF_URB_ENTRY_READ_OFFSET_SHIFT 4
/* DW2 */

6
src/mesa/drivers/dri/i965/gen8_sf_state.c
View file

@ -152,7 +152,11 @@ upload_sf(struct brw_context *brw)
uint32_t line_width_u3_7 = U_FIXED(CLAMP(ctx->Line.Width, 0.0, 7.99), 7);
if (line_width_u3_7 == 0)
line_width_u3_7 = 1;
dw2 |= line_width_u3_7 << GEN6_SF_LINE_WIDTH_SHIFT;
if (brw->gen >= 9 || brw->is_cherryview) {
dw1 |= line_width_u3_7 << GEN9_SF_LINE_WIDTH_SHIFT;
} else {
dw2 |= line_width_u3_7 << GEN6_SF_LINE_WIDTH_SHIFT;
}
if (ctx->Line.SmoothFlag) {
dw2 |= GEN6_SF_LINE_END_CAP_WIDTH_1_0;