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Author SHA1 Message Date
Danylo Piliaiev
d5199e2d29 tu: Fix misleading lrz_disabled_at_draw values for RP
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tu_render_pass_state_merge checks if lrz_disable_reason is NULL,
but it wasn't initialized to NULL.

Fixes: d6684aedf4 ("tu: Track at which draw call LRZ is disabled")

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39263>
 2026-01-12 17:07:15 +00:00
Georg Lehmann
daf235c607 aco/tests: don't destroy vk_device if it was never created 
Happens if you only run one test that doesn't need a vk_device.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39268>
 2026-01-12 16:16:54 +00:00
Georg Lehmann
fad95030a7 aco/tests: test VALUMaskWriteHazard with v_cmpx 
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39252>
 2026-01-12 15:48:39 +00:00
Georg Lehmann
1d85552745 aco/tests: test VALUReadSGPRHazard with v_cmpx 
To avoid regressing this in a future rework.

Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39252>
 2026-01-12 15:48:39 +00:00
Georg Lehmann
3e10ab34e1 aco/insert_NOPs: explicitly wait for sa_sdst to resolve SALU -> VALU hazards 
The assumption that these waits are not required has been proven incorrect
in at least some cases.

Totals from 190 (0.24% of 79825) affected shaders: (Navi31)
Instrs: 499718 -> 500491 (+0.15%)
CodeSize: 2658228 -> 2661916 (+0.14%)
Latency: 5964632 -> 5965453 (+0.01%); split: -0.00%, +0.01%
InvThroughput: 794221 -> 794289 (+0.01%)

Totals from 17093 (21.41% of 79839) affected shaders: (Navi48)
Instrs: 22805214 -> 22854313 (+0.22%)
CodeSize: 121240428 -> 121432904 (+0.16%); split: -0.00%, +0.16%
Latency: 166500300 -> 166530529 (+0.02%); split: -0.00%, +0.02%
InvThroughput: 28770053 -> 28772870 (+0.01%); split: -0.00%, +0.01%

Fixes: 018f45f981 ("aco/insert_NOPs: remove redundant VALUReadSGPRHazard waits")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/14516

Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39252>
 2026-01-12 15:48:38 +00:00
David Rosca
94f2d110a1 frontends/va: Fix RGB/YUV conversion in Get/PutImage 
This needs to set some matrix, otherwise identity would be used for
RGB/YUV conversion. For YUV/YUV or RGB/RGB conversion vlVaPostProcCompositor
will ignore the matrices, so it's okay to always set bt709.
Also set color range.

Fixes: 9393a0510b ("frontends/va: Use new RGB YUV conversion matrix")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/14456
Reviewed-by: Ruijing Dong <ruijing.dong@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38892>
 2026-01-12 15:32:40 +00:00
David Rosca
1395d806ba frontends/va: Also treat PRI/TRC_RESERVED0 as unspecified 
PIPE_VIDEO_VPP_PRI_RESERVED0 and PIPE_VIDEO_VPP_TRC_RESERVED0 have value 0,
and this is what we will get from apps that doesn't set primaries and transfer
characteristics at all.

Fixes: a284bff8ad ("frontends/va: Set color properties when not using explicit color standard")
Reviewed-by: Ruijing Dong <ruijing.dong@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38892>
 2026-01-12 15:32:39 +00:00
Lionel Landwerlin
081c5bc6a5 brw: fix derivatives on non 32bit floats 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: mesa-stable
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/14600
Meh'd-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39226>
 2026-01-12 15:18:46 +00:00
David Rosca
c81194d8ae pipe: Remove MPEG4 decode support
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Reviewed-by: Leo Liu <leo.liu@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38780>
 2026-01-12 14:51:35 +00:00
David Rosca
7550e0aa49 nouveau: Remove MPEG4 decode support 
Reviewed-by: Leo Liu <leo.liu@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38780>
 2026-01-12 14:51:34 +00:00
David Rosca
eb62e35eac virgl: Remove MPEG4 decode support 
Reviewed-by: Leo Liu <leo.liu@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38780>
 2026-01-12 14:51:34 +00:00
David Rosca
183fe68ce2 r600: Remove MPEG4 decode support 
Reviewed-by: Leo Liu <leo.liu@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38780>
 2026-01-12 14:51:34 +00:00
David Rosca
c78b84a4e2 radeonsi/video: Remove MPEG4 decode support 
Reviewed-by: Leo Liu <leo.liu@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38780>
 2026-01-12 14:51:34 +00:00
David Rosca
73e9df3bf8 frontends/va: Remove MPEG4 decode support 
This has always been disabled by default, because VAAPI doesn't provide
all the parameters we need, which makes it impossible to correctly decode
most streams.

Reviewed-by: Leo Liu <leo.liu@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38780>
 2026-01-12 14:51:33 +00:00
Danylo Piliaiev
12416c9fca tu: Restore PC_TESS_BASE after BIN preemption save/restore
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Preamble save/restore for BINs doesn't handle PC_TESS_BASE, so we
assume that PC_TESS_BASE is invalid after any GMEM pass.

In addition on A7XX PC_TESS_BASE doesn't require WFI.

Fixes misrendering on A750 in "Industria", "Resident Evil 2" and
any other game that uses tesselation.

Cc: mesa-stable

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39235>
 2026-01-12 12:57:26 +00:00
Eric Engestrom
08cb3429c7 docs: update url to ci-tron docs 
We finally moved our docs to our domain, so let's update the link here :)

There's an automatic redirect, but the nightly linkcheck raises it as
"needs updating" since it's a 301, so here we go.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39265>
 2026-01-12 12:52:32 +00:00
Lionel Landwerlin
a97b01801a brw: enable SIMD32 compute shaders with ray queries 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: mesa-stable
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/11020
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36181>
 2026-01-12 12:19:21 +00:00
Lionel Landwerlin
527ae448e5 brw/nir/rt: ensure we can load 2 RT_DISPATCH_GLOBALS 
Each group of 16 lanes inside a SIMD32 shader will load different globals.

In SIMD8/16 shaders, the divergence analysis will turn this load into
nir_load_global_constant_uniform_block_intel.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: mesa-stable
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36181>
 2026-01-12 12:19:21 +00:00
Lionel Landwerlin
b996b03f21 brw: enable topology opcodes in SIMD32 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: mesa-stable
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36181>
 2026-01-12 12:19:21 +00:00
Lionel Landwerlin
286073f6eb brw: handle lowering of a couple of opcodes 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: mesa-stable
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36181>
 2026-01-12 12:19:21 +00:00
Lionel Landwerlin
2fa09500a2 brw: enable ray query spilling in SIMD32 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: mesa-stable
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36181>
 2026-01-12 12:19:21 +00:00
Lionel Landwerlin
6d19b898e7 anv/brw: prep work for SIMD32 ray queries 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: mesa-stable
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36181>
 2026-01-12 12:19:21 +00:00
Samuel Pitoiset
b65cc9d587 ac,radv: sample and set correct shader/memory clocks for RGP 
These clocks need to be the clocks at trace time. This shouldn't fix
anything given that RADV sets profile_peak when SQTT is enabled but
better to report it correctly anyways.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39208>
 2026-01-12 11:58:43 +00:00
David Rosca
bcfe698afe radeonsi/vcn: Use is_non_existing H264 ref flag 
Reviewed-by: Benjamin Cheng <benjamin.cheng@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31368>
 2026-01-12 11:35:41 +00:00
David Rosca
e7aaea0e27 frontends/va: Support VA_PICTURE_H264_NON_EXISTING 
Reviewed-by: Benjamin Cheng <benjamin.cheng@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31368>
 2026-01-12 11:35:41 +00:00
David Rosca
f9c646670b radeonsi/video: Don't report support for H264 Baseline profile 
Frontend was using PIPE_VIDEO_PROFILE_MPEG4_AVC_BASELINE for
VAProfileH264ConstrainedBaseline, so this hasn't caused any issues.
Change it to correct enum value to make it less confusing.

Reviewed-by: Ruijing Dong <ruijing.dong@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38748>
 2026-01-12 11:21:39 +00:00
David Rosca
6ed00e2d5d frontends/va: Use correct pipe profile for VAProfileH264ConstrainedBaseline 
Reviewed-by: Ruijing Dong <ruijing.dong@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38748>
 2026-01-12 11:21:39 +00:00
David Rosca
0518784b62 radv/amdgpu: Only wait on queue syncobj when needed 
This would always wait on the queue syncobj if there was any other
wait syncobj, but it should only wait after zero submit.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39193>
 2026-01-12 10:59:03 +00:00
Dave Airlie
ab9e904f24 radv/coopmat: fix deref stride
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This at least fixes the nir debug output to have correct values.

Fixes: 48fc8c8d1c ("radv/nir/lower_cmat: set optimal load/store alignment")
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39256>
 2026-01-12 10:39:05 +00:00
David Rosca
df4220d500 radv/video: Use different dpb swizzle mode for 10 bit encode 
Acked-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Benjamin Cheng <benjamin.cheng@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39189>
 2026-01-12 10:18:18 +00:00
David Rosca
587a7aa510 radv: Enable DCC modifiers for multi plane formats on GFX12 
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39190>
 2026-01-12 09:57:56 +00:00
Samuel Pitoiset
5bcca4a832 radv/spm: use a staging buffer for faster reads on dGPUS 
This allows us to move the SPM buffer to VRAM because I think it must
be in VRAM too.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39195>
 2026-01-12 09:35:37 +00:00
Samuel Pitoiset
6863a90486 radv/spm: rework allocating the SPM buffer 
For using a staging buffer.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39195>
 2026-01-12 09:35:37 +00:00
Samuel Pitoiset
c7d0aa6671 radv/sqtt: use a staging buffer for faster reads on dGPUS 
This is way faster.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39195>
 2026-01-12 09:35:36 +00:00
Samuel Pitoiset
5d430940d2 radv/sqtt: rework allocating the SQTT buffer 
For using a staging buffer.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39195>
 2026-01-12 09:35:36 +00:00
Samuel Pitoiset
1c611c2dac radv/sqtt: use VkCommandBuffer objects for SQTT start/stop sequences 
For using a staging buffer.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39195>
 2026-01-12 09:35:35 +00:00
Marek Olšák
ceb2667cf3 gallium/util: print task/mesh statistics in util_end_pipestat_query 
Used for debugging. Not used by anything in the tree.

Reviewed-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39253>
 2026-01-12 08:51:15 +00:00
Yiwei Zhang
b41f466045 panvk: fix to defer disk cache init after vk_physical_device_init
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Instead of initializing the disk cache earlier, the vk_properties
filling can be deferred after disk cache init is done. Otherwise, the
created disk cache will be zero'ed out in vk_physical_device_init,
ending up with leaked alloc and disabled disk cache (though advertised).

Fixes: acd00c07f6 ("panvk: Initialize the disk cache earlier")
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39248>
 2026-01-12 08:34:46 +00:00
Samuel Pitoiset
6f4b3c7c9b ac/perfcounter: re-order GPU perf blocks on GFX11 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39199>
 2026-01-12 08:10:33 +00:00
Samuel Pitoiset
653b39989a ac/perfcounter: define more GPU blocks on GFX11 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39199>
 2026-01-12 08:10:33 +00:00
Samuel Pitoiset
d391cd0c4d ac/perfcounter: fix number of scoped instances for RMI block 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39199>
 2026-01-12 08:10:33 +00:00
Samuel Pitoiset
ea63aa3e8e ac/perfcounter: add missing configuration for GCEA on GFX11 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39199>
 2026-01-12 08:10:33 +00:00
Samuel Pitoiset
6722a6332a ac,radv,radeonsi: rename num_spm_counters to num_spm_modules 
A module can have different number of counters.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39199>
 2026-01-12 08:10:32 +00:00
Samuel Pitoiset
fb43d7bff2 ac/perfcounter: re-order GPU perf blocks on GFX12 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39199>
 2026-01-12 08:10:31 +00:00
Samuel Pitoiset
3b6ff80d48 ac/perfcounter: define more GPU blocks on GFX12 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39199>
 2026-01-12 08:10:31 +00:00
Samuel Pitoiset
eb37d6ceb7 ac/perfcounter: fix computing number of 16-bit/32-bit SPM counters 
Determine them only when both are explicitly 0.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39199>
 2026-01-12 08:10:30 +00:00
Samuel Pitoiset
d1efdc7e76 ac/perfcounter: fix number of 32-bit SPM counters 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39199>
 2026-01-12 08:10:29 +00:00
Samuel Pitoiset
9fe57d3882 ac/spm: define new per-shader engine blocks 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39199>
 2026-01-12 08:10:29 +00:00
Samuel Pitoiset
60fac38491 ac/spm: fix typo in one GPU perf block name 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39199>
 2026-01-12 08:10:29 +00:00
Samuel Pitoiset
db02077c8a radv: remove extra instructions after UNREACHABLE 
Minor cleanups.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39237>
 2026-01-12 07:41:08 +00:00