Commit graph

219613 commits

Author SHA1 Message Date
Karol Herbst
d2bf824baf nak: replace legalize_ext_instr with explicit lowering
legalize_ext_instr wasn't doing anything besides lowering uniform sources
and panicing on a bunch of Source types.

Having a common helper looping over all sources doesn't make much sense,
because all the instructions are widly different in regards to UGPRs. The
panics will be hit while emitting the sources as well, so this helper
provided little help and wasn't flexible enough for what we need.

Furthermore some instructions like LDG also take an additional input
predicate that legalize_ext_instr can't handle.

Reviewed-by: Mary Guillemard <mary@mary.zone>
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Acked-by: Mel Henning <mhenning@darkrefraction.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40272>
2026-03-10 00:10:04 +00:00
Karol Herbst
95f19bd5eb nak: invalidate loop analysis with nak_nir_lower_load_store
We'll start to lower load_global_bounded there and that will invalidate
loop analysis, because the amount of instructions will change within a
block.

Reviewed-by: Mary Guillemard <mary@mary.zone>
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Acked-by: Mel Henning <mhenning@darkrefraction.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40272>
2026-03-10 00:10:04 +00:00
Benjamin Cheng
8f1ace0571 radv: Disable video features for some DRM modifiers
Filter out video decode/encode format features when the DRM modifier
doesn't support video operations. Along with a CTS fix, this will fix
dEQP-VK.video.formats.* on UVD/VCN1 (which do not support swizzled
input).

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40203>
2026-03-09 23:27:46 +00:00
Iván Briano
5d22f307d5 anv: don't try to fast clear D/S with multiview
Some checks are pending
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If multiview is enabled on the render pass, baseLayer and layerCount
will be 0 and 1 respectively and throw us off.
We can still fast clear if view_mask == 1, but anything else hits the
BLORP_BATCH_NO_EMIT_DEPTH_STENCIL restriction.

Fixes: e488773b29 ("anv: Fast clear depth/stencil surface in vkCmdClearAttachments")

Signed-off-by: Iván Briano <ivan.briano@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40229>
2026-03-09 22:49:05 +00:00
Georg Lehmann
6936282bd3 nir/opt_algebraic: remove min(a, >= 1.0) before fsat
Foz-DB Navi48:
Totals from 86 (0.08% of 114655) affected shaders:
Instrs: 217553 -> 217408 (-0.07%); split: -0.07%, +0.01%
CodeSize: 1159992 -> 1159380 (-0.05%); split: -0.06%, +0.01%
Latency: 1657600 -> 1657533 (-0.00%); split: -0.01%, +0.00%
InvThroughput: 203205 -> 203178 (-0.01%); split: -0.02%, +0.00%
SClause: 5245 -> 5244 (-0.02%)
Copies: 13726 -> 13716 (-0.07%); split: -0.14%, +0.07%
VALU: 130151 -> 130039 (-0.09%); split: -0.09%, +0.00%
SALU: 26476 -> 26474 (-0.01%); split: -0.02%, +0.01%

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40281>
2026-03-09 21:11:25 +00:00
Georg Lehmann
108a4d4341 nir: create more fsat using range analysis
Foz-DB Navi48:
Totals from 5922 (5.17% of 114655) affected shaders:
Instrs: 5188307 -> 5184193 (-0.08%); split: -0.09%, +0.01%
CodeSize: 27852544 -> 27843252 (-0.03%); split: -0.05%, +0.01%
Latency: 28723967 -> 28714268 (-0.03%); split: -0.04%, +0.01%
InvThroughput: 4745002 -> 4742298 (-0.06%); split: -0.07%, +0.01%
VClause: 68649 -> 68650 (+0.00%)
SClause: 103932 -> 103917 (-0.01%); split: -0.02%, +0.00%
Copies: 244683 -> 244706 (+0.01%); split: -0.01%, +0.02%
PreSGPRs: 272361 -> 272362 (+0.00%); split: -0.00%, +0.00%
VALU: 3248960 -> 3245520 (-0.11%); split: -0.11%, +0.00%
SALU: 516784 -> 516796 (+0.00%); split: -0.01%, +0.01%
VOPD: 8910 -> 8895 (-0.17%)

Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40281>
2026-03-09 21:11:25 +00:00
Sagar Ghuge
f7e3085e6a anv: Improve bvh_no_build option
Some checks are pending
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We can't guarantee that skipping the BVH build would let the BVH memory
all zero. So explicitly set it to zero when running things with
BVH_NO_BUILD option.

This will help us to narrow down isuse if it's in BVH encoding or
application shader. Leaving uninitialized blob of memory would hit
intermittent hangs and would lead us to nowhere.

Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40276>
2026-03-09 20:31:27 +00:00
Felix DeGrood
8ad49647f7 intel/decoder: update warning message when buildtype=release
INTEL_DEBUG=bat is no longer supported on release drivers, instead
using a stub decoder. Update stub decoder warning message to
mention this.

Signed-off-by: Felix DeGrood <felix.j.degrood@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40306>
2026-03-09 20:01:01 +00:00
Ian Romanick
ffd4497e48 brw/asm: Don't drop accumulator number in the assembler
Previously "acc1" or "acc2" would be stored as acc0.

Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40226>
2026-03-09 19:21:39 +00:00
Ian Romanick
1ae7a82811 brw: Fix encoding of accumulator sources of 3-source instructions
Previously the accumulator was always forced to be acc0.

Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40226>
2026-03-09 19:21:39 +00:00
Ian Romanick
6531c425a0 brw/emit: Src1 can be accumulator on Gfx12.5 and newer
v2: Add Bspec reference number. Suggested by Caio.

Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40226>
2026-03-09 19:21:39 +00:00
Ian Romanick
c3a5b62c08 brw/validate: Perform more 3-src validation in brw_validate instead of brw_eu_emit
v2: s/Lake/Ice Lake/ in a comment. Noticed by Caio. Add a missing Xe2
Bspec reference number. Suggested by Caio.

Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40226>
2026-03-09 19:21:39 +00:00
Ian Romanick
1f45e33072 brw/validate: Implicit read of accumulator cannot also have explicit read
v2: Add Bspec reference number. Suggested by Caio.

Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40226>
2026-03-09 19:21:38 +00:00
Ian Romanick
8a6de2d973 brw/validate: Eliminate duplicate integer multiply validation
I think two MRs must have crossed in the mail so to speak. Keep Caio's
formatting and error message, and keep my PRM quote.

Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40226>
2026-03-09 19:21:38 +00:00
Ian Romanick
64c60582b5 elk/algebraic: Don't optimize SEL.L.SAT or SEL.G.SAT
shader-db:

Broadwell
total instructions in shared programs: 18607516 -> 18607530 (<.01%)
instructions in affected programs: 2095 -> 2109 (0.67%)
helped: 0 / HURT: 8

total cycles in shared programs: 955704436 -> 955702925 (<.01%)
cycles in affected programs: 34299 -> 32788 (-4.41%)
helped: 2 / HURT: 6

All Haswell and older platforms had similar results. (Haswell shown)
total instructions in shared programs: 16989200 -> 16989201 (<.01%)
instructions in affected programs: 461 -> 462 (0.22%)
helped: 0 / HURT: 1

total cycles in shared programs: 946537070 -> 946537035 (<.01%)
cycles in affected programs: 16378 -> 16343 (-0.21%)
helped: 1 / HURT: 0

Test: piglit!1100
Reported-by: Georg Lehmann
Fixes: ca675b73d3 ("i965/fs: Optimize saturating SEL.L(E) with imm val >= 1.0.")
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40284>
2026-03-09 18:41:55 +00:00
Ian Romanick
6c6c6ce054 brw/algebraic: Don't optimize SEL.L.SAT or SEL.G.SAT
This optimization was added in October 2013, and the error was only just
now discovered. Removing the SEL.G.SAT optimization affected zero
shader-db shaders, and it affected 9 fossil-db shaders for instruction
size only.

I haven't checked to see if any of the hurt shaders are helped by
!39987.

shader-db:

All Intel platforms had similar results. (Lunar Lake shown)
total instructions in shared programs: 17093041 -> 17093055 (<.01%)
instructions in affected programs: 2072 -> 2086 (0.68%)
helped: 0 / HURT: 8

total cycles in shared programs: 876739578 -> 876739154 (<.01%)
cycles in affected programs: 18946 -> 18522 (-2.24%)
helped: 2 / HURT: 6

fossil-db:

Lunar Lake
Totals:
Instrs: 906230557 -> 906240487 (+0.00%); split: -0.00%, +0.00%
CodeSize: 14498856128 -> 14499003168 (+0.00%); split: -0.00%, +0.00%
Send messages: 40667184 -> 40667205 (+0.00%); split: -0.00%, +0.00%
Cycle count: 104068494103 -> 104068561943 (+0.00%); split: -0.00%, +0.00%
Max live registers: 189570192 -> 189570204 (+0.00%); split: -0.00%, +0.00%
Max dispatch width: 48157648 -> 48157552 (-0.00%)
Non SSA regs after NIR: 139823587 -> 139823016 (-0.00%); split: -0.00%, +0.00%

Totals from 9172 (0.46% of 1985212) affected shaders:
Instrs: 10774709 -> 10784639 (+0.09%); split: -0.00%, +0.09%
CodeSize: 177868384 -> 178015424 (+0.08%); split: -0.08%, +0.17%
Send messages: 311154 -> 311175 (+0.01%); split: -0.00%, +0.01%
Cycle count: 232471392 -> 232539232 (+0.03%); split: -0.15%, +0.18%
Max live registers: 1243549 -> 1243561 (+0.00%); split: -0.00%, +0.01%
Max dispatch width: 196672 -> 196576 (-0.05%)
Non SSA regs after NIR: 509663 -> 509092 (-0.11%); split: -0.19%, +0.08%

Test: piglit!1100
Reported-by: Georg Lehmann
Fixes: ca675b73d3 ("i965/fs: Optimize saturating SEL.L(E) with imm val >= 1.0.")
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40284>
2026-03-09 18:41:55 +00:00
Valentine Burley
827370d144 intel/ci: Document recent Intel flakes
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Not caused by the new kernel, these have been flaking for a while now.

Signed-off-by: Valentine Burley <valentine.burley@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40159>
2026-03-09 17:42:03 +00:00
Valentine Burley
64b7388bc2 etnaviv/ci: Switch CI-tron to gfx-ci/linux kernel
We can now use the standard gfx-ci/linux v6.19.5 kernel for all etnaviv
jobs.

Signed-off-by: Valentine Burley <valentine.burley@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40159>
2026-03-09 17:42:03 +00:00
Valentine Burley
68e0eb78d1 freedreno/ci: Switch sm8650 to gfx-ci/linux kernel
Use the standard gfx-ci/linux v6.19.5 kernel for the a750 jobs on
sm8650-hdk.

Signed-off-by: Valentine Burley <valentine.burley@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40159>
2026-03-09 17:42:03 +00:00
Valentine Burley
31090dea4c ci: Update kernel to Linux 6.19.6
The new kernel also fixes the previous issue in the virgl-traces job, but
sadly Xe regressed, so keep the 6.17 kernel in zink-anv-adl.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/14161
Signed-off-by: Valentine Burley <valentine.burley@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40159>
2026-03-09 17:42:03 +00:00
Valentine Burley
efd980aa15 ci/lava: Uprev lava-job-submitter
The new version drops our internal timestamp handling since newer
gitlab-runner versions already provide native timestamp support.

It also prepares for future CI-tron support in gfx-ci/linux by appending
`noinitrd` and `initcall_blacklist=cdc_driver_init` to the kernel
cmdline, disabling the initramdisk and CDC Composite Device that CI-tron
needs.

Signed-off-by: Valentine Burley <valentine.burley@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40159>
2026-03-09 17:42:03 +00:00
Valentine Burley
de7a584093 radeonsi/ci: Skip subgroups.arithmetic tests on Mendocino
This is not caused by the new kernel, these tests have occasionally
timed out over the last couple of weeks.
Running them single-threaded didn't help.

Signed-off-by: Valentine Burley <valentine.burley@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40159>
2026-03-09 17:42:03 +00:00
Karmjit Mahil
72870051d8 zink: Fix incorrect assert checking for linear state format
With `pres->format == PIPE_FORMAT_L8_UNORM` and
`state->format == PIPE_FORMAT_L8_SRGB` the assert is triggered.
We should be comparing the linear version of `state->format` since
we're only concerned about the physical memory layout here.

Signed-off-by: Karmjit Mahil <karmjit.mahil@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31717>
2026-03-09 17:02:26 +00:00
Lionel Landwerlin
de29b88668 anv: fix pulling constant data in compute/mesh/task shaders
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Missing the accounting for the base offset.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/15029
Fixes: 9f2215b480 ("anv/brw: remove push constant load emulation from the backend compiler")
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40301>
2026-03-09 16:25:43 +00:00
Lionel Landwerlin
e70bb86e1c anv: only go into buffer relocs after we've looked at all batches
With the slab, anv_device_lookup_bo() will have anv_bo::map = NULL
while the seen_bbos will not and we want a host pointer for decoding.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40294>
2026-03-09 15:50:51 +00:00
Alyssa Rosenzweig
edccd06a0b nir/lower_subgroups: fix boolean clustered reductions
It is legal to have a cluster size larger than the subgroup/ballot size,
but our lowering would blow up in this case due to the nir_ishl_imm
overflowing in the lowering. Fortunately, this is easy to handle.

Fixes sub_group_clustered_reduce_logical_and()

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40224>
2026-03-09 14:50:37 +00:00
Aitor Camacho
97756219c4 kk: Set command buffer state to 0 when reset
Some checks are pending
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nvk and hk were setting the state to 0, but we weren't which led to issues
with the state being carried over after resetting.

Signed-off-by: Aitor Camacho <aitor@lunarg.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40193>
2026-03-09 13:37:09 +00:00
Eric R. Smith
8521051cfa pco: fix a typo in the check for optimization looping
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The count isn't incremented anywhere else.

Signed-off-by: Eric R. Smith <eric.smith@collabora.com>
Reviewed-by: Simon Perretta <simon.perretta@imgtec.com>
Fixes: f1b24267d2 ("pco: rework nir processing and passes")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40240>
2026-03-09 11:27:27 +00:00
Pavel Ondračka
ce33f82f83 r300: disable clip-discard watermark for triangles
Some checks are pending
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Commit 0d4aa5f55f introduced the watermark to optimize the guardband
state changes and always computed new_distance as MAX2(distance,
watermark).

That is correct for point/line paths where distance > 0, but it keeps a
non-zero discard distance alive when the next draw sets distance = 0
(triangles). This leaks wide point/line clip-discard state into later
triangle draws and can clip away large parts of geometry (as observed in
Sauerbraten). Only apply the watermark when distance > 0 and reset it to
zero otherwise so triangle draws disable clip-discard as intended.

Fixes: 0d4aa5f55f ("r300: pop-free clipping")
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/14959
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40223>
2026-03-09 10:18:51 +00:00
Samuel Pitoiset
8f10e2886c radv: dump the PS epilog in the GPU hang report
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40219>
2026-03-09 09:53:27 +00:00
Samuel Pitoiset
4c7958ae6c radv: apply the 1D workgroup optimization for mesh/task shaders too
Suggested-by: Georg Lehmann <dadschoorse@gmail.com>
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40194>
2026-03-09 09:29:35 +00:00
Samuel Pitoiset
3c4cb16159 radv: fix local invocation index for mesh/task and quad derivatives on GFX12
It must be lowered.

This fixes
dEQP-VK.spirv_assembly.instruction.compute.compute_shader_derivatives.{mesh,task}.*.

Cc: mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40194>
2026-03-09 09:29:34 +00:00
Samuel Pitoiset
4428541c54 radv/meta: fix HTILE fixup after copying depth/stencil image copies
Typo, it should be false because it's after the copy.

Fixes: 4f41818194 ("radv/meta: add a function to fixup HTILE metadata for copies on compute queue")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40270>
2026-03-09 09:07:09 +00:00
Samuel Pitoiset
fff16a9748 radv: replace radv_sdma_surf by ac_sdma_surf
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40186>
2026-03-09 08:40:47 +00:00
Samuel Pitoiset
c40225e490 radv: tidy up radv_sdma_surf
Adjust few things before replacing it by ac_sdma_surf.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40186>
2026-03-09 08:40:47 +00:00
Samuel Pitoiset
0616fd22a5 radv: simplify getting bpe for SDMA surfaces
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40186>
2026-03-09 08:40:46 +00:00
Samuel Pitoiset
9893ac3674 radv: remove unnecessary radv_sdma_surf::{blk_w,blk_h}
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40186>
2026-03-09 08:40:46 +00:00
Samuel Pitoiset
94acb7edd5 radv: simplify computing offset/extent of SDMA surfaces
By computing in elements earlier.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40186>
2026-03-09 08:40:45 +00:00
Samuel Pitoiset
5923a7b8c6 radv: use vk_image_buffer_copy_layout() for SDMA buf layout
For consistency with non-SDMA paths.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40186>
2026-03-09 08:40:45 +00:00
Samuel Pitoiset
02d047099e radv: simplify 96-bit copies with SDMA
By adjusting offset/extent earlier.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40186>
2026-03-09 08:40:45 +00:00
Samuel Pitoiset
6f3b9a62b3 radv: remove redundant radv_sdma_surf::is_linear
is_linear is never used for buffers.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40186>
2026-03-09 08:40:44 +00:00
Samuel Pitoiset
dba9809e0c radv: remove redundant radv_sdma_surf::is_3d
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40186>
2026-03-09 08:40:44 +00:00
Samuel Pitoiset
1a00587c44 radv: fix a GPU hang with PS epilogs and secondary command buffers
If the secondary changes the fragment output state and if the same
PS epilog used before ExecuteCommands() is re-bind immediately after
that call, the PS epilog state wouldn't be re-emitted.

Apply the same change for VS prologs, although the logic is slightly
different and the bug shouldn't occur. The whole logic of secondaries
should be completely rewritten because it's definitely not robust.

This fixes a GPU hang in Where Winds Meet, see
https://github.com/doitsujin/dxvk/issues/5436.

Cc: mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40221>
2026-03-09 08:16:49 +00:00
Samuel Pitoiset
ac3fd06987 radv: always enable DISABLE_CONSERVATIVE_ZPASS_COUNTS on GFX11
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This might cause incorrect occlusion queries count.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40235>
2026-03-09 07:26:25 +00:00
Kenneth Graunke
952bf55483 nir: Fix divergence of Intel URB input/output handle intrinsics
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Tessellation evaluation shaders have a single convergent URB handle
(for the common patch data) used by all lanes.  Every other stage's
IO handles have separate handles in each lane.

Thanks to Alyssa Rosenzweig for catching this bug.

Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40280>
2026-03-09 02:38:59 +00:00
Connor Abbott
6e3d805735 freedreno: Rename afuc to QRisc
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In [1] the AQE is called the "Application QRisc Engine." Thus the real
name of afuc is QRisc. Rename everything.

[1] a698ebd321

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40287>
2026-03-08 22:32:39 +00:00
Connor Abbott
554eec159b freedreno/afuc: Update cread/cwrite syntax in README
We now print actual modifiers instead of mysterious flags. Remove the
remaining ones.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40287>
2026-03-08 22:32:39 +00:00
Mel Henning
1371c53e6a nvk: Expose VK_KHR_depth_clamp_zero_one
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Promoted from EXT

Reviewed-By: Thomas H.P. Andersen <phomes@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39812>
2026-03-08 17:16:26 -04:00
Mel Henning
8e2707950b nvk: Use the MME for cond rendering on Turing+
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We can avoid the stalls from subc switches by avoiding using the copy engine
during vkCmdBeginConditionalRenderingEXT. Implement this by loading the
cond render value using the MME, since the hardware doesn't have a
suitable 32-bit comparison itself.

This brings the Sascha Willems conditionalrender demo from
from 1661 to 8334 fps on my blackwell system with all meshes disabled.

Reviewed-by: Mary Guillemard <mary@mary.zone>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40277>
2026-03-08 17:31:32 +00:00
Mel Henning
905557ab31 nvk: Use SET_GLOBAL_RENDER_ENABLE
This brings the Sascha Willems conditionalrender demo from
927 to 1661 fps on my blackwell system with all meshes disabled.

Reviewed-by: Mary Guillemard <mary@mary.zone>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40277>
2026-03-08 17:31:32 +00:00