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nir: Fix divergence of Intel URB input/output handle intrinsics
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Tessellation evaluation shaders have a single convergent URB handle
(for the common patch data) used by all lanes.  Every other stage's
IO handles have separate handles in each lane.

Thanks to Alyssa Rosenzweig for catching this bug.

Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40280>
This commit is contained in:
Kenneth Graunke 2026-03-06 15:48:21 -08:00 • committed by Marge Bot
parent 6e3d805735
commit 952bf55483
1 changed files with 5 additions and 2 deletions
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7
src/compiler/nir/nir_divergence_analysis.c
View file

@ -361,8 +361,6 @@ visit_intrinsic(nir_intrinsic_instr *instr, struct divergence_state *state)
case nir_intrinsic_load_core_max_id_arm:
case nir_intrinsic_load_warp_max_id_arm:
case nir_intrinsic_load_tess_config_intel:
case nir_intrinsic_load_urb_input_handle_intel:
case nir_intrinsic_load_urb_output_handle_intel:
case nir_intrinsic_load_ray_query_global_intel:
case nir_intrinsic_load_call_return_address_amd:
case nir_intrinsic_load_indirect_address_intel:
@ -398,9 +396,14 @@ visit_intrinsic(nir_intrinsic_instr *instr, struct divergence_state *state)
*/
case nir_intrinsic_load_global_block_intel:
case nir_intrinsic_load_urb_input_handle_indexed_intel:
case nir_intrinsic_load_urb_output_handle_intel:
is_divergent = true;
break;
case nir_intrinsic_load_urb_input_handle_intel:
is_divergent = stage != MESA_SHADER_TESS_EVAL;
break;
case nir_intrinsic_decl_reg:
case nir_intrinsic_load_sysval_nv:
is_divergent = nir_intrinsic_divergent(instr);