Commit graph

92663 commits

Author SHA1 Message Date
Timothy Arceri
d0cec1fce1 glthread: remove extra _mesa_glthread_finish() from generated code
The other user of print_sync_dispatch() was ending up with code that
looked like:

      _mesa_glthread_finish(ctx);
      _mesa_glthread_restore_dispatch(ctx);
      _mesa_glthread_finish(ctx);

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2017-06-07 14:53:38 +10:00
Anuj Phogat
8d02916e0c intel: Fix broxton 2x6 way size computation
This patch is undoing the changes to way size computation
in broxton 2x6, made by below commit:

Commit: 0d576fbfbe
Author:     Anuj Phogat <anuj.phogat@gmail.com>
i965: Simplify l3 way size computations

By making use of l3_banks field in gen_device_info struct
l3_way_size for gen7+ = 2 * l3_banks.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=101306
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Tested-by: Mark Janes <mark.a.janes@intel.com>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
2017-06-06 21:30:51 -07:00
Dave Airlie
86eff151b1 radv: move chip_class extraction down further.
This seems to matter here in a profile, without this we spend a lot
more time exiting this function with no flush bits.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2017-06-07 10:25:20 +10:00
Dave Airlie
00fe30f376 radv: move lots of index related things into the bind.
This just moves lots of stuff to the bind stage rather than
dealing with it in the draw stage.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2017-06-07 10:24:37 +10:00
Dave Airlie
734ea16bdb radv: move calculating the vertex sgpr to the pipeline.
There is no need to calculate this at draw time.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2017-06-07 10:24:36 +10:00
Dave Airlie
3f48021b86 radv: rename and make global some functions.
I want to use these in the pipeline setup stage.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2017-06-07 10:24:36 +10:00
Eric Engestrom
63a8a88ac4 tree-wide: remove trailing backslash
Simple search for a backslash followed by two newlines.
If one of the newlines were to be removed, this would cause issues, so
let's just remove these trailing backslashes.

Signed-off-by: Eric Engestrom <eric.engestrom@imgtec.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
2017-06-07 01:18:09 +01:00
Dave Airlie
f0b82bc545 radv/gfx9: use correct register setting for uconfig regs
Thanks to Marek for pointing this out.

Signed-off-by: Dave Airlie <airlied@redhat.com>
2017-06-07 08:09:03 +10:00
Bas Nieuwenhuizen
59c2e2a061 radv: Remove SI num RB override for occlusion queries.
radeonsi doesn't have it anymore either.

Signed-off-by: Bas Nieuwenhuizen <basni@google.com>
Fixes: f4e499ec79 "radv: add initial non-conformant radv vulkan driver"
Reviewed-by: Dave Airlie <airlied@redhat.com>
2017-06-06 23:23:43 +02:00
Bas Nieuwenhuizen
d607b83b79 radv: Split out updating the vertex descriptors.
Simple refactor.

Signed-off-by: Bas Nieuwenhuizen <basni@google.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
2017-06-06 23:23:43 +02:00
Bas Nieuwenhuizen
58c8aae241 radv: Move pipeline stuff from flush_state to emit_graphics_pipeline.
No functional changes.

Signed-off-by: Bas Nieuwenhuizen <basni@google.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
2017-06-06 23:23:43 +02:00
Bas Nieuwenhuizen
e08f741678 radv: Add early exit for cache flushes.
No sense checking each bit separately in the common case of none
being set.

Signed-off-by: Bas Nieuwenhuizen <basni@google.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
2017-06-06 23:23:43 +02:00
Bas Nieuwenhuizen
4ec89727b2 radv: Remove vertex_descriptors_dirty.
Redundant.

Signed-off-by: Bas Nieuwenhuizen <basni@google.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
2017-06-06 23:23:43 +02:00
Bas Nieuwenhuizen
fe0b8d1e8b radv: Don't use a divide by index_size.
Divides are pretty slow, and this is in the hot path of a draw.

Signed-off-by: Bas Nieuwenhuizen <basni@google.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
2017-06-06 23:23:43 +02:00
Chris Wilson
7063696b71 i965: Explicitly disallow tiled memcpy path on Gen4 with swizzling.
The manual detiling paths are not prepared to handle Gen4-G45 with
swizzling enabled, so explicitly disable them.  (They're already
disabled because these platforms don't have LLC but a future patch could
enable this path).

Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
2017-06-06 11:47:56 -07:00
Matt Turner
bc17155fd0 i965: Remove brw_bo_map_unsynchronized()
Call brw_bo_map() directly.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2017-06-06 11:47:47 -07:00
Matt Turner
e0a9b261e5 i965: Use unsynchronized mappings for BufferSubData on non-LLC
Now that unsynchronized maps actually work, we can use them, like we do
on LLC platforms.

On Broxton, the performance of Unigine Valley 1.1-rc1 is improved by
37.6656% +/- 0.401389% (n=20) at 1280x720/QUALITY_LOW, and by
20.862% +/- 2.20901% (n=3) at 1920x1080/QUALITY_LOW.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2017-06-06 11:47:47 -07:00
Matt Turner
a16355d67d i965: Make unsynchronized maps unsynchronized on non-LLC
On Broxton, the performance of Unigine Valley 1.0 is improved by
13.3067% +/- 0.144322% (n=40) at 1280x720/QUALITY_LOW, and by
1.68478% +/- 0.484226% (n=3) at 1920x1080/QUALITY_LOW.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2017-06-06 11:47:47 -07:00
Matt Turner
ce17d4c5f5 i965: Implement brw_bo_map_unsynchronized() with MAP_ASYNC
This way we can let brw_bo_map() choose the best mapping type.

Part of the patch inlines map_gtt() into brw_bo_map_gtt() (and removes
map_gtt()). brw_bo_map_gtt() just wrapped map_gtt() with locking and a
call to set_domain(). map_gtt() is called by brw_bo_map_unsynchronized()
to avoid the call to set_domain(). With the MAP_ASYNC flag, we now have
the same behavior previously provided by brw_bo_map_unsynchronized().

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2017-06-06 11:47:46 -07:00
Matt Turner
68bfc377fb i965: Elide call to set_domain() if MAP_ASYNC
No functional change (no callers currently pass MAP_ASYNC)

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2017-06-06 11:47:46 -07:00
Matt Turner
2120cfe1af i965: Add and use brw_bo_map()
We can encapsulate the logic for choosing the mapping type. This will
also help when we add WC mappings.

A few functional changes are made in this patch. On non-LLC, what were
previously WB mappings are now GTT mappings (in the prefilling debug
code in brw_performance_query.c; the shader_time code in brw_program.c;
and in the case of an RW mapping in intel_buffer_objects.c).

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2017-06-06 11:47:46 -07:00
Matt Turner
dcb03bf18d i965: Drop MAP_READ from some write-only mappings
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2017-06-06 11:47:46 -07:00
Matt Turner
275401d32b i965: Pass flags to brw_bo_map_*
brw_bo_map_cpu() took a write_enable arg, but it wasn't always clear
whether we were also planning to read from the buffer. I kept everything
semantically identical by passing only MAP_READ or MAP_READ | MAP_WRITE
depending on the write_enable argument.

The other flags are not used yet, but MAP_ASYNC for instance, will be
used in a later patch to remove the need for a separate
brw_bo_map_unsynchronized() function.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2017-06-06 11:47:46 -07:00
Matt Turner
925a4222f2 i965: Rename brw_bo_map() -> brw_bo_map_cpu()
I'm going to make a new function named brw_bo_map() in a later patch
that is responsible for choosing the mapping type, so this patch clears
the way.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2017-06-06 11:47:46 -07:00
Matt Turner
3d1530d3e8 i965: Rename *_virtual -> map_*
I think these are better names, and it reduces the delta between
upstream and Chris Wilson's brw-batch branch.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2017-06-06 11:47:46 -07:00
Chris Wilson
6aa2e8777b i965: Pass the map-mode along to intel_mipmap_tree_map_raw()
Since we can distinguish when mapping between READ and WRITE, we can
pass along the map mode to avoid stalls and flushes where possible.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
2017-06-06 11:47:46 -07:00
Matt Turner
47bb498534 i965: Add a cache_coherent field to brw_bo
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2017-06-06 11:47:46 -07:00
Matt Turner
51d714dca6 i965: Remove unused 'use_resource_streamer' field
Missing in the resource streamer removal of commit 951f56cd43.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2017-06-06 11:47:46 -07:00
Matt Turner
5dc35e1664 i965: Remove brw_bo's virtual member
Just return the map from brw_map_bo_*

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2017-06-06 11:47:46 -07:00
Matt Turner
d7024a6b3c i965: Remove unused brw_bo_map__* functions
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2017-06-06 11:47:46 -07:00
Alex Smith
922b038864 anv: Set better descriptor set limits
Based on discussions with Jason, Ivy Bridge and Bay Trail only actually
support 16 samplers, while newer hardware can support more than the
current limit of 64. Therefore set the lower limit where needed, and
bump up to 128 for everything else. There is also a limit on the total
number of other resources of around 250.

This allows Dawn of War III to render correctly on ANV.

Signed-off-by: Alex Smith <asmith@feralinteractive.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2017-06-06 08:20:09 -07:00
Alex Smith
59c1797d56 anv: Set driver version to Mesa version
As already done by RADV.

v2: Move version calculation function to src/vulkan/util to share with
    RADV.

Signed-off-by: Alex Smith <asmith@feralinteractive.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2017-06-06 08:20:00 -07:00
Alex Smith
dc6182fa3f radv/vulkan: Move radv_get_driver_version to src/vulkan/util
This means it can be reused for other Vulkan drivers. Also fix up a
typo, need to search for '.' in the version string rather than ','.

v2: Remove unneeded temporary version variable (Emil, Eric)

Signed-off-by: Alex Smith <asmith@feralinteractive.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2017-06-06 08:19:55 -07:00
Alex Smith
621b3410f5 util/vulkan: Move Vulkan utilities to src/vulkan/util
We have Vulkan utilities in both src/util and src/vulkan/util. The
latter seems a more appropriate place for Vulkan-specific things, so
move them there.

v2: Android build system changes (from Tapani Pälli)

Signed-off-by: Alex Smith <asmith@feralinteractive.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com>
Acked-by: Jason Ekstrand <jason@jlekstrand.net>
2017-06-06 08:17:13 -07:00
Lionel Landwerlin
2ef73473c8 intel: gen-decoder: rework how we handle groups
The current way of handling groups doesn't seem to be able to handle
MI_LOAD_REGISTER_* with more than one register. This change reworks
the way we handle groups by building a traversal list on loading the
GENXML files.

Let's say you have

Instruction {
  Field0
  Field1
  Field2
  Group0 (count=2) {
    Field0-0
    Field0-1
  }
  Group1 (count=4) {
    Field1-0
    Field1-1
  }
}

We build of linked on load that goes :

Instruction -> Group0 -> Group1

All of those are gen_group structures, making the traversal trivial.
We just need to iterate groups for the right number of timers (count
field in genxml).

The more fancy case is when you have only a single group of unknown
size (count=0). In that case we keep on reading that group for as long
as we're within the DWordLength of that instruction.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Rafael Antognolli <rafael.antognolli@intel.com>
2017-06-06 14:04:37 +01:00
Marek Olšák
6c655cfeb4 radeonsi: fix a GPU hang with tessellation on 2-CU configs
Only harvested Stoney has 2 CUs. Tested on 2-CU Stoney and Fiji forced
to 2 CUs.

Cc: 17.0 17.1 <mesa-stable@lists.freedesktop.org>
Tested-by: Edmondo Tommasina <edmondo.tommasina@gmail.com>
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
2017-06-06 13:01:52 +02:00
Samuel Pitoiset
b9f9bad4eb mesa: make use of NewWindowRectangles driver flags
Now, st_update_window_rectangles() won't be called when the
scissor is going to be updated.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2017-06-06 11:47:31 +02:00
Samuel Pitoiset
035b0176e2 mesa: add new gl_driver_flags::NewWindowRectangles
This new driver flag will replace _NEW_SCISSOR which is
emitted when setting new window rectangles but it actually
triggers useless changes in the state tracker (like scissor
and rasterizer).

EXT_window_rectangles is currently only supported by Nouveau.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2017-06-06 11:47:27 +02:00
Samuel Pitoiset
d19d8f5e6b mesa: remove call to Driver.Scissor() in _mesa_WindowRectanglesEXT()
This is actually useless because this driver call is only used
by the classic DRI drivers which don't support that extension
and probably won't never support it.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2017-06-06 11:47:24 +02:00
Samuel Pitoiset
11c6aab239 mesa: only emit _NEW_MULTISAMPLE when min sample shading changes
We usually check that given parameters are different before
updating the state.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2017-06-06 11:47:22 +02:00
Samuel Pitoiset
af9e537be3 mesa: only emit _NEW_MULTISAMPLE when sample mask changes
We usually check that given parameters are different before
updating the state.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2017-06-06 11:47:19 +02:00
Samuel Pitoiset
706e31fe5a mesa: only emit _NEW_MULTISAMPLE when coverage parameters change
We usually check that given parameters are different before
updating the state.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2017-06-06 11:47:16 +02:00
Kenneth Graunke
9cd69022d5 i965: Change INTEL_DEBUG=vec4 to INTEL_SCALAR_VS for consistency.
We moved to INTEL_SCALAR_* when we added more than a single stage, but
never went back and converted the VS to work that way.  Be consistent.

Also update the documentation to actually mention these debug variables.

Acked-by: Jason Ekstrand <jason@jlekstrand.net>
2017-06-05 23:32:40 -07:00
Dave Airlie
2890a71158 radv: expose integrated device type for APUs.
This just sets the vulkan device type depending on whether
this is an APU or GPU.

Signed-off-by: Dave Airlie <airlied@redhat.com>
Fixes: f4e499ec79 "radv: add initial non-conformant radv vulkan driver"
2017-06-06 12:48:57 +10:00
Bas Nieuwenhuizen
ecdace80f4 ac/surface: Fix HTILE for radv.
We always compute HTILE size using addrlib, even when not TC compatible.

Signed-off-by: Bas Nieuwenhuizen <basni@google.com>
Reviewed-by: Dave Airlied <airlied@redhat.com>
2017-06-06 03:17:02 +02:00
Dave Airlie
0e72dea46f radv: fix write event eop on vega.
Typo here, fixes command submission hangs on vega
2017-06-06 10:43:19 +10:00
Dave Airlie
65477bae9c radv: enable GFX9 on radv
I'm open to reverting this closer to release if bad things
happen, but it might be easier to debugging to leave it for now.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2017-06-06 09:44:26 +10:00
Dave Airlie
c07eb1823f radv: turn off geom/tess for gfx9.
We don't support these yet, and it'll take a bit of work to do so.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2017-06-06 09:44:18 +10:00
Dave Airlie
348f63623b radv: misc GFX9 changes.
These are just some register changes ported from radeonsi for gfx9.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2017-06-06 09:44:10 +10:00
Dave Airlie
289de9f945 radv: add some GFX9 specific events.
These are ported from radeonsi, don't know all the rules for
when they should be inserted.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2017-06-06 09:44:00 +10:00