As Box::into_raw() is called when adding a job, we need to call
Box::from_raw() so Rust recovers the track of the memory, avoiding a
leak.
Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>
Backport-to: 26.1
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/42319>
nir_opt_vectorize compares phi sources using component 0
after chasing through movs. For multi-component phi sources, that first
component may not represent the whole source: it can be constant while
other components are not, or it can come from a different component range.
Reject multi-component phi sources unless all chased components are
constants, or come from the same def within the same max-vector component
range.
Fixes OpenCL-CTS test test_select.
Fixes: 6b611dbe ("nir/opt_vectorize: add support for phi nodes")
Signed-off-by: Ahmed Hesham <ahmed.hesham@arm.com>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Acked-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40820>
If this would be the first time the shim has been initialized, then
drm_shim_fd_lookup() would return NULL, so skip the init_shim().
init_shim() uses malloc, so it can't be called during jemalloc
initialization.
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38350>
This is to avoid a situation where jemalloc initialization calls
readlink(), which then tries to use malloc during init_shim().
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38350>
Introduces GPU hang detection via the feedback handler in MTLCommitOptions.
The issue is that even if the GPU hangs, the queue will be moved forward
signaling all semaphores/fences before the callback is executed. This leads
to reporting device lost later than the ideal fence wait for the
submission. If we want to accomplish this, we would have to move fence
signaling to the callback which would slow down GPU execution. Maybe
provide a way to configure this if the user really wants to pin-point when
the hang happens in the future.
Signed-off-by: Aitor Camacho <aitor@lunarg.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/42334>
I simply added the new `Crash` and failed to noticed it was a `Fail` previously
and not a `Pass`, and as such I should've updated the existing line instead of
adding a new one.
Fixes: dc1db5367e ("nvk/ci: document fixed tests, new failures, and recent flakes")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/42373>
Sliced 3D storage views now work on both Bifrost and Valhall, so
advertise the extension.
Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/42322>
Same goal as on Valhall, but Bifrost reaches a storage image through an
attribute buffer instead of a texture descriptor. Reuse panvk_storage_pview()
to build the sliced view, then point the attribute buffer at its first slice
and limit its depth to the slice count.
Views without slicing keep the full depth and are not affected.
Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/42322>
A sliced 3D view must only expose its own Z slices when used as a storage
image. On Valhall a storage image is read through a texture descriptor,
so restrict that descriptor to the view's slice range.
Views without slicing keep the full depth and are not affected.
Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/42322>
VK_EXT_image_sliced_view_of_3d needs a 3D view to describe a range of Z
slices, and pan_image_view had nowhere to store it. Rename first_layer
and last_layer to first_layer_or_z_slice and last_layer_or_z_slice and
keep a 3D view's Z slice range there, so all descriptor code reads it
from one place.
A 3D view uses its full range by default, so existing views behave as
before.
Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/42322>
RTI (ray tracing inspector) is a GUI for inspecting acceleration
structures and ray tracing dispatches. There are some general classes
for application lifetime, gpu resource managment and rendering. The
visualization and BVH/node info needs to be implemented by
driver/hardware specific backends (By overriding the virtual functions
in rti_file_view).
Reviewed-by: Natalie Vock <natalie.vock@gmx.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41806>
The whole point of this command is to inline the data
in the command buffer for faster transfers.
This patch use I2M if the last sub channel is 3D or Compute to avoid a
sub channel switch. We also only use I2M for transfer smaller or equal
to 2012 bytes (matching the current limit of nvk_cmd_buffer_push)
Signed-off-by: Mary Guillemard <mary@mary.zone>
Tested-by: Thomas H.P. Andersen <phomes@gmail.com>
Reviewed-by: Mel Henning <mhenning@darkrefraction.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/42257>
On macOS 26, some of the math for setting the index buffer length
draw register is missing for indirect draws, resulting in robustness
failures. Work around this by handling robustness ourselves.
On macOS 26 and 27 beta, index robustness does not work for buffers
that are not 32-bit aligned. Handle these ourselves.
Reviewed-by: Aitor Camacho <aitor@lunarg.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/42354>
If GNU Binutils is configured with --enable-error-rwx-segments=yes, the
linker will error out on RWX segments by default, which causes problems for
32-bit when -Dglx-read-only-text=false in:
* src/glx/libGLX_mesa.so
* src/gallium/targets/dri/libgallium.so
Pass -Wl,--no-fatal-rwx-sections if supported by the linker accordingly
for that case.
This is the same issue as mentioned in 39408229b50 ("ci: make linker warnings fatal").
cc: mesa-stable
Signed-off-by: Sam James <sam@gentoo.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33727>
The outer condition is fixed to check correctly whether any sign-extended
bit is used.
The inner condition was supposed to check whether src2 is constant.
Fixes: 7d24a9b649 - nir: handle ibfe/ubfe in nir_def_bits_used
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41908>
The following cases are optimized.
Pathological indirect load case:
Before:
output[direct_index] = a;
--- next shader ---
b = input[indirect_index];
After:
output[0] = a;
--- next shader ---
b = input[0];
Pathological indirect store case:
Before:
output[indirect_index] = a;
--- next shader ---
b = input[direct_index];
After:
if (indirect_index == direct_index)
output[0] = a;
--- next shader ---
b = input[0];
Acked-by: Georg Lehmann <dadschoorse@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41681>
This strengthens dead IO elimination for indirect IO.
The following case is now handled:
Producer:
output[0] = ...
a = output[i]; // indirect output load
b = output[2]; // dead, the producer writes output[0], not output[2]
Consumer:
c = input[2]; // dead, the producer writes output[0], not output[2]
Previously, the indirect output load would prevent any input elimination
in the consumer. With better per-element tracking, we can determine
that element 2 is indeed not written by the producer and remove all
the dead loads.
Acked-by: Georg Lehmann <dadschoorse@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41681>
The bound check only checked for the dynamic offset and ignored the
constant base one. This fixes the bound check, but also simulates 32-bit
overflow semantics due to the ldcx offset being 32 bits as well.
Backport-To: 26.1
Reviewed-by: Mel Henning <mhenning@darkrefraction.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/42337>
The pre Turing lowering path of load_global_constant_offset compared the
offset and size with ilt, but we need an unsigned check as offset can be
arbitrary and follows unsigned semantics.
When lowering non-uniform ldcx we also have to compare with ult for the
same reasons.
Assisted-by: Claude
Backport-to: *
Reviewed-by: Mel Henning <mhenning@darkrefraction.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/42337>
So your MR crashes CI jobs on hardware you've never heard of, let alone
have sitting on your desk. This page explains how to reproduce those CI
jobs with drm-shim.
Signed-off-by: Valentine Burley <valentine.burley@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41959>
This configures bin/drm-shim.py as 'drm-shim' and prepends its build
location to the devenv PATH so it can be executed easily.
Signed-off-by: Valentine Burley <valentine.burley@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41959>
The initial flake list introduced pointed to specific tests, but we face other
tests in the same family quite often. It is better to transform this to
regular expressions to group them better.
Signed-off-by: Sergi Blanch Torne <sergi.blanch.torne@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/42238>
Only x86/x86_64 systems can have integrated r300 chipsets that
require software vertex processing through draw. Other supported systems
use discrete r300/r500 cards with hardware TCL, so they should not need
LLVM just to build r300.
Keep requiring LLVM by default for x86-family r300 builds so distro builds
continue to support those integrated chipsets. If a user explicitly disables
LLVM or draw LLVM, allow the build but warn that integrated chipsets
requiring software vertex processing will be slow.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/42085>
