fdo-mirrors/mesa
1
0
Fork 0
mirror of https://gitlab.freedesktop.org/mesa/mesa.git synced 2026-05-08 13:28:06 +02:00
Code Issues Projects Releases Packages Wiki Activity Actions 1
202202 commits 66 branches 934 tags 937 MiB
Commit graph

202202 commits

This branch
This branch
All branches
Author SHA1 Message Date
Natalie Vock
40b0ad0f45 vulkan/bvh: Move leaf builder code to header 
Reviewed-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32797>
 2025-02-18 13:00:52 +00:00
Rhys Perry
d2907d271e ac/nir: set higher alignment for some swizzled store_buffer_amd 
No fossil-db changes (navi31, navi21, polaris10).

fossil-db (vega10):
Totals from 37 (0.06% of 62962) affected shaders:
MaxWaves: 189 -> 180 (-4.76%)
Instrs: 45607 -> 45616 (+0.02%); split: -0.16%, +0.18%
CodeSize: 241980 -> 234908 (-2.92%)
VGPRs: 2524 -> 2784 (+10.30%)
Latency: 152476 -> 151948 (-0.35%); split: -0.38%, +0.03%
InvThroughput: 74441 -> 78360 (+5.26%); split: -0.21%, +5.47%
VClause: 902 -> 1044 (+15.74%); split: -1.55%, +17.29%
Copies: 4989 -> 6745 (+35.20%)
PreVGPRs: 2044 -> 2334 (+14.19%)
VALU: 31634 -> 33389 (+5.55%)
SALU: 2601 -> 2602 (+0.04%)
VMEM: 5774 -> 3991 (-30.88%)

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33531>
 2025-02-18 12:31:19 +00:00
Rhys Perry
8fd862499a ac/nir: don't cross swizzle elements when vectorizing buffer_amd intrinsic 
This can happen for mesh shader outputs.

No fossil-db changes (navi31, navi21, polaris10).

fossil-db (vega10):
Totals from 37 (0.06% of 62962) affected shaders:
MaxWaves: 183 -> 189 (+3.28%)
Instrs: 45037 -> 45607 (+1.27%); split: -0.09%, +1.36%
CodeSize: 231472 -> 241980 (+4.54%)
VGPRs: 2656 -> 2524 (-4.97%)
Latency: 151199 -> 152476 (+0.84%); split: -0.02%, +0.87%
InvThroughput: 75148 -> 74441 (-0.94%); split: -1.44%, +0.50%
VClause: 882 -> 902 (+2.27%); split: -4.31%, +6.58%
Copies: 6465 -> 4989 (-22.83%)
PreVGPRs: 2265 -> 2044 (-9.76%)
VALU: 33109 -> 31634 (-4.45%)
SALU: 2602 -> 2601 (-0.04%)
VMEM: 3711 -> 5774 (+55.59%)

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Fixes: c3d27906d8 ("radv: vectorize lowered shader IO")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33531>
 2025-02-18 12:31:19 +00:00
David Rosca
ebd8893710 radv/video: Move IB header from begin/end to encode_video 
For decode this is also done in decode_video.

This breaks if app doesn't call vkCmdEncodeVideoKHR before end, eg:

  vkCmdBeginVideoCodingKHR
  vkCmdControlVideoCodingKHR
  vkCmdEndVideoCodingKHR

Cc: mesa-stable
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33582>
 2025-02-18 11:12:22 +00:00
David Rosca
77ff18aa3b radv/video: Fix setting balanced preset for HEVC encode with SAO enabled 
FW disables SAO in speed preset, so we need to switch to balanced.

Cc: mesa-stable
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/12615
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33582>
 2025-02-18 11:12:22 +00:00
Danylo Piliaiev
49191f46e6 tu/a6xx: Emit VSC addresses for each bin to restore after preemption 
KGSL unconditionally supports preemption so we cannot ignore it.

On a6xx, we have to emit VSC addresses per-bin or make the amble include
these registers, because CP_SET_BIN_DATA5_OFFSET will use the
register instead of the pseudo register and its value won't survive
across preemptions. The blob seems to take the second approach and
emits the preamble lazily. We chose the per-bin approach but blob's
should be a better one.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/12627

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33580>
 2025-02-18 10:23:09 +00:00
Samuel Pitoiset
9427df23b4 radv: use radv_image::bindings::addr more 
Also remove radv_image::bindings::offset.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33524>
 2025-02-18 09:49:14 +01:00
Samuel Pitoiset
066467cf98 radv: compute radv_image::bindings::addr at bind time 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33524>
 2025-02-18 09:47:24 +01:00
Samuel Pitoiset
f234099d6d radv: rename radv_image::bindings::bo_va to addr 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33524>
 2025-02-18 09:47:24 +01:00
Samuel Pitoiset
0f8b3bf489 radv: remove redundant zero initialization when creating images 
The struct is already zero-allocated.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33524>
 2025-02-18 09:47:24 +01:00
Samuel Pitoiset
63b5bce396 radv: stop using image binding offset when exporting BO metadata 
The offset must be zero for dedicated allocations.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33524>
 2025-02-18 09:47:23 +01:00
Samuel Pitoiset
50851f17d1 radv/meta: remove the buffer dependency for image copy operations 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33526>
 2025-02-18 08:40:30 +01:00
Samuel Pitoiset
ae5d2bfd36 radv/meta: use radv_copy_memory() instead of radv_copy_buffer() 
To remove the buffer dependency.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33526>
 2025-02-18 08:40:30 +01:00
Samuel Pitoiset
70bd4fe621 radv/meta: pass the buffer addr to SDMA image buffer copy operations 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33526>
 2025-02-18 08:40:30 +01:00
Samuel Pitoiset
6e2da49e92 radv/meta: add BOs to cmdbuf list earlier for image copy operations 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33526>
 2025-02-18 08:40:30 +01:00
Samuel Pitoiset
e0070bc68b radv: fix adding the VRS image BO to the cmdbuf list on GFX11 
This might cause random faults.

Cc: mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33584>
 2025-02-18 07:13:07 +00:00
Tapani Pälli
d8381415a6 anv: tighten condition for changing barrier layouts 
Assertion (or attempting the layout change) is causing crash when
launching Steel Rats. Tighten the condition for change so that it should
affect only when runtime has made changes.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/12602
Fixes: eed788213b ("anv: ensure consistent layout transitions in render passes")
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33523>
 2025-02-18 06:30:14 +00:00
Vasily Khoruzhick
b6fba15bd7 lima: ppir: duplicate fneg and fabs if its source is an intrinsic 
fneg and fabs are folded later in ppir, but having them in nir as a
separate instructions prevents duplicate_intrinsics pass from duplicating
load_input and load_uniform. Duplicate fneg and fabs, so subsequent
duplicate_intrinsic pass can duplicate the loads

shader-db:

total instructions in shared programs: 27698 -> 27675 (-0.08%)
instructions in affected programs: 2752 -> 2729 (-0.84%)
helped: 21
HURT: 2
helped stats (abs) min: 1 max: 4 x̄: 1.19 x̃: 1
helped stats (rel) min: 0.38% max: 6.67% x̄: 2.75% x̃: 0.75%
HURT stats (abs)   min: 1 max: 1 x̄: 1.00 x̃: 1
HURT stats (rel)   min: 1.89% max: 1.89% x̄: 1.89% x̃: 1.89%
95% mean confidence interval for instructions value: -1.39 -0.61
95% mean confidence interval for instructions %-change: -3.67% -1.03%
Instructions are helped.

total loops in shared programs: 2 -> 2 (0.00%)
loops in affected programs: 0 -> 0
helped: 0
HURT: 0

total spills in shared programs: 372 -> 368 (-1.08%)
spills in affected programs: 27 -> 23 (-14.81%)
helped: 4
HURT: 0

total fills in shared programs: 1224 -> 1205 (-1.55%)
fills in affected programs: 81 -> 62 (-23.46%)
helped: 4
HURT: 0

LOST:   0
GAINED: 0

Reviewed-by: Erico Nunes <nunes.erico@gmail.com>
Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33569>
 2025-02-18 02:38:26 +00:00
Faith Ekstrand
86e217e7df nvk: Implement descriptorBufferPushDescriptors 
The only thing we really need to do here is to make sure we don't try
to use the EDB path for push descriptors since those aren't really
descriptor buffers.

Backport-to: 25.0
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33589>
 2025-02-17 23:38:17 +00:00
José Roberto de Souza
7d4c91efef intel/dev: Call intel_device_info_update_after_hwconfig() from common code 
Avoid backends duplication.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33585>
 2025-02-17 20:52:31 +00:00
José Roberto de Souza
e170252d97 intel/dev: Improve max_cs_threads documentation 
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33585>
 2025-02-17 20:52:31 +00:00
Vasily Khoruzhick
dde084d688 lima: ppir: use combiner unit for mul 
Combiner unit runs after fmul/smul/fadd/sadd units and it can consume
the results that previous units wrote to the registers. So prefer
placing scalar mul into combiner unit and predecessors (if any)
into other units

shader-db:

total instructions in shared programs: 29072 -> 27698 (-4.73%)
instructions in affected programs: 11237 -> 9863 (-12.23%)
helped: 163
HURT: 0
helped stats (abs) min: 1 max: 42 x̄: 8.43 x̃: 4
helped stats (rel) min: 0.64% max: 30.00% x̄: 13.03% x̃: 11.76%
95% mean confidence interval for instructions value: -9.89 -6.96
95% mean confidence interval for instructions %-change: -14.09% -11.97%
Instructions are helped.

total loops in shared programs: 2 -> 2 (0.00%)
loops in affected programs: 0 -> 0
helped: 0
HURT: 0

total spills in shared programs: 367 -> 372 (1.36%)
spills in affected programs: 16 -> 21 (31.25%)
helped: 1
HURT: 2

total fills in shared programs: 1208 -> 1224 (1.32%)
fills in affected programs: 51 -> 67 (31.37%)
helped: 2
HURT: 2

LOST:   0
GAINED: 0

Reviewed-by: Erico Nunes <nunes.erico@gmail.com>
Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33568>
 2025-02-17 12:25:01 -08:00
Vasily Khoruzhick
bc9fca2fb1 lima: ppir: add codegen for mov and mul on combiner unit 
Combiner unit support scalar by vector multiplication and scalar mov.
Implement it for codegen

Reviewed-by: Erico Nunes <nunes.erico@gmail.com>
Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33568>
 2025-02-17 12:25:01 -08:00
Vasily Khoruzhick
5937d12d29 lima: ppir: assert on unexpected pipeline dest for fmul and vmul 
Assert on unexpected pipeline dest for fmul and vmul to catch scheduler
bugs early

Reviewed-by: Erico Nunes <nunes.erico@gmail.com>
Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33540>
 2025-02-17 19:51:30 +00:00
Vasily Khoruzhick
c6c37b516d lima: ppir: fix diassembling atan and combiner codegen definition 
Fix multiple issues with atan in disassembler:

- arg1_en field in combiner unit actually seems to be a bit indicating
  that one of sources is vector (e.g. for atan_pt2, or multiplication)
- atan2 has 2 arguments, not one
- properly handle all instruction variants

Reviewed-by: Erico Nunes <nunes.erico@gmail.com>
Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33540>
 2025-02-17 19:51:30 +00:00
Vasily Khoruzhick
f90df9a39e lima: ppir: print index of the node that breaks node_to_instr 
Print index of the node that breaks node_to_instr to make debugging
easier

Reviewed-by: Erico Nunes <nunes.erico@gmail.com>
Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33540>
 2025-02-17 19:51:30 +00:00
Vasily Khoruzhick
7621f9beda lima: ppir: fixup src node when replacing src for select and load_reg 
Fixup src node when replacing src for select and load_reg

It doesn't affect compiler functionality, but affects printing ppir
representation.

Reviewed-by: Erico Nunes <nunes.erico@gmail.com>
Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33540>
 2025-02-17 19:51:30 +00:00
Vasily Khoruzhick
2ea27f41e3 lima: ppir: improve readability of ppir represantation dump 
Improve readability of ppir representation dump

- adopt "dest = op src1[, srcN]"
- use symbolic names of pipeline registers
- print destination writemask
- print destination modifier (if any)
- print source(s) swizzle
- print constants
- print load node base index
- print branch condition(s)

With these modifications it's actually possible to follow the program

-------block   0-------
 $0008 = mov ^texture ($0005) // NIR: new
  ($0005) ^texture = ld_tex ^discard ($0006).xyzx, $0004.xxxx // NIR: ssa4
    ($0006) ^discard = ld_coords_reg $0002.xyzx // NIR: new
       $0004.x = ld_var 0 // NIR: ssa6
       $0002.xyz = mov $0001.yzwx // NIR: ssa5
         $0001 = ld_var 0 // NIR: ssa7

Reviewed-by: Erico Nunes <nunes.erico@gmail.com>
Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33540>
 2025-02-17 19:51:30 +00:00
Eric Engestrom
8771762bcd llvmpipe/ci: drop fraction for asan tests that takes 1.5 min without fraction 
The fraction was making it run for only 10-12 seconds, which is wasteful
considering the huge overhead.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33581>
 2025-02-17 19:10:57 +00:00
Lionel Landwerlin
2361ed27f3 runtime: sort push constant layouts 
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33548>
 2025-02-17 18:39:53 +00:00
Danylo Piliaiev
97f851e7c5 tu: Handle mismatched mutability when resolving from GMEM 
Apparently fast path cannot handle mismatched mutability and we
should use CP_BLIT which has SP_PS_2D_SRC_INFO.MUTABLEEN to signal
src mutability. Previously it was partially handled by
tu_attachment_store_mismatched_swap.

Fixes: a104a7ca1a
("tu: Handle non-identity GMEM swaps when resolving")

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33514>
 2025-02-17 17:56:17 +00:00
Danylo Piliaiev
4c918603e0 freedreno/fdl: Log mutability when dumping layout 
Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33514>
 2025-02-17 17:56:17 +00:00
Danylo Piliaiev
bdf0f61d4a tu: Get correct src view when storing gmem attachment 
Fixes: a104a7ca1a
("tu: Handle non-identity GMEM swaps when resolving")

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33514>
 2025-02-17 17:56:17 +00:00
Samuel Pitoiset
7b5efb4c0b radv: remove radv_buffer_view_{init,finish}() helpers 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33505>
 2025-02-17 16:53:28 +01:00
Samuel Pitoiset
3c98a336cf radv: remove radv_buffer_{init,finish}() helpers 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33505>
 2025-02-17 16:53:08 +01:00
Samuel Pitoiset
84ba15eb05 radv/meta: switch to descriptor buffers 
The main advantage is to use BDA for texel buffer descriptors.
It might also be slightly faster on the CPU.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33505>
 2025-02-17 16:52:49 +01:00
Samuel Pitoiset
bb7f86a9e4 vulkan: add descriptor buffer support to compute astc decoder 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33505>
 2025-02-17 15:03:43 +01:00
Kenneth Graunke
e65c1473de nir: Eliminate dead writes to shared memory at the end of the program 
If the program writes to shared variables after all reads, in the last
block of the program, no one will ever read the value we write.  We can
just eliminate these dead writes.

(Thanks to Faith Ekstrand for improving the ends_program() conditions.)

Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33452>
 2025-02-17 12:46:07 +00:00
Samuel Pitoiset
9af11bf306 radv: add initial DCC support on GFX12 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33255>
 2025-02-17 12:03:09 +00:00
Samuel Pitoiset
827cef7f7f ac/gpu_info: add gfx12_supports_dcc_write_compress_disable 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33255>
 2025-02-17 12:03:09 +00:00
Valentine Burley
53c1b15f53 anv/ci: Don't start X11 for ANGLE 
This is no longer required.

Also document a flake seen recently.

Signed-off-by: Valentine Burley <valentine.burley@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33578>
 2025-02-17 11:31:01 +00:00
Valentine Burley
72b8ba4851 radv/ci: Don't start X11 for ANGLE 
This is no longer required.

Signed-off-by: Valentine Burley <valentine.burley@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33578>
 2025-02-17 11:31:01 +00:00
Yiwei Zhang
0b908bb27e venus: updated to use core types for promoted extensions 
Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33567>
 2025-02-17 10:46:35 +00:00
Yiwei Zhang
207c9ec65a venus: sync protocol for v1.4.307 release and update promoted entries 
Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33567>
 2025-02-17 10:46:35 +00:00
Yiwei Zhang
ae2830e520 venus: drop unused codes 
Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33567>
 2025-02-17 10:46:34 +00:00
Konstantin Seurer
af375c6756 radv: Optimize fs builtins using static gfx state 
The values of some builtins are known at compile time when the
application creates pipelines with static state.

Stats for graphics pipelines:

Totals from 568 (0.71% of 80536) affected shaders:
MaxWaves: 12364 -> 12502 (+1.12%); split: +1.26%, -0.15%
Instrs: 515696 -> 501182 (-2.81%); split: -2.85%, +0.04%
CodeSize: 2815736 -> 2741464 (-2.64%); split: -2.69%, +0.05%
VGPRs: 29528 -> 29160 (-1.25%); split: -1.71%, +0.46%
SpillSGPRs: 212 -> 215 (+1.42%)
Latency: 5515421 -> 5409125 (-1.93%); split: -2.05%, +0.13%
InvThroughput: 1293512 -> 1277913 (-1.21%); split: -1.27%, +0.06%
VClause: 10570 -> 10295 (-2.60%); split: -2.74%, +0.14%
SClause: 19040 -> 18531 (-2.67%); split: -2.83%, +0.16%
Copies: 37189 -> 35431 (-4.73%); split: -5.31%, +0.58%
Branches: 11391 -> 11070 (-2.82%); split: -2.92%, +0.11%
PreSGPRs: 27848 -> 27313 (-1.92%); split: -1.95%, +0.03%
PreVGPRs: 24847 -> 24106 (-2.98%); split: -3.00%, +0.02%
VALU: 359356 -> 348779 (-2.94%); split: -2.97%, +0.03%
SALU: 59135 -> 57448 (-2.85%); split: -3.11%, +0.26%
VMEM: 14674 -> 14313 (-2.46%)
SMEM: 30901 -> 30342 (-1.81%); split: -1.84%, +0.03%

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32793>
 2025-02-17 09:45:15 +00:00
Valentine Burley
bbfbd16580 turnip/ci: Add a nightly ANGLE job on a750 
Signed-off-by: Valentine Burley <valentine.burley@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33542>
 2025-02-17 09:07:48 +00:00
Valentine Burley
bd2563eb02 turnip/ci: Rename valve-freedreno-turnip-manual-rules 
The valve-freedreno-turnip-manual-rules naming would suggest
freedreno + turnip rules, but in fact this rule is meant to only
impact turnip.
Change the name to match .google-turnip-manual-rules and
.collabora-turnip-manual-rules.

Signed-off-by: Valentine Burley <valentine.burley@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33542>
 2025-02-17 09:07:48 +00:00
Valentine Burley
612f56cb5e ci/container: Include ANGLE in the arm64 test-gl container 
Build ANGLE in the arm64 test-gl containers.

Signed-off-by: Valentine Burley <valentine.burley@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33542>
 2025-02-17 09:07:48 +00:00
Valentine Burley
45fe200222 turnip/ci: Add nightly ANGLE jobs on a618 and a660 
Signed-off-by: Valentine Burley <valentine.burley@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33542>
 2025-02-17 09:07:48 +00:00