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radv: use radv_image::bindings::addr more

Browse source 
Also remove radv_image::bindings::offset.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33524>
This commit is contained in:
Samuel Pitoiset 2025-02-11 17:55:52 +01:00
parent 066467cf98
commit 9427df23b4
14 changed files with 108 additions and 127 deletions
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123
src/amd/vulkan/meta/radv_meta_bufimage.c
View file

@ -663,10 +663,10 @@ fixup_gfx9_cs_copy(struct radv_cmd_buffer *cmd_buffer, const struct radv_meta_bl
uint32_t x = (coordY < hw_mip_extent.height) ? hw_mip_extent.width : 0;
for (; x < mip_extent.width; x++) {
uint32_t coordX = x + mip_offset.x;
uint64_t addr = ac_surface_addr_from_coord(pdev->addrlib, gpu_info, surf, &surf_info, mip_level, coordX,
coordY, img_bsurf->layer, image->vk.image_type == VK_IMAGE_TYPE_3D);
struct radeon_winsys_bo *img_bo = image->bindings[0].bo;
const uint64_t img_va = radv_buffer_get_va(img_bo) + image->bindings[0].offset + addr;
uint64_t img_offset =
ac_surface_addr_from_coord(pdev->addrlib, gpu_info, surf, &surf_info, mip_level, coordX, coordY,
img_bsurf->layer, image->vk.image_type == VK_IMAGE_TYPE_3D);
const uint64_t img_va = image->bindings[0].addr + img_offset;
/* buf_bsurf->offset already includes the layer offset */
const uint64_t mem_va = buf_bsurf->addr + buf_bsurf->offset + y * buf_bsurf->pitch * surf->bpe + x * surf->bpe;
if (to_image) {
@ -766,29 +766,28 @@ radv_meta_buffer_to_image_cs_r32g32b32(struct radv_cmd_buffer *cmd_buffer, struc
radv_meta_bind_descriptors(
cmd_buffer, VK_PIPELINE_BIND_POINT_COMPUTE, layout, 2,
(VkDescriptorGetInfoEXT[]){
{
.sType = VK_STRUCTURE_TYPE_DESCRIPTOR_GET_INFO_EXT,
.type = VK_DESCRIPTOR_TYPE_UNIFORM_TEXEL_BUFFER,
.data.pUniformTexelBuffer =
&(VkDescriptorAddressInfoEXT){
.sType = VK_STRUCTURE_TYPE_DESCRIPTOR_ADDRESS_INFO_EXT,
.address = src->addr + src->offset,
.range = src->size - src->offset,
.format = src->format,
},
},
{
.sType = VK_STRUCTURE_TYPE_DESCRIPTOR_GET_INFO_EXT,
.type = VK_DESCRIPTOR_TYPE_STORAGE_TEXEL_BUFFER,
.data.pStorageTexelBuffer =
&(VkDescriptorAddressInfoEXT){
.sType = VK_STRUCTURE_TYPE_DESCRIPTOR_ADDRESS_INFO_EXT,
.address = radv_buffer_get_va(dst->image->bindings[0].bo) + dst->image->bindings[0].offset,
.range = dst->image->size,
.format = get_r32g32b32_format(dst->format),
},
}});
(VkDescriptorGetInfoEXT[]){{
.sType = VK_STRUCTURE_TYPE_DESCRIPTOR_GET_INFO_EXT,
.type = VK_DESCRIPTOR_TYPE_UNIFORM_TEXEL_BUFFER,
.data.pUniformTexelBuffer =
&(VkDescriptorAddressInfoEXT){
.sType = VK_STRUCTURE_TYPE_DESCRIPTOR_ADDRESS_INFO_EXT,
.address = src->addr + src->offset,
.range = src->size - src->offset,
.format = src->format,
},
},
{
.sType = VK_STRUCTURE_TYPE_DESCRIPTOR_GET_INFO_EXT,
.type = VK_DESCRIPTOR_TYPE_STORAGE_TEXEL_BUFFER,
.data.pStorageTexelBuffer =
&(VkDescriptorAddressInfoEXT){
.sType = VK_STRUCTURE_TYPE_DESCRIPTOR_ADDRESS_INFO_EXT,
.address = dst->image->bindings[0].addr,
.range = dst->image->size,
.format = get_r32g32b32_format(dst->format),
},
}});
radv_CmdBindPipeline(radv_cmd_buffer_to_handle(cmd_buffer), VK_PIPELINE_BIND_POINT_COMPUTE, pipeline);
@ -893,29 +892,28 @@ radv_meta_image_to_image_cs_r32g32b32(struct radv_cmd_buffer *cmd_buffer, struct
radv_meta_bind_descriptors(
cmd_buffer, VK_PIPELINE_BIND_POINT_COMPUTE, layout, 2,
(VkDescriptorGetInfoEXT[]){
{
.sType = VK_STRUCTURE_TYPE_DESCRIPTOR_GET_INFO_EXT,
.type = VK_DESCRIPTOR_TYPE_UNIFORM_TEXEL_BUFFER,
.data.pUniformTexelBuffer =
&(VkDescriptorAddressInfoEXT){
.sType = VK_STRUCTURE_TYPE_DESCRIPTOR_ADDRESS_INFO_EXT,
.address = radv_buffer_get_va(src->image->bindings[0].bo) + src->image->bindings[0].offset,
.range = src->image->size,
.format = get_r32g32b32_format(src->format),
},
},
{
.sType = VK_STRUCTURE_TYPE_DESCRIPTOR_GET_INFO_EXT,
.type = VK_DESCRIPTOR_TYPE_STORAGE_TEXEL_BUFFER,
.data.pStorageTexelBuffer =
&(VkDescriptorAddressInfoEXT){
.sType = VK_STRUCTURE_TYPE_DESCRIPTOR_ADDRESS_INFO_EXT,
.address = radv_buffer_get_va(dst->image->bindings[0].bo) + dst->image->bindings[0].offset,
.range = dst->image->size,
.format = get_r32g32b32_format(dst->format),
},
}});
(VkDescriptorGetInfoEXT[]){{
.sType = VK_STRUCTURE_TYPE_DESCRIPTOR_GET_INFO_EXT,
.type = VK_DESCRIPTOR_TYPE_UNIFORM_TEXEL_BUFFER,
.data.pUniformTexelBuffer =
&(VkDescriptorAddressInfoEXT){
.sType = VK_STRUCTURE_TYPE_DESCRIPTOR_ADDRESS_INFO_EXT,
.address = src->image->bindings[0].addr,
.range = src->image->size,
.format = get_r32g32b32_format(src->format),
},
},
{
.sType = VK_STRUCTURE_TYPE_DESCRIPTOR_GET_INFO_EXT,
.type = VK_DESCRIPTOR_TYPE_STORAGE_TEXEL_BUFFER,
.data.pStorageTexelBuffer =
&(VkDescriptorAddressInfoEXT){
.sType = VK_STRUCTURE_TYPE_DESCRIPTOR_ADDRESS_INFO_EXT,
.address = dst->image->bindings[0].addr,
.range = dst->image->size,
.format = get_r32g32b32_format(dst->format),
},
}});
radv_CmdBindPipeline(radv_cmd_buffer_to_handle(cmd_buffer), VK_PIPELINE_BIND_POINT_COMPUTE, pipeline);
@ -1038,19 +1036,18 @@ radv_meta_clear_image_cs_r32g32b32(struct radv_cmd_buffer *cmd_buffer, struct ra
radv_cs_add_buffer(device->ws, cmd_buffer->cs, dst->image->bindings[0].bo);
radv_meta_bind_descriptors(
cmd_buffer, VK_PIPELINE_BIND_POINT_COMPUTE, layout, 1,
(VkDescriptorGetInfoEXT[]){{
.sType = VK_STRUCTURE_TYPE_DESCRIPTOR_GET_INFO_EXT,
.type = VK_DESCRIPTOR_TYPE_STORAGE_TEXEL_BUFFER,
.data.pStorageTexelBuffer =
&(VkDescriptorAddressInfoEXT){
.sType = VK_STRUCTURE_TYPE_DESCRIPTOR_ADDRESS_INFO_EXT,
.address = radv_buffer_get_va(dst->image->bindings[0].bo) + dst->image->bindings[0].offset,
.range = dst->image->size,
.format = get_r32g32b32_format(dst->format),
},
}});
radv_meta_bind_descriptors(cmd_buffer, VK_PIPELINE_BIND_POINT_COMPUTE, layout, 1,
(VkDescriptorGetInfoEXT[]){{
.sType = VK_STRUCTURE_TYPE_DESCRIPTOR_GET_INFO_EXT,
.type = VK_DESCRIPTOR_TYPE_STORAGE_TEXEL_BUFFER,
.data.pStorageTexelBuffer =
&(VkDescriptorAddressInfoEXT){
.sType = VK_STRUCTURE_TYPE_DESCRIPTOR_ADDRESS_INFO_EXT,
.address = dst->image->bindings[0].addr,
.range = dst->image->size,
.format = get_r32g32b32_format(dst->format),
},
}});
radv_CmdBindPipeline(radv_cmd_buffer_to_handle(cmd_buffer), VK_PIPELINE_BIND_POINT_COMPUTE, pipeline);

23
src/amd/vulkan/meta/radv_meta_clear.c
View file

@ -552,10 +552,9 @@ get_clear_htile_mask_pipeline(struct radv_device *device, VkPipeline *pipeline_o
static uint32_t
clear_htile_mask(struct radv_cmd_buffer *cmd_buffer, const struct radv_image *image, struct radeon_winsys_bo *bo,
uint64_t offset, uint64_t size, uint32_t htile_value, uint32_t htile_mask)
uint64_t va, uint64_t size, uint32_t htile_value, uint32_t htile_mask)
{
struct radv_device *device = radv_cmd_buffer_device(cmd_buffer);
const uint64_t va = radv_buffer_get_va(bo) + offset;
uint64_t block_count = DIV_ROUND_UP(size, 1024);
struct radv_meta_saved_state saved_state;
VkPipelineLayout layout;
@ -811,7 +810,7 @@ radv_clear_cmask(struct radv_cmd_buffer *cmd_buffer, struct radv_image *image, c
size = slice_size * vk_image_subresource_layer_count(&image->vk, range);
}
return radv_fill_buffer(cmd_buffer, image, image->bindings[0].bo, radv_image_get_va(image, 0) + cmask_offset, size,
return radv_fill_buffer(cmd_buffer, image, image->bindings[0].bo, image->bindings[0].addr + cmask_offset, size,
value);
}
@ -829,7 +828,7 @@ radv_clear_fmask(struct radv_cmd_buffer *cmd_buffer, struct radv_image *image, c
fmask_offset += slice_size * range->baseArrayLayer;
size = slice_size * vk_image_subresource_layer_count(&image->vk, range);
return radv_fill_buffer(cmd_buffer, image, image->bindings[0].bo, radv_image_get_va(image, 0) + fmask_offset, size,
return radv_fill_buffer(cmd_buffer, image, image->bindings[0].bo, image->bindings[0].addr + fmask_offset, size,
value);
}
@ -877,8 +876,8 @@ radv_clear_dcc(struct radv_cmd_buffer *cmd_buffer, struct radv_image *image, con
if (!size)
continue;
flush_bits |= radv_fill_buffer(cmd_buffer, image, image->bindings[0].bo, radv_image_get_va(image, 0) + dcc_offset,
size, value);
flush_bits |=
radv_fill_buffer(cmd_buffer, image, image->bindings[0].bo, image->bindings[0].addr + dcc_offset, size, value);
}
return flush_bits;
@ -1098,11 +1097,11 @@ radv_clear_htile(struct radv_cmd_buffer *cmd_buffer, const struct radv_image *im
if (htile_mask == UINT_MAX) {
/* Clear the whole HTILE buffer. */
flush_bits |= radv_fill_buffer(cmd_buffer, image, image->bindings[0].bo,
radv_image_get_va(image, 0) + htile_offset, size, value);
image->bindings[0].addr + htile_offset, size, value);
} else {
/* Only clear depth or stencil bytes in the HTILE buffer. */
flush_bits |= clear_htile_mask(cmd_buffer, image, image->bindings[0].bo,
image->bindings[0].offset + htile_offset, size, value, htile_mask);
image->bindings[0].addr + htile_offset, size, value, htile_mask);
}
}
} else {
@ -1113,12 +1112,12 @@ radv_clear_htile(struct radv_cmd_buffer *cmd_buffer, const struct radv_image *im
if (htile_mask == UINT_MAX) {
/* Clear the whole HTILE buffer. */
flush_bits = radv_fill_buffer(cmd_buffer, image, image->bindings[0].bo,
radv_image_get_va(image, 0) + htile_offset, size, value);
flush_bits = radv_fill_buffer(cmd_buffer, image, image->bindings[0].bo, image->bindings[0].addr + htile_offset,
size, value);
} else {
/* Only clear depth or stencil bytes in the HTILE buffer. */
flush_bits = clear_htile_mask(cmd_buffer, image, image->bindings[0].bo,
image->bindings[0].offset + htile_offset, size, value, htile_mask);
flush_bits = clear_htile_mask(cmd_buffer, image, image->bindings[0].bo, image->bindings[0].addr + htile_offset,
size, value, htile_mask);
}
}

2
src/amd/vulkan/meta/radv_meta_dcc_retile.c
View file

@ -134,7 +134,7 @@ radv_retile_dcc(struct radv_cmd_buffer *cmd_buffer, struct radv_image *image)
radv_CmdBindPipeline(radv_cmd_buffer_to_handle(cmd_buffer), VK_PIPELINE_BIND_POINT_COMPUTE, pipeline);
const uint64_t va = radv_buffer_get_va(image->bindings[0].bo) + image->bindings[0].offset;
const uint64_t va = image->bindings[0].addr;
radv_cs_add_buffer(device->ws, cmd_buffer->cs, image->bindings[0].bo);

2
src/amd/vulkan/meta/radv_meta_fast_clear.c
View file

@ -231,7 +231,7 @@ radv_emit_set_predication_state_from_image(struct radv_cmd_buffer *cmd_buffer, s
uint64_t va = 0;
if (value)
va = radv_image_get_va(image, 0) + pred_offset;
va = image->bindings[0].addr + pred_offset;
radv_emit_set_predication_state(cmd_buffer, true, PREDICATION_OP_BOOL64, va);
}

6
src/amd/vulkan/meta/radv_meta_fmask_copy.c
View file

@ -104,10 +104,8 @@ radv_fixup_copy_dst_metadata(struct radv_cmd_buffer *cmd_buffer, const struct ra
/* Copy CMASK+FMASK. */
size = src_image->planes[0].surface.cmask_size + src_image->planes[0].surface.fmask_size;
src_va = radv_buffer_get_va(src_image->bindings[0].bo) + src_image->bindings[0].offset +
src_image->planes[0].surface.fmask_offset;
dst_va = radv_buffer_get_va(dst_image->bindings[0].bo) + dst_image->bindings[0].offset +
dst_image->planes[0].surface.fmask_offset;
src_va = src_image->bindings[0].addr + src_image->planes[0].surface.fmask_offset;
dst_va = dst_image->bindings[0].addr + dst_image->planes[0].surface.fmask_offset;
radv_copy_buffer(cmd_buffer, src_image->bindings[0].bo, dst_image->bindings[0].bo, src_va, dst_va, size);
}

10
src/amd/vulkan/radv_cmd_buffer.c
View file

@ -4619,7 +4619,7 @@ radv_emit_framebuffer_state(struct radv_cmd_buffer *cmd_buffer)
radv_cs_add_buffer(device->ws, cmd_buffer->cs, vrs_image->bindings[0].bo);
va = radv_image_get_va(vrs_image, 0);
va = vrs_image->bindings[0].addr;
va |= vrs_image->planes[0].surface.tile_swizzle << 8;
xmax = vrs_iview->vk.extent.width - 1;
@ -9275,9 +9275,9 @@ radv_CmdBeginRendering(VkCommandBuffer commandBuffer, const VkRenderingInfo *pRe
uint32_t level = ds_iview->vk.base_mip_level;
/* HTILE buffer */
uint64_t htile_offset = ds_image->bindings[0].offset + ds_image->planes[0].surface.meta_offset +
ds_image->planes[0].surface.u.gfx9.meta_levels[level].offset;
const uint64_t htile_va = radv_buffer_get_va(ds_image->bindings[0].bo) + htile_offset;
uint64_t htile_offset =
ds_image->planes[0].surface.meta_offset + ds_image->planes[0].surface.u.gfx9.meta_levels[level].offset;
const uint64_t htile_va = ds_image->bindings[0].addr + htile_offset;
assert(render->area.offset.x + render->area.extent.width <= ds_image->vk.extent.width &&
render->area.offset.x + render->area.extent.height <= ds_image->vk.extent.height);
@ -12501,7 +12501,7 @@ radv_init_dcc(struct radv_cmd_buffer *cmd_buffer, struct radv_image *image, cons
/* Initialize the mipmap levels without DCC. */
if (size != image->planes[0].surface.meta_size) {
flush_bits |= radv_fill_buffer(cmd_buffer, image, image->bindings[0].bo,
radv_image_get_va(image, 0) + image->planes[0].surface.meta_offset + size,
image->bindings[0].addr + image->planes[0].surface.meta_offset + size,
image->planes[0].surface.meta_size - size, 0xffffffff);
}
}

4
src/amd/vulkan/radv_device.c
View file

@ -1524,7 +1524,7 @@ radv_initialise_color_surface(struct radv_device *device, struct radv_color_buff
ac_init_cb_surface(&pdev->info, &cb_state, &cb->ac);
uint32_t plane_id = iview->image->disjoint ? iview->plane_id : 0;
va = radv_image_get_va(iview->image, plane_id);
va = iview->image->bindings[plane_id].addr;
const struct ac_mutable_cb_state mutable_cb_state = {
.surf = surf,
@ -1586,7 +1586,7 @@ radv_initialise_ds_surface(const struct radv_device *device, struct radv_ds_buff
const struct ac_ds_state ds_state = {
.surf = &iview->image->planes[0].surface,
.va = radv_image_get_va(iview->image, 0),
.va = iview->image->bindings[0].addr,
.format = radv_format_to_pipe_format(iview->image->vk.format),
.width = iview->image->vk.extent.width,
.height = iview->image->vk.extent.height,

13
src/amd/vulkan/radv_image.c
View file

@ -1738,7 +1738,7 @@ radv_DestroyImage(VkDevice _device, VkImage _image, const VkAllocationCallbacks
static void
radv_bind_image_memory(struct radv_device *device, struct radv_image *image, uint32_t bind_idx,
struct radeon_winsys_bo *bo, uint64_t offset, uint64_t range)
struct radeon_winsys_bo *bo, uint64_t addr, uint64_t range)
{
struct radv_physical_device *pdev = radv_device_physical(device);
struct radv_instance *instance = radv_physical_device_instance(pdev);
@ -1746,8 +1746,7 @@ radv_bind_image_memory(struct radv_device *device, struct radv_image *image, uin
assert(bind_idx < 3);
image->bindings[bind_idx].bo = bo;
image->bindings[bind_idx].offset = offset;
image->bindings[bind_idx].addr = radv_buffer_get_va(bo) + offset;
image->bindings[bind_idx].addr = addr;
image->bindings[bind_idx].range = range;
radv_rmv_log_image_bind(device, bind_idx, radv_image_to_handle(image));
@ -1778,8 +1777,7 @@ radv_BindImageMemory2(VkDevice _device, uint32_t bindInfoCount, const VkBindImag
struct radv_image *swapchain_img =
radv_image_from_handle(wsi_common_get_image(swapchain_info->swapchain, swapchain_info->imageIndex));
radv_bind_image_memory(device, image, 0,
swapchain_img->bindings[0].bo, swapchain_img->bindings[0].offset,
radv_bind_image_memory(device, image, 0, swapchain_img->bindings[0].bo, swapchain_img->bindings[0].addr,
swapchain_img->bindings[0].range);
continue;
}
@ -1816,8 +1814,9 @@ radv_BindImageMemory2(VkDevice _device, uint32_t bindInfoCount, const VkBindImag
}
}
radv_bind_image_memory(device, image, bind_idx, mem->bo, pBindInfos[i].memoryOffset,
reqs.memoryRequirements.size);
const uint64_t addr = radv_buffer_get_va(mem->bo) + pBindInfos[i].memoryOffset;
radv_bind_image_memory(device, image, bind_idx, mem->bo, addr, reqs.memoryRequirements.size);
}
return VK_SUCCESS;
}

17
src/amd/vulkan/radv_image.h
View file

@ -33,7 +33,6 @@ struct radv_image_plane {
struct radv_image_binding {
/* Set when bound */
struct radeon_winsys_bo *bo;
VkDeviceSize offset;
uint64_t addr;
uint64_t range;
};
@ -75,12 +74,6 @@ struct radv_image {
VK_DEFINE_NONDISP_HANDLE_CASTS(radv_image, vk.base, VkImage, VK_OBJECT_TYPE_IMAGE)
static inline uint64_t
radv_image_get_va(const struct radv_image *image, uint32_t bind_idx)
{
return image->bindings[bind_idx].addr;
}
static inline bool
radv_image_extent_compare(const struct radv_image *image, const VkExtent3D *extent)
{
@ -215,7 +208,7 @@ radv_image_get_fast_clear_va(const struct radv_image *image, uint32_t base_level
{
assert(radv_image_has_clear_value(image));
uint64_t va = radv_image_get_va(image, 0);
uint64_t va = image->bindings[0].addr;
va += image->clear_value_offset + base_level * 8;
return va;
}
@ -225,7 +218,7 @@ radv_image_get_fce_pred_va(const struct radv_image *image, uint32_t base_level)
{
assert(image->fce_pred_offset != 0);
uint64_t va = radv_image_get_va(image, 0);
uint64_t va = image->bindings[0].addr;
va += image->fce_pred_offset + base_level * 8;
return va;
}
@ -235,7 +228,7 @@ radv_image_get_dcc_pred_va(const struct radv_image *image, uint32_t base_level)
{
assert(image->dcc_pred_offset != 0);
uint64_t va = radv_image_get_va(image, 0);
uint64_t va = image->bindings[0].addr;
va += image->dcc_pred_offset + base_level * 8;
return va;
}
@ -245,7 +238,7 @@ radv_get_tc_compat_zrange_va(const struct radv_image *image, uint32_t base_level
{
assert(image->tc_compat_zrange_offset != 0);
uint64_t va = radv_image_get_va(image, 0);
uint64_t va = image->bindings[0].addr;
va += image->tc_compat_zrange_offset + base_level * 4;
return va;
}
@ -255,7 +248,7 @@ radv_get_ds_clear_value_va(const struct radv_image *image, uint32_t base_level)
{
assert(radv_image_has_clear_value(image));
uint64_t va = radv_image_get_va(image, 0);
uint64_t va = image->bindings[0].addr;
va += image->clear_value_offset + base_level * 8;
return va;
}

6
src/amd/vulkan/radv_image_view.c
View file

@ -59,7 +59,7 @@ radv_set_mutable_tex_desc_fields(struct radv_device *device, struct radv_image *
struct radv_image_plane *plane = &image->planes[plane_id];
const uint32_t bind_idx = image->disjoint ? plane_id : 0;
struct radv_image_binding *binding = &image->bindings[bind_idx];
uint64_t gpu_address = binding->bo ? radv_image_get_va(image, bind_idx) + offset : 0;
uint64_t gpu_address = binding->bo ? image->bindings[bind_idx].addr + offset : 0;
const bool dcc_enabled = pdev->info.gfx_level >= GFX12 || radv_dcc_enabled(image, first_level);
const struct ac_mutable_tex_state ac_state = {
@ -200,7 +200,7 @@ gfx10_make_texture_descriptor(struct radv_device *device, struct radv_image *ima
const struct ac_fmask_state ac_state = {
.surf = &image->planes[0].surface,
.va = radv_image_get_va(image, 0),
.va = image->bindings[0].addr,
.width = width,
.height = height,
.depth = depth,
@ -304,7 +304,7 @@ gfx6_make_texture_descriptor(struct radv_device *device, struct radv_image *imag
const struct ac_fmask_state ac_fmask_state = {
.surf = &image->planes[0].surface,
.va = radv_image_get_va(image, 0),
.va = image->bindings[0].addr,
.width = width,
.height = height,
.depth = depth,

4
src/amd/vulkan/radv_rmv.c
View file

@ -606,8 +606,8 @@ radv_rmv_log_image_bind(struct radv_device *device, uint32_t bind_idx, VkImage _
struct radeon_winsys_bo *bo = image->bindings[bind_idx].bo;
simple_mtx_lock(&device->vk.memory_trace_data.token_mtx);
log_resource_bind_locked(device, (uint64_t)_image, bo->initial_domain,
radv_buffer_get_va(bo) + image->bindings[bind_idx].offset, image->bindings[bind_idx].range);
log_resource_bind_locked(device, (uint64_t)_image, bo->initial_domain, image->bindings[bind_idx].addr,
image->bindings[bind_idx].range);
simple_mtx_unlock(&device->vk.memory_trace_data.token_mtx);
}

2
src/amd/vulkan/radv_sdma.c
View file

@ -271,7 +271,7 @@ radv_sdma_get_surf(const struct radv_device *const device, const struct radv_ima
const unsigned plane_idx = radv_plane_from_aspect(aspect_mask);
const unsigned binding_idx = image->disjoint ? plane_idx : 0;
const struct radeon_surf *const surf = &image->planes[plane_idx].surface;
const uint64_t va = radv_image_get_va(image, binding_idx);
const uint64_t va = image->bindings[binding_idx].addr;
const uint32_t bpe = radv_sdma_get_bpe(image, aspect_mask);
struct radv_sdma_surf info = {
.extent =

19
src/amd/vulkan/radv_video.c
View file

@ -2069,9 +2069,8 @@ rvcn_dec_message_decode(struct radv_cmd_buffer *cmd_buffer, struct radv_video_se
if (vid->dpb_type != DPB_DYNAMIC_TIER_2)
return true;
uint64_t addr;
uint64_t addr = dpb->bindings[0].addr;
radv_cs_add_buffer(device->ws, cmd_buffer->cs, dpb->bindings[0].bo);
addr = radv_buffer_get_va(dpb->bindings[0].bo) + dpb->bindings[0].offset;
addr += dpb_array_idx * (dpb->planes[0].surface.u.gfx9.surf_slice_size + dpb->planes[1].surface.u.gfx9.surf_slice_size);
dynamic_dpb_t2->dpbCurrLo = addr;
@ -2099,7 +2098,7 @@ rvcn_dec_message_decode(struct radv_cmd_buffer *cmd_buffer, struct radv_video_se
int f_dpb_array_idx = frame_info->pReferenceSlots[i].pPictureResource->baseArrayLayer + f_dpb_iv->vk.base_array_layer;
radv_cs_add_buffer(device->ws, cmd_buffer->cs, dpb_img->bindings[0].bo);
addr = radv_buffer_get_va(dpb_img->bindings[0].bo) + dpb_img->bindings[0].offset;
addr = dpb_img->bindings[0].addr;
addr += f_dpb_array_idx * (dpb_img->planes[0].surface.u.gfx9.surf_slice_size + dpb_img->planes[1].surface.u.gfx9.surf_slice_size);
dynamic_dpb_t2->dpbAddrLo[i] = addr;
dynamic_dpb_t2->dpbAddrHi[i] = addr >> 32;
@ -2108,7 +2107,7 @@ rvcn_dec_message_decode(struct radv_cmd_buffer *cmd_buffer, struct radv_video_se
}
radv_cs_add_buffer(device->ws, cmd_buffer->cs, dpb->bindings[0].bo);
addr = radv_buffer_get_va(dpb->bindings[0].bo) + dpb->bindings[0].offset;
addr = dpb->bindings[0].addr;
addr += dpb_array_idx * (dpb->planes[0].surface.u.gfx9.surf_slice_size + dpb->planes[1].surface.u.gfx9.surf_slice_size);
dynamic_dpb_t2->dpbCurrLo = addr;
dynamic_dpb_t2->dpbCurrHi = addr >> 32;
@ -2673,8 +2672,7 @@ radv_uvd_decode_video(struct radv_cmd_buffer *cmd_buffer, const VkVideoDecodeInf
struct radv_image_view *dpb_iv =
radv_image_view_from_handle(frame_info->pSetupReferenceSlot->pPictureResource->imageViewBinding);
struct radv_image *dpb = dpb_iv->image;
send_cmd(cmd_buffer, RDECODE_CMD_DPB_BUFFER, dpb->bindings[0].bo,
radv_buffer_get_va(dpb->bindings[0].bo) + dpb->bindings[0].offset);
send_cmd(cmd_buffer, RDECODE_CMD_DPB_BUFFER, dpb->bindings[0].bo, dpb->bindings[0].addr);
}
if (vid->ctx.mem)
@ -2686,8 +2684,7 @@ radv_uvd_decode_video(struct radv_cmd_buffer *cmd_buffer, const VkVideoDecodeInf
struct radv_image_view *dst_iv = radv_image_view_from_handle(frame_info->dstPictureResource.imageViewBinding);
struct radv_image *img = dst_iv->image;
send_cmd(cmd_buffer, RDECODE_CMD_DECODING_TARGET_BUFFER, img->bindings[0].bo,
radv_buffer_get_va(img->bindings[0].bo) + img->bindings[0].offset);
send_cmd(cmd_buffer, RDECODE_CMD_DECODING_TARGET_BUFFER, img->bindings[0].bo, img->bindings[0].addr);
send_cmd(cmd_buffer, RDECODE_CMD_FEEDBACK_BUFFER, fb_bo, radv_buffer_get_va(fb_bo) + fb_offset);
if (have_it(vid))
send_cmd(cmd_buffer, RDECODE_CMD_IT_SCALING_TABLE_BUFFER, it_probs_bo,
@ -2758,8 +2755,7 @@ radv_vcn_decode_video(struct radv_cmd_buffer *cmd_buffer, const VkVideoDecodeInf
struct radv_image_view *dpb_iv =
radv_image_view_from_handle(frame_info->pSetupReferenceSlot->pPictureResource->imageViewBinding);
struct radv_image *dpb = dpb_iv->image;
send_cmd(cmd_buffer, RDECODE_CMD_DPB_BUFFER, dpb->bindings[0].bo,
radv_buffer_get_va(dpb->bindings[0].bo) + dpb->bindings[0].offset);
send_cmd(cmd_buffer, RDECODE_CMD_DPB_BUFFER, dpb->bindings[0].bo, dpb->bindings[0].addr);
}
if (vid->ctx.mem)
@ -2771,8 +2767,7 @@ radv_vcn_decode_video(struct radv_cmd_buffer *cmd_buffer, const VkVideoDecodeInf
struct radv_image_view *dst_iv = radv_image_view_from_handle(frame_info->dstPictureResource.imageViewBinding);
struct radv_image *img = dst_iv->image;
send_cmd(cmd_buffer, RDECODE_CMD_DECODING_TARGET_BUFFER, img->bindings[0].bo,
radv_buffer_get_va(img->bindings[0].bo) + img->bindings[0].offset);
send_cmd(cmd_buffer, RDECODE_CMD_DECODING_TARGET_BUFFER, img->bindings[0].bo, img->bindings[0].addr);
send_cmd(cmd_buffer, RDECODE_CMD_FEEDBACK_BUFFER, fb_bo, radv_buffer_get_va(fb_bo) + fb_offset);
if (have_it(vid))
send_cmd(cmd_buffer, RDECODE_CMD_IT_SCALING_TABLE_BUFFER, it_probs_bo,

4
src/amd/vulkan/radv_video_enc.c
View file

@ -1231,7 +1231,7 @@ radv_enc_ctx(struct radv_cmd_buffer *cmd_buffer, const VkVideoEncodeInfoKHR *inf
dpb_image_sizes(dpb, &luma_pitch, &luma_size, &chroma_size, &colloc_bytes);
radv_cs_add_buffer(device->ws, cs, dpb->bindings[0].bo);
va = radv_buffer_get_va(dpb->bindings[0].bo) + dpb->bindings[0].offset;
va = dpb->bindings[0].addr;
}
uint32_t swizzle_mode = 0;
@ -1437,7 +1437,7 @@ radv_enc_params(struct radv_cmd_buffer *cmd_buffer, const VkVideoEncodeInfoKHR *
struct radv_device *device = radv_cmd_buffer_device(cmd_buffer);
const struct radv_physical_device *pdev = radv_device_physical(device);
struct radeon_cmdbuf *cs = cmd_buffer->cs;
uint64_t va = radv_buffer_get_va(src_img->bindings[0].bo) + src_img->bindings[0].offset;
uint64_t va = src_img->bindings[0].addr;
uint64_t luma_va = va + src_img->planes[0].surface.u.gfx9.surf_offset;
uint64_t chroma_va = va + src_img->planes[1].surface.u.gfx9.surf_offset;
uint32_t pic_type;