these must be dynamically uniform but can be GPR. fixes validation on
dEQP-GLES31.functional.shaders.opaque_type_indexing.ubo.dynamically_uniform_tessellation_evaluation,
and probably really bugs doing indirect loads in divergent control flow
(when lane 0 is masked off).
no fossil-db changes.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/42056>
This optimization mostly helped BRW because 3-src instructions can't take
immediates, and BRW can't allocate scalars without wasting an entire GRF unit
per scalar. Jay has a better RA that can pack many scalars into a single GRF
unit, so allocating temporary registers for the immediates is far less likely
to lead to as much spilling as it does on BRW.
SIMD16:
Totals from 1331 (50.28% of 2647) affected shaders:
Instrs: 1665848 -> 1665514 (-0.02%); split: -0.16%, +0.14%
CodeSize: 23192072 -> 23215672 (+0.10%); split: -0.30%, +0.40%
SIMD32:
Totals from 1114 (42.09% of 2647) affected shaders:
Instrs: 1959968 -> 1960548 (+0.03%); split: -0.30%, +0.33%
CodeSize: 28004460 -> 28023468 (+0.07%); split: -0.39%, +0.46%
Number of spill instructions: 31157 -> 31161 (+0.01%); split: -0.01%, +0.03%
Number of fill instructions: 32138 -> 32130 (-0.02%); split: -0.05%, +0.02%
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/42056>
The idea here is to eliminate the flag used for the select condition,
not eliminate other flag sources.
Previously, if we had an instruction like:
gpr = SEL <not in flag> 0 <already in flag>
we would process source 0 and try to rewrite_without_flags(). Because
it's not in a flag, we think eliminating flags would be useful, so we
rewrite it. But this only eliminates the source 2 selection flag, not
the source 0 flag. It's valid to do so (but debatably useful).
However, we thought we were done, and skipped the setup that ensures
source 0's value was actually loaded into a flag.
Instead, we should just perform this optimization when processing the
selection flag (source 2). By that point, we will have properly set
up any flags for sources 0 and 1. And if source 2 is not in a flag,
we can decide to rewrite without it. Or, if it's already in a flag,
we can keep it as-is.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/42056>
delete_solo_discard was removing unconditional discards in the case
where the entire program had been optimized away. However, we can
do better: unconditional discards in the end block can be removed if
1. All render target writes after the discard have been eliminated
2. No intrinsics with side-effects (e.g. image stores) come after
See
dEQP-VK.fragment_operations.early_fragment.discard_early_fragment_tests_depth
where there's a discard at the end of the program which can be removed.
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/42056>
opt_unconditional_discards may eliminate all render target stores
due to all pixels being discarded. In that case, it tries to add
one back with a Null RT and no colour/depth/stencil outputs, just
to end the thread. In that case, we don't want to predicate it on
helper invocations - we just need a basic message to end the thread.
In particular, we already lowered nir_intrinsic_is_helper_invocation
so we don't want to emit it again, as nothing would lower it afterwards.
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/42056>
Since Metal only has 16 and 32 bit types, if 8 bit indices were used, we
would ran into asserts when trying to fetch the size from the util call.
Reviewed-by: squidbus <squidbus@proton.me>
Signed-off-by: Aitor Camacho <aitor@lunarg.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/42024>
Standard gfx-ci/linux kernel can be used for all imagination jobs.
Signed-off-by: Robert Mazur <robert.mazur@imgtec.com>
Co-authored-by: Martin Roukala <martin.roukala@mupuf.org>
Reviewed-by: Valentine Burley <valentine.burley@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41869>
Picks up drm/imagination bug fixes and enables DRM_POWERVR for TI AM62/AM68.
Signed-off-by: Robert Mazur <robert.mazur@imgtec.com>
Reviewed-by: Valentine Burley <valentine.burley@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41869>
I detected so many leaks with them, so I think running them with ASAN
is really useful, they take up to 6 minutes max.
I added a suffix to make it more obvious.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/42022>
Use recent kernel in CI-Tron.
We keep old kernel in baremetal as we have some troubles to get the
proper v3d/vc4 kernel drivers loaded.
Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/42084>
When GL_ARB_clip_control is used with a zero or very small depth range
(e.g. glDepthRange(d, d)), the viewport Z scale approaches zero. The
hardware guardband clipper divides by this scale, which can cause
incorrect clipping or dropped geometry.
V3D 7.1+ provides packet 112 (CLIPPER_Z_SCALE_AND_OFFSET_NO_GUARDBAND)
for this scenario. Use it when the absolute Z scale is below 0.01,
matching the threshold used by the v3dv Vulkan driver.
This fixes rendering with zero-width depth ranges under clip_control,
as exposed by the Vulkan CTS test:
dEQP-VK.draw.renderpass.inverted_depth_ranges.nodepthclamp_deltazero
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/42082>
Based on current v3dv support for clip control
v1: original version (Andrew Copland)
v2: update docs, really enable extension (Alejandro Piñeiro)
v3: adjusted viewport and its dirty flag (Chema Casanova)
v4: avoid dirty flags when no rasterization is enabled (Iago Toral)
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/42082>
The stencil blit path used PIPE_TEXTURE_3D directly as a ternary
condition when computing the last layer. This tests the enum constant
itself rather than the resource target, so the 3D branch is always
selected.
Check src->base.target instead so non-3D stencil resources use their
array size when selecting the layer range.
Fixes: ac207acb97 ("broadcom/vc5: Implement stencil blits using RGBA.")
Signed-off-by: yserrr <dlwognsdc610@naver.com>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/42054>
Sample locations are render pass state in Metal. In the best case
(same sample positions for all of subpass), we simply configure it
at the start and proceed as normal. For sub-optimal case (sample
positions change during subpass), we can support it by restarting
the Metal render pass with the new values.
This also interacts with the existing logic for centering sample
positions for bresenham lines. The user's custom sample positions
are prioritized, and centering applies in the default case. Some bug
fixes have also been made to prevent losing attachment contents from
render pass restarts and ensure the render pass restart happens before
other draw state is flushed.
Reviewed-by: Aitor Camacho <aitor@lunarg.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/42036>
If the view type is not an array and the image has multiple layers,
this is invalid and leads to Metal asserts. The current approach also
probably won't work for block texel views since they create a single
layer alias at the subresource. Instead we can just skip setting the
attachment descriptor levels and slices if we created a view.
Reviewed-by: Aitor Camacho <aitor@lunarg.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/42071>
This seems to fix some compiler crashes encountered on complex shaders,
possibly some attempted optimizations across blocks are going wrong.
Reviewed-by: Aitor Camacho <aitor@lunarg.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/42071>
Previously when loop analyze was guessing loop iterations based
on array/sample access, we incorrectly used the induction variable of
the loop terminator to calculate loop iterations, rather than
the induction variable that accesses the array/sample.
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/work_items/15550
Fixes: de30bfd5b8 ("nir/loop_analyze: ignore terminating induction variable in guess_loop_limit()")
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/42038>
vir_setup_def_use() pins a temp's live-interval start to ip 0 when it is
initialised from a payload register (W, centroid W, Z), which the hardware
sets up before the program runs. The range check is mis-coded with '||'
instead of '&&', so it matches every index and pins any QFILE_REG read,
not just payload reads.
On V3D 7.x the per-varying C coefficient lands in rf0 (QFILE_REG 0), so
every flat varying gets pinned live-from-start; a shader reading many
varyings then keeps them all live at once, inflating register pressure to
roughly the varying count and failing register allocation.
This fixes spec@glsl-1.30@execution@varying-packing-mixed-types on rpi5
(previously crashing on RA failure).
Fixes: ce66c9aead ("broadcom/compiler: update payload registers handling when computing live intervals")
Assisted-by: Claude Opus 4.8
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/42072>
Android builds need to pass the Meson amdgpu-virtio option explicitly.
Add BOARD_MESA3D_AMDGPU_VIRTIO handling and forward it to Meson,
defaulting to false when the board flag is not set.
Use the same quoted amdgpu.h include style as the other AMD virtio
headers so the Android build resolves the header through Mesa's
configured include paths.
Signed-off-by: Lei Huang <Lei.Huang@amd.com>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Valentine Burley <valentine.burley@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41957>
A long-running job can trip the Panfrost watchdog, resulting
in the job timing out. However, GROUP_SUBMIT does not report
that through the normal submission/fence path. GROUP_SUBMIT
has already returned, and the syncobj is signalled, without
checking the group state, making any "completion" seem like
a success.
Poll the Panthor group state from get_device_reset_status()
and surface fatal faults and timeouts as a context reset.
This was observed when running the OpenCL-CTS test
test_allocations image2d_read on Mali, which is a very
long-running compute job. Rusticl already checks the device
reset status when flushing events, so following this change,
the timeout propagates as an execution failure instead of
being silently ignored, and the subsequent read observing
partial writes, with the test ultimately failing at the
verification step.
Signed-off-by: Ahmed Hesham <ahmed.hesham@arm.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41995>
The runtime impact is negligible with fraction=20 for the regular jobs,
and the virtio job (a618-android) gets fraction=100.
Signed-off-by: Valentine Burley <valentine.burley@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41924>
Use the new common queue emulation infrastructure to advertise 2 graphics
queues when the engine name is "android framework". The second queue is
emulated: submissions to it are redirected to the real queue by the
common runtime. No kernel submitqueue is created for the emulated queue.
This mirrors the approach used by Venus and enables skiavk, which
requires multiple graphics queues to avoid racing between webview and the
Skia Vulkan renderer.
Queue teardown iterates in reverse order so emulated aliases are finished
before the real queue that owns the lock.
Test: boot to UI with skiavk using ANGLE-on-Turnip in Cuttlefish
full VK CTS run with tu_emulate_second_queue=true in CI
few relevant VK CTS tests with tu_emulate_second_queue=true on KGSL
Signed-off-by: Valentine Burley <valentine.burley@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41924>
A driver can call vk_queue_set_emulated() to mark a queue as an emulated
alias of another queue. Submissions to the emulated queue are redirected
to the real queue's driver_submit(), so the driver always sees the queue
with actual hardware resources. All submissions (from both the real and
emulated queues) are serialized through a shared mutex (real_queue->lock)
to prevent concurrent hardware access.
The emulated queue does not need driver_submit set, it will use the real
queue's driver_submit and hardware resources.
Must be called from device-init context (single-threaded). The real queue
must outlive all of its emulated aliases, since vk_queue_finish() on the
real queue destroys the lock.
Signed-off-by: Valentine Burley <valentine.burley@collabora.com>
Reviewed-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Reviewed-by: Lucas Fryzek <lfryzek@igalia.com>
Acked-by: Yiwei Zhang <zzyiwei@chromium.org>
Reviewed-by: Christian Gmeiner <cgmeiner@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41924>
tu_queue_init() calls vk_queue_init() before tu_drm_submitqueue_new().
If the DRM submitqueue creation fails, the function returns without
calling vk_queue_finish(), leaking the vk_queue resources.
Cc: mesa-stable
Signed-off-by: Valentine Burley <valentine.burley@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41924>
Credits to Toshinari Morikawa, and this supersedes
https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41904.
ring->free_submits can go unbound for heavy scenes that use 3 or more
shm pool allocs for CS storage. This change fixes to loop through the
free list for a cached entry, which is good enough in practice since
the most recently retired submit is cached at the list head.
Cc: mesa-stable
Reported-by: Toshinari Morikawa <morikawa.toshinari@jp.panasonic.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41917>
etna_try_blt_blit(..) derived the BLT sRGB decode (on read) and encode
(on write) flags independently from the source and destination formats.
A copy between two sRGB formats - such as the glReadPixels resolve of an
SRGB8_ALPHA8 framebuffer - therefore decoded to linear and re-encoded.
That roundtrip through the hardware is not bit-preserving and loses up
to 2/255 at low values, corrupting the readback of the conversions
r32f, rg32f and rgba32f to srgb8_alpha8.
Apply the sRGB conversion only when the copy crosses the sRGB/linear
boundary. Same-encoding copies stay a plain bit copy.
Fixes dEQP-GLES3.functional.fbo.blit.conversion.{r32f,rg32f,rgba32f}_to_srgb8_alpha8
Fixes: 99400f272d ("etnaviv: blt: Add BLT format conversion support")
Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41892>
