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broadcom/compiler: update payload registers handling when computing live intervals

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As for v71 the payload registers are not the same. Specifically now
rf3 is used as payload register, so this is needed to avoid rf3 being
selected as a instruction dst by the register allocator, overwriting
the payload value that could be still used.

Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25450>
This commit is contained in:
Alejandro Piñeiro 2021-10-19 23:52:30 +02:00 • committed by Marge Bot
parent d72e57fe30
commit ce66c9aead
1 changed files with 13 additions and 8 deletions
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21
src/broadcom/compiler/vir_live_variables.c
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@ -179,17 +179,22 @@ vir_setup_def_use(struct v3d_compile *c)
flags_inst = NULL;
}
/* Payload registers: r0/1/2 contain W, centroid W,
* and Z at program start. Register allocation will
* force their nodes to R0/1/2.
/* Payload registers: for fragment shaders, W,
* centroid W, and Z will be initialized in r0/1/2
* until v42, or r1/r2/r3 since v71.
*
* For compute shaders, payload is in r0/r2 up to v42,
* r2/r3 since v71.
*
* Register allocation will force their nodes to those
* registers.
*/
if (inst->src[0].file == QFILE_REG) {
switch (inst->src[0].index) {
case 0:
case 1:
case 2:
uint32_t min_payload_r = c->devinfo->ver >= 71 ? 1 : 0;
uint32_t max_payload_r = c->devinfo->ver >= 71 ? 3 : 2;
if (inst->src[0].index >= min_payload_r ||
inst->src[0].index <= max_payload_r) {
c->temp_start[inst->dst.index] = 0;
break;
}
}