Commit graph

71935 commits

Author SHA1 Message Date
Timur Kristóf
cad4e7d2e7 radv, radeonsi: Move GFX6-7 CB clamp issue to ac_gpu_info
To improve consistency between the two drivers.
This excludes Hawaii from the workaround on RADV.

Also add the same to ac_null_device_create().

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38304>
2025-11-15 14:24:59 +01:00
Timur Kristóf
35b376b942 radeonsi: Respect if rbplus is allowed when choosing color formats
For consistency with RADV.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38304>
2025-11-15 14:24:52 +01:00
Timur Kristóf
4f793d2515 radeonsi: Inline si_choose_spi_color_formats
Will be necessary for the subsequent commit.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38304>
2025-11-15 14:24:46 +01:00
Marek Olšák
f9341082a2 nir,glsl,zink: remove the option nir_io_separate_clip_cull_distance_arrays
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This calls nir_separate_merged_clip_cull_io in zink, which is better
than having to handle separate clip & cull arrays in all passes.

Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38452>
2025-11-15 03:30:10 +00:00
Marek Olšák
e372365cf4 nir: rename nir_copy_prop -> nir_opt_copy_prop
Acked-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38411>
2025-11-15 02:16:38 +00:00
Lucas Fryzek
b75b0ce7b2 lp: Implement gallium depth_bounds_test capability
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Support for this capability in llvmpipe expose
support for GL_EXT_depth_bounds_test, as well as supporting
the `depthBounds` device feature in lavapipe.

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36487>
2025-11-14 09:43:22 +00:00
Daniel Schürmann
7ee1932309 treewide: Never preserve nir_metadata_dominance without nir_metadata_block_index
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38367>
2025-11-14 09:09:14 +00:00
Adrián Larumbe
a24f490488 panfrost: match a GL object's maximum label length to KMD uAPI limit
At present, this is the value mandated by the KMD's uAPI, or 4096 bytes.

Signed-off-by: Adrián Larumbe <adrian.larumbe@collabora.com>
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Reviewed-by: Eric R. Smith <eric.smith@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38027>
2025-11-13 19:16:15 +00:00
Adrián Larumbe
a68c584d70 mesa: gallium: make GL object maximum label length a pipescreen cap
Commit a4ffd2395f ("mesa: Implement label sharing from GL objects with
UM drivers") enabled GL clients to tag objects at a UM driver level. In
the case of Panfrost, and for both KMDs, maximum label size is set to
4096, but the Mesa limit is much lower.

Since glObjectLabel() allocates object labels dynamically, there's no
need to have this value chiseled in stone, so allow Gallium driver
implementers to set their own limit through a pipe screen capability.

Keep the same default maximum label length as before.

Signed-off-by: Adrián Larumbe <adrian.larumbe@collabora.com>
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Reviewed-by: Eric R. Smith <eric.smith@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38027>
2025-11-13 19:16:15 +00:00
Pohsiang (John) Hsu
e9757d25e0 mediafoundation: propagate input timestamp / duration to output
Reviewed-by: Sil Vilerino <sivileri@microsoft.com>

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/14261
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38427>
2025-11-13 16:31:06 +00:00
Benjamin Cheng
b4ae11ee42 ac,radeonsi/vcn,radv/video: Drop signature param
The signature is not very useful, and is unnecessary CPU overhead.

Reviewed-by: David Rosca <david.rosca@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38372>
2025-11-13 14:35:58 +00:00
Gert Wollny
79e4323cf0 r600/sfn: Don't start a new ALU-CF if LDS pipeline loads are pending
Fixes: e57643cf (r600/sfn: Add handling for R600 indirect access alias handling)

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38398>
2025-11-13 11:17:51 +00:00
Qiang Yu
ece827d53b radeonsi: enable EXT_mesh_shader
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38044>
2025-11-13 01:30:27 +00:00
Qiang Yu
3d01529316 radeonsi: si_calculate_max_simd_waves support task and mesh shader
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38044>
2025-11-13 01:30:25 +00:00
Qiang Yu
4495978932 radeonsi: handle maybe per primitive input for fragment shader
Some fragment shader may be per-primitive when mesh pipeline,
per-vertex when vertex pipeline. We sort these inputs always
after other per-vertex inputs in nir_recompute_io_bases, so
fragment shader code is same, just need to set different reg.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38044>
2025-11-13 01:30:24 +00:00
Qiang Yu
1733dddee9 radeonsi: add mesh shader functions
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38044>
2025-11-13 01:30:23 +00:00
Qiang Yu
4c220f9745 radeonsi: add si_emit_rasterizer_prim_state_for_mesh
To be used by mesh pipeline.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38044>
2025-11-13 01:30:22 +00:00
Qiang Yu
4ee6553767 radeonsi: add si_update_shaders_for_mesh
To be used by mesh pipeline.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38044>
2025-11-13 01:30:20 +00:00
Qiang Yu
8410970e8b radeonsi: add si_update_shaders_shared_by_vertex_and_mesh_pipe
Move shared part of si_update_shaders to this function,
no implementation change.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38044>
2025-11-13 01:30:19 +00:00
Qiang Yu
87715a1c8c radeonsi: compute culldist_mask and clipdist_mask for mesh shader
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38044>
2025-11-13 01:30:18 +00:00
Qiang Yu
355e499b52 radeonsi: si_emit_buffered_compute_sh_regs support gang cs
To be used by task shader gang cs.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38044>
2025-11-13 01:30:17 +00:00
Qiang Yu
b713f453c6 radeonsi: lower mesh shader local id and workgroup id
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38044>
2025-11-13 01:30:15 +00:00
Qiang Yu
2e025d66c3 radeonsi: add task shader queries support
Need to emit query start/stop/sample packets in compute
queue.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38044>
2025-11-13 01:30:15 +00:00
Qiang Yu
9a31151436 radeonsi: increase task wait count when emit barrier
It will be waited by task queue too.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38044>
2025-11-13 01:30:15 +00:00
Qiang Yu
c0f6e97d6c radeonsi: implement nir_intrinsic_load_ring_mesh_scratch_amd
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38044>
2025-11-13 01:30:13 +00:00
Qiang Yu
5048216b43 radeonsi: init mesh shader ngg info
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38044>
2025-11-13 01:30:13 +00:00
Qiang Yu
432f66a7b6 radeonsi: add si_create_compute_state_for_nir
To be shared by task shader state creation.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38044>
2025-11-13 01:30:11 +00:00
Qiang Yu
263cce11bd radeonsi: move shared_size to si_shader_variant_info
For mesh shader which know this after ac_nir_lower_ngg_mesh.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38044>
2025-11-13 01:30:08 +00:00
Qiang Yu
e3ab6249f2 radeonsi: export si_init_compute_preamble_state for task shader
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38044>
2025-11-13 01:30:03 +00:00
Qiang Yu
0ee4747678 radeonsi: log cs support mesh shader
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38044>
2025-11-13 01:30:02 +00:00
Qiang Yu
f1138c18ac radeonsi: implement task ring nir intrinsic lower
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38044>
2025-11-13 01:30:02 +00:00
Qiang Yu
e819554b2a radeonsi: add task/mesh shader context states
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38044>
2025-11-13 01:30:00 +00:00
Qiang Yu
cffc40051d winsys/amdgpu: support gang submit for kernel queue
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38044>
2025-11-13 01:29:58 +00:00
Qiang Yu
963ad4bb4e radeonsi: add si_emit_task_shader_pointers
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38044>
2025-11-13 01:29:58 +00:00
Qiang Yu
66cd3f1b52 radeonsi: add si_upload_shader_descriptos
To be shared with gfx, mesh and compute pipeline.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38044>
2025-11-13 01:29:55 +00:00
Qiang Yu
12f33b596c radeonsi: export si_setup_compute_scratch_buffer for task shader
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38044>
2025-11-13 01:29:54 +00:00
Qiang Yu
915d5167af radeonsi: change arg for si_cp_dma_prefetch
To be used by gang cs too.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38044>
2025-11-13 01:29:52 +00:00
Yonggang Luo
8c427aae92 util: Remove unused ALIGN function to prevent future use
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The #undef ALIGN is also not needed anymore, remove it.

Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Acked-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38365>
2025-11-12 21:58:41 +00:00
Yonggang Luo
ecb0ccf603 treewide: Replace calling to function ALIGN with align
This is done by grep ALIGN( to align(

docs,*.xml,blake3 is excluded

Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Acked-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38365>
2025-11-12 21:58:40 +00:00
Yonggang Luo
03a32b3fe2 radeon/drm: Replace all usage of ALIGN to align and remove ALIGN macro
As now all ALIGN usage is on 32bit integer

Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Acked-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38365>
2025-11-12 21:58:38 +00:00
Yonggang Luo
0fe6143a77 radeon/drm: use align64 for 64 bits input instead of ALIGN
Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Acked-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38365>
2025-11-12 21:58:38 +00:00
Konstantin Seurer
de32f9275f treewide: add & use parent instr helpers
We add a bunch of new helpers to avoid the need to touch >parent_instr,
including the full set of:

* nir_def_is_*
* nir_def_as_*_or_null
* nir_def_as_* [assumes the right instr type]
* nir_src_is_*
* nir_src_as_*
* nir_scalar_is_*
* nir_scalar_as_*

Plus nir_def_instr() where there's no more suitable helper.

Also an existing helper is renamed to unify all the names, while we're
churning the tree:

* nir_src_as_alu_instr -> nir_src_as_alu

..and then we port the tree to use the helpers as much as possible, using
nir_def_instr() where that does not work.

Acked-by: Marek Olšák <maraeo@gmail.com>

---

To eliminate nir_def::parent_instr we need to churn the tree anyway, so I'm
taking this opportunity to clean up a lot of NIR patterns.

Co-authored-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38313>
2025-11-12 21:22:13 +00:00
Marek Olšák
7d22e4c7ba gallium/noop: don't unref buffers passed to set_vertex_buffers to fix crashes
this code is invalid after the refcounting rework

Fixes: b3133e250e - gallium: add pipe_context::resource_release to eliminate buffer refcounting

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38329>
2025-11-12 15:02:20 +00:00
Timur Kristóf
0651fd4e6d radeonsi/ci, zink+radv/ci: Remove GS primitive_counter tests from flakes
Some checks are pending
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These should be fixed now.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38364>
2025-11-12 13:40:55 +00:00
Faith Ekstrand
6ee4ea5ea3 nir: Add a type parameter to nir_lower_point_size()
On Mali, we need not only clamp but also convert to float16 on Valhall+.
We could have a separate pass for this but it fits in nicely with the
rest of nir_lower_point_size() so we might as well put it there.

Acked-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38379>
2025-11-12 01:34:36 +00:00
Sviatoslav Peleshko
f03432c81a mesa,driconf: Add WA to initialize vertex program outputs to vec4(0,0,0,1)
Per ARB_vertex_program spec result registers are 4-component and initially
undefined, and the FF fragment program expects its intputs to be
4-component too. So, if the client's vertex program does not write the
whole vector it will cause misrenderings unless the same client also
supplies fragment program that expects less than 4 componens.

This commit adds a workaround that initializes results to vec4(0, 0, 0, 1)
which seems to be an expected behavior for such clients.

Cc: mesa-stable
Signed-off-by: Sviatoslav Peleshko <sviatoslav.peleshko@globallogic.com>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38295>
2025-11-11 22:16:46 +00:00
Eric Engestrom
f30e5ff44b ci: uprev vkd3d
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03cca4cd97...4acd227131

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38370>
2025-11-11 20:15:21 +00:00
Daniel Schürmann
5682e39e6b amd: enable load/store_shared2_amd for GFX6
Totals from 1509 (2.43% of 62200) affected shaders: (Pitcairn)

MaxWaves: 8078 -> 8057 (-0.26%); split: +0.09%, -0.35%
Instrs: 977182 -> 951746 (-2.60%); split: -2.62%, +0.02%
CodeSize: 4951468 -> 4758192 (-3.90%); split: -3.92%, +0.01%
SGPRs: 76704 -> 76696 (-0.01%)
VGPRs: 81092 -> 81068 (-0.03%); split: -0.34%, +0.31%
Latency: 11663237 -> 11526070 (-1.18%); split: -1.19%, +0.01%
InvThroughput: 6198904 -> 6114851 (-1.36%); split: -1.43%, +0.07%
VClause: 26656 -> 26655 (-0.00%); split: -0.05%, +0.05%
SClause: 22304 -> 22307 (+0.01%); split: -0.03%, +0.04%
Copies: 107503 -> 109564 (+1.92%); split: -0.23%, +2.15%
Branches: 22917 -> 22918 (+0.00%)
PreSGPRs: 42246 -> 42242 (-0.01%); split: -0.01%, +0.00%
PreVGPRs: 64561 -> 64761 (+0.31%); split: -0.01%, +0.32%
VALU: 600285 -> 601139 (+0.14%); split: -0.26%, +0.40%
SALU: 130622 -> 130851 (+0.18%); split: -0.16%, +0.33%
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37682>
2025-11-11 17:12:17 +00:00
Roland Scheidegger
d6fd8b4201 llvmpipe: do bounds checking for shared memory
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Just compare against the size that was declared.
This is probably overkill. I couldn't figure out what vulkan says wrt
OOB access of shared memory. D3D however (which is very strict about
these things) says that for TGSM writes the entire contents of the TGSM
becomes undefined, for reads the result is undefined. Hence, rather
than masking out such accesses, to avoid the segfaults it would be
enough to just clamp the offsets to valid values.
nir doesn't seem easily able to tell us if an access is guaranteed
in-bound (unlike for ssbo access), so assume always potentially OOB.

v2: fix rusticl - for cl we don't know the shared size at compilation
time, this is only provided at launch_grid() time, the nir shader info
shared_size might be zero. Hence pass through the size via cs jit
context, there already actually was a member in there which looks
like it was intended for that (interestingly enough, the cs jit context
was actually unused, since resources are passed elsewhere nowadays).

Reviewed-by: Brian Paul <brian.paul@broadcom.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38307>
2025-11-11 09:28:30 +00:00
Christian Gmeiner
9c31b9b342 etnaviv: blt: Add Z16_UNORM format translation
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Passes dEQP-GLES3.functional.fbo.msaa.4_samples.depth_component16

Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38362>
2025-11-11 00:30:21 +01:00